davinci_cpdma.h 4.0 KB

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  1. /*
  2. * Texas Instruments CPDMA Driver
  3. *
  4. * Copyright (C) 2010 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #ifndef __DAVINCI_CPDMA_H__
  16. #define __DAVINCI_CPDMA_H__
  17. #define CPDMA_MAX_CHANNELS BITS_PER_LONG
  18. #define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7)
  19. #define CPDMA_RX_VLAN_ENCAP BIT(19)
  20. #define CPDMA_EOI_RX_THRESH 0x0
  21. #define CPDMA_EOI_RX 0x1
  22. #define CPDMA_EOI_TX 0x2
  23. #define CPDMA_EOI_MISC 0x3
  24. struct cpdma_params {
  25. struct device *dev;
  26. void __iomem *dmaregs;
  27. void __iomem *txhdp, *rxhdp, *txcp, *rxcp;
  28. void __iomem *rxthresh, *rxfree;
  29. int num_chan;
  30. bool has_soft_reset;
  31. int min_packet_size;
  32. u32 desc_mem_phys;
  33. u32 desc_hw_addr;
  34. int desc_mem_size;
  35. int desc_align;
  36. u32 bus_freq_mhz;
  37. u32 descs_pool_size;
  38. /*
  39. * Some instances of embedded cpdma controllers have extra control and
  40. * status registers. The following flag enables access to these
  41. * "extended" registers.
  42. */
  43. bool has_ext_regs;
  44. };
  45. struct cpdma_chan_stats {
  46. u32 head_enqueue;
  47. u32 tail_enqueue;
  48. u32 pad_enqueue;
  49. u32 misqueued;
  50. u32 desc_alloc_fail;
  51. u32 pad_alloc_fail;
  52. u32 runt_receive_buff;
  53. u32 runt_transmit_buff;
  54. u32 empty_dequeue;
  55. u32 busy_dequeue;
  56. u32 good_dequeue;
  57. u32 requeue;
  58. u32 teardown_dequeue;
  59. };
  60. struct cpdma_ctlr;
  61. struct cpdma_chan;
  62. typedef void (*cpdma_handler_fn)(void *token, int len, int status);
  63. struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
  64. int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
  65. int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
  66. int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
  67. struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
  68. cpdma_handler_fn handler, int rx_type);
  69. int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan);
  70. int cpdma_chan_destroy(struct cpdma_chan *chan);
  71. int cpdma_chan_start(struct cpdma_chan *chan);
  72. int cpdma_chan_stop(struct cpdma_chan *chan);
  73. int cpdma_chan_get_stats(struct cpdma_chan *chan,
  74. struct cpdma_chan_stats *stats);
  75. int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
  76. int len, int directed);
  77. int cpdma_chan_process(struct cpdma_chan *chan, int quota);
  78. int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
  79. void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
  80. int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
  81. u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr);
  82. u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr);
  83. bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
  84. int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight);
  85. int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate);
  86. u32 cpdma_chan_get_rate(struct cpdma_chan *ch);
  87. u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr);
  88. enum cpdma_control {
  89. CPDMA_TX_RLIM, /* read-write */
  90. CPDMA_CMD_IDLE, /* write-only */
  91. CPDMA_COPY_ERROR_FRAMES, /* read-write */
  92. CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
  93. CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
  94. CPDMA_TX_PRIO_FIXED, /* read-write */
  95. CPDMA_STAT_IDLE, /* read-only */
  96. CPDMA_STAT_TX_ERR_CHAN, /* read-only */
  97. CPDMA_STAT_TX_ERR_CODE, /* read-only */
  98. CPDMA_STAT_RX_ERR_CHAN, /* read-only */
  99. CPDMA_STAT_RX_ERR_CODE, /* read-only */
  100. CPDMA_RX_BUFFER_OFFSET, /* read-write */
  101. };
  102. int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
  103. int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
  104. int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr);
  105. void cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc);
  106. int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr);
  107. int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr);
  108. #endif