qede_ptp.c 14 KB

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  1. /* QLogic qede NIC Driver
  2. * Copyright (c) 2015-2017 QLogic Corporation
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and /or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include "qede_ptp.h"
  33. struct qede_ptp {
  34. const struct qed_eth_ptp_ops *ops;
  35. struct ptp_clock_info clock_info;
  36. struct cyclecounter cc;
  37. struct timecounter tc;
  38. struct ptp_clock *clock;
  39. struct work_struct work;
  40. struct qede_dev *edev;
  41. struct sk_buff *tx_skb;
  42. /* ptp spinlock is used for protecting the cycle/time counter fields
  43. * and, also for serializing the qed PTP API invocations.
  44. */
  45. spinlock_t lock;
  46. bool hw_ts_ioctl_called;
  47. u16 tx_type;
  48. u16 rx_filter;
  49. };
  50. /**
  51. * qede_ptp_adjfreq
  52. * @ptp: the ptp clock structure
  53. * @ppb: parts per billion adjustment from base
  54. *
  55. * Adjust the frequency of the ptp cycle counter by the
  56. * indicated ppb from the base frequency.
  57. */
  58. static int qede_ptp_adjfreq(struct ptp_clock_info *info, s32 ppb)
  59. {
  60. struct qede_ptp *ptp = container_of(info, struct qede_ptp, clock_info);
  61. struct qede_dev *edev = ptp->edev;
  62. int rc;
  63. __qede_lock(edev);
  64. if (edev->state == QEDE_STATE_OPEN) {
  65. spin_lock_bh(&ptp->lock);
  66. rc = ptp->ops->adjfreq(edev->cdev, ppb);
  67. spin_unlock_bh(&ptp->lock);
  68. } else {
  69. DP_ERR(edev, "PTP adjfreq called while interface is down\n");
  70. rc = -EFAULT;
  71. }
  72. __qede_unlock(edev);
  73. return rc;
  74. }
  75. static int qede_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
  76. {
  77. struct qede_dev *edev;
  78. struct qede_ptp *ptp;
  79. ptp = container_of(info, struct qede_ptp, clock_info);
  80. edev = ptp->edev;
  81. DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP adjtime called, delta = %llx\n",
  82. delta);
  83. spin_lock_bh(&ptp->lock);
  84. timecounter_adjtime(&ptp->tc, delta);
  85. spin_unlock_bh(&ptp->lock);
  86. return 0;
  87. }
  88. static int qede_ptp_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
  89. {
  90. struct qede_dev *edev;
  91. struct qede_ptp *ptp;
  92. u64 ns;
  93. ptp = container_of(info, struct qede_ptp, clock_info);
  94. edev = ptp->edev;
  95. spin_lock_bh(&ptp->lock);
  96. ns = timecounter_read(&ptp->tc);
  97. spin_unlock_bh(&ptp->lock);
  98. DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP gettime called, ns = %llu\n", ns);
  99. *ts = ns_to_timespec64(ns);
  100. return 0;
  101. }
  102. static int qede_ptp_settime(struct ptp_clock_info *info,
  103. const struct timespec64 *ts)
  104. {
  105. struct qede_dev *edev;
  106. struct qede_ptp *ptp;
  107. u64 ns;
  108. ptp = container_of(info, struct qede_ptp, clock_info);
  109. edev = ptp->edev;
  110. ns = timespec64_to_ns(ts);
  111. DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP settime called, ns = %llu\n", ns);
  112. /* Re-init the timecounter */
  113. spin_lock_bh(&ptp->lock);
  114. timecounter_init(&ptp->tc, &ptp->cc, ns);
  115. spin_unlock_bh(&ptp->lock);
  116. return 0;
  117. }
  118. /* Enable (or disable) ancillary features of the phc subsystem */
  119. static int qede_ptp_ancillary_feature_enable(struct ptp_clock_info *info,
  120. struct ptp_clock_request *rq,
  121. int on)
  122. {
  123. struct qede_dev *edev;
  124. struct qede_ptp *ptp;
  125. ptp = container_of(info, struct qede_ptp, clock_info);
  126. edev = ptp->edev;
  127. DP_ERR(edev, "PHC ancillary features are not supported\n");
  128. return -ENOTSUPP;
  129. }
  130. static void qede_ptp_task(struct work_struct *work)
  131. {
  132. struct skb_shared_hwtstamps shhwtstamps;
  133. struct qede_dev *edev;
  134. struct qede_ptp *ptp;
  135. u64 timestamp, ns;
  136. int rc;
  137. ptp = container_of(work, struct qede_ptp, work);
  138. edev = ptp->edev;
  139. /* Read Tx timestamp registers */
  140. spin_lock_bh(&ptp->lock);
  141. rc = ptp->ops->read_tx_ts(edev->cdev, &timestamp);
  142. spin_unlock_bh(&ptp->lock);
  143. if (rc) {
  144. /* Reschedule to keep checking for a valid timestamp value */
  145. schedule_work(&ptp->work);
  146. return;
  147. }
  148. ns = timecounter_cyc2time(&ptp->tc, timestamp);
  149. memset(&shhwtstamps, 0, sizeof(shhwtstamps));
  150. shhwtstamps.hwtstamp = ns_to_ktime(ns);
  151. skb_tstamp_tx(ptp->tx_skb, &shhwtstamps);
  152. dev_kfree_skb_any(ptp->tx_skb);
  153. ptp->tx_skb = NULL;
  154. clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
  155. DP_VERBOSE(edev, QED_MSG_DEBUG,
  156. "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
  157. timestamp, ns);
  158. }
  159. /* Read the PHC. This API is invoked with ptp_lock held. */
  160. static u64 qede_ptp_read_cc(const struct cyclecounter *cc)
  161. {
  162. struct qede_dev *edev;
  163. struct qede_ptp *ptp;
  164. u64 phc_cycles;
  165. int rc;
  166. ptp = container_of(cc, struct qede_ptp, cc);
  167. edev = ptp->edev;
  168. rc = ptp->ops->read_cc(edev->cdev, &phc_cycles);
  169. if (rc)
  170. WARN_ONCE(1, "PHC read err %d\n", rc);
  171. DP_VERBOSE(edev, QED_MSG_DEBUG, "PHC read cycles = %llu\n", phc_cycles);
  172. return phc_cycles;
  173. }
  174. static int qede_ptp_cfg_filters(struct qede_dev *edev)
  175. {
  176. enum qed_ptp_hwtstamp_tx_type tx_type = QED_PTP_HWTSTAMP_TX_ON;
  177. enum qed_ptp_filter_type rx_filter = QED_PTP_FILTER_NONE;
  178. struct qede_ptp *ptp = edev->ptp;
  179. if (!ptp)
  180. return -EIO;
  181. if (!ptp->hw_ts_ioctl_called) {
  182. DP_INFO(edev, "TS IOCTL not called\n");
  183. return 0;
  184. }
  185. switch (ptp->tx_type) {
  186. case HWTSTAMP_TX_ON:
  187. edev->flags |= QEDE_TX_TIMESTAMPING_EN;
  188. tx_type = QED_PTP_HWTSTAMP_TX_ON;
  189. break;
  190. case HWTSTAMP_TX_OFF:
  191. edev->flags &= ~QEDE_TX_TIMESTAMPING_EN;
  192. tx_type = QED_PTP_HWTSTAMP_TX_OFF;
  193. break;
  194. case HWTSTAMP_TX_ONESTEP_SYNC:
  195. DP_ERR(edev, "One-step timestamping is not supported\n");
  196. return -ERANGE;
  197. }
  198. spin_lock_bh(&ptp->lock);
  199. switch (ptp->rx_filter) {
  200. case HWTSTAMP_FILTER_NONE:
  201. rx_filter = QED_PTP_FILTER_NONE;
  202. break;
  203. case HWTSTAMP_FILTER_ALL:
  204. case HWTSTAMP_FILTER_SOME:
  205. case HWTSTAMP_FILTER_NTP_ALL:
  206. ptp->rx_filter = HWTSTAMP_FILTER_NONE;
  207. rx_filter = QED_PTP_FILTER_ALL;
  208. break;
  209. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  210. ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
  211. rx_filter = QED_PTP_FILTER_V1_L4_EVENT;
  212. break;
  213. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  214. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  215. ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
  216. /* Initialize PTP detection for UDP/IPv4 events */
  217. rx_filter = QED_PTP_FILTER_V1_L4_GEN;
  218. break;
  219. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  220. ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
  221. rx_filter = QED_PTP_FILTER_V2_L4_EVENT;
  222. break;
  223. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  224. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  225. ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
  226. /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
  227. rx_filter = QED_PTP_FILTER_V2_L4_GEN;
  228. break;
  229. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  230. ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
  231. rx_filter = QED_PTP_FILTER_V2_L2_EVENT;
  232. break;
  233. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  234. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  235. ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
  236. /* Initialize PTP detection L2 events */
  237. rx_filter = QED_PTP_FILTER_V2_L2_GEN;
  238. break;
  239. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  240. ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
  241. rx_filter = QED_PTP_FILTER_V2_EVENT;
  242. break;
  243. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  244. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  245. ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
  246. /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
  247. rx_filter = QED_PTP_FILTER_V2_GEN;
  248. break;
  249. }
  250. ptp->ops->cfg_filters(edev->cdev, rx_filter, tx_type);
  251. spin_unlock_bh(&ptp->lock);
  252. return 0;
  253. }
  254. int qede_ptp_hw_ts(struct qede_dev *edev, struct ifreq *ifr)
  255. {
  256. struct hwtstamp_config config;
  257. struct qede_ptp *ptp;
  258. int rc;
  259. ptp = edev->ptp;
  260. if (!ptp)
  261. return -EIO;
  262. if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
  263. return -EFAULT;
  264. DP_VERBOSE(edev, QED_MSG_DEBUG,
  265. "HWTSTAMP IOCTL: Requested tx_type = %d, requested rx_filters = %d\n",
  266. config.tx_type, config.rx_filter);
  267. if (config.flags) {
  268. DP_ERR(edev, "config.flags is reserved for future use\n");
  269. return -EINVAL;
  270. }
  271. ptp->hw_ts_ioctl_called = 1;
  272. ptp->tx_type = config.tx_type;
  273. ptp->rx_filter = config.rx_filter;
  274. rc = qede_ptp_cfg_filters(edev);
  275. if (rc)
  276. return rc;
  277. config.rx_filter = ptp->rx_filter;
  278. return copy_to_user(ifr->ifr_data, &config,
  279. sizeof(config)) ? -EFAULT : 0;
  280. }
  281. int qede_ptp_get_ts_info(struct qede_dev *edev, struct ethtool_ts_info *info)
  282. {
  283. struct qede_ptp *ptp = edev->ptp;
  284. if (!ptp) {
  285. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  286. SOF_TIMESTAMPING_RX_SOFTWARE |
  287. SOF_TIMESTAMPING_SOFTWARE;
  288. info->phc_index = -1;
  289. return 0;
  290. }
  291. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  292. SOF_TIMESTAMPING_RX_SOFTWARE |
  293. SOF_TIMESTAMPING_SOFTWARE |
  294. SOF_TIMESTAMPING_TX_HARDWARE |
  295. SOF_TIMESTAMPING_RX_HARDWARE |
  296. SOF_TIMESTAMPING_RAW_HARDWARE;
  297. if (ptp->clock)
  298. info->phc_index = ptp_clock_index(ptp->clock);
  299. else
  300. info->phc_index = -1;
  301. info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
  302. BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
  303. BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
  304. BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
  305. BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
  306. BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
  307. BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
  308. BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
  309. BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
  310. BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
  311. BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
  312. BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
  313. BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
  314. info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
  315. return 0;
  316. }
  317. void qede_ptp_disable(struct qede_dev *edev)
  318. {
  319. struct qede_ptp *ptp;
  320. ptp = edev->ptp;
  321. if (!ptp)
  322. return;
  323. if (ptp->clock) {
  324. ptp_clock_unregister(ptp->clock);
  325. ptp->clock = NULL;
  326. }
  327. /* Cancel PTP work queue. Should be done after the Tx queues are
  328. * drained to prevent additional scheduling.
  329. */
  330. cancel_work_sync(&ptp->work);
  331. if (ptp->tx_skb) {
  332. dev_kfree_skb_any(ptp->tx_skb);
  333. ptp->tx_skb = NULL;
  334. }
  335. /* Disable PTP in HW */
  336. spin_lock_bh(&ptp->lock);
  337. ptp->ops->disable(edev->cdev);
  338. spin_unlock_bh(&ptp->lock);
  339. kfree(ptp);
  340. edev->ptp = NULL;
  341. }
  342. static int qede_ptp_init(struct qede_dev *edev, bool init_tc)
  343. {
  344. struct qede_ptp *ptp;
  345. int rc;
  346. ptp = edev->ptp;
  347. if (!ptp)
  348. return -EINVAL;
  349. spin_lock_init(&ptp->lock);
  350. /* Configure PTP in HW */
  351. rc = ptp->ops->enable(edev->cdev);
  352. if (rc) {
  353. DP_INFO(edev, "PTP HW enable failed\n");
  354. return rc;
  355. }
  356. /* Init work queue for Tx timestamping */
  357. INIT_WORK(&ptp->work, qede_ptp_task);
  358. /* Init cyclecounter and timecounter. This is done only in the first
  359. * load. If done in every load, PTP application will fail when doing
  360. * unload / load (e.g. MTU change) while it is running.
  361. */
  362. if (init_tc) {
  363. memset(&ptp->cc, 0, sizeof(ptp->cc));
  364. ptp->cc.read = qede_ptp_read_cc;
  365. ptp->cc.mask = CYCLECOUNTER_MASK(64);
  366. ptp->cc.shift = 0;
  367. ptp->cc.mult = 1;
  368. timecounter_init(&ptp->tc, &ptp->cc,
  369. ktime_to_ns(ktime_get_real()));
  370. }
  371. return rc;
  372. }
  373. int qede_ptp_enable(struct qede_dev *edev, bool init_tc)
  374. {
  375. struct qede_ptp *ptp;
  376. int rc;
  377. ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
  378. if (!ptp) {
  379. DP_INFO(edev, "Failed to allocate struct for PTP\n");
  380. return -ENOMEM;
  381. }
  382. ptp->edev = edev;
  383. ptp->ops = edev->ops->ptp;
  384. if (!ptp->ops) {
  385. DP_INFO(edev, "PTP enable failed\n");
  386. rc = -EIO;
  387. goto err1;
  388. }
  389. edev->ptp = ptp;
  390. rc = qede_ptp_init(edev, init_tc);
  391. if (rc)
  392. goto err1;
  393. qede_ptp_cfg_filters(edev);
  394. /* Fill the ptp_clock_info struct and register PTP clock */
  395. ptp->clock_info.owner = THIS_MODULE;
  396. snprintf(ptp->clock_info.name, 16, "%s", edev->ndev->name);
  397. ptp->clock_info.max_adj = QED_MAX_PHC_DRIFT_PPB;
  398. ptp->clock_info.n_alarm = 0;
  399. ptp->clock_info.n_ext_ts = 0;
  400. ptp->clock_info.n_per_out = 0;
  401. ptp->clock_info.pps = 0;
  402. ptp->clock_info.adjfreq = qede_ptp_adjfreq;
  403. ptp->clock_info.adjtime = qede_ptp_adjtime;
  404. ptp->clock_info.gettime64 = qede_ptp_gettime;
  405. ptp->clock_info.settime64 = qede_ptp_settime;
  406. ptp->clock_info.enable = qede_ptp_ancillary_feature_enable;
  407. ptp->clock = ptp_clock_register(&ptp->clock_info, &edev->pdev->dev);
  408. if (IS_ERR(ptp->clock)) {
  409. DP_ERR(edev, "PTP clock registration failed\n");
  410. qede_ptp_disable(edev);
  411. rc = -EINVAL;
  412. goto err2;
  413. }
  414. return 0;
  415. err1:
  416. kfree(ptp);
  417. err2:
  418. edev->ptp = NULL;
  419. return rc;
  420. }
  421. void qede_ptp_tx_ts(struct qede_dev *edev, struct sk_buff *skb)
  422. {
  423. struct qede_ptp *ptp;
  424. ptp = edev->ptp;
  425. if (!ptp)
  426. return;
  427. if (test_and_set_bit_lock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags))
  428. return;
  429. if (unlikely(!(edev->flags & QEDE_TX_TIMESTAMPING_EN))) {
  430. DP_NOTICE(edev,
  431. "Tx timestamping was not enabled, this packet will not be timestamped\n");
  432. } else if (unlikely(ptp->tx_skb)) {
  433. DP_NOTICE(edev,
  434. "The device supports only a single outstanding packet to timestamp, this packet will not be timestamped\n");
  435. } else {
  436. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  437. /* schedule check for Tx timestamp */
  438. ptp->tx_skb = skb_get(skb);
  439. schedule_work(&ptp->work);
  440. }
  441. }
  442. void qede_ptp_rx_ts(struct qede_dev *edev, struct sk_buff *skb)
  443. {
  444. struct qede_ptp *ptp;
  445. u64 timestamp, ns;
  446. int rc;
  447. ptp = edev->ptp;
  448. if (!ptp)
  449. return;
  450. spin_lock_bh(&ptp->lock);
  451. rc = ptp->ops->read_rx_ts(edev->cdev, &timestamp);
  452. if (rc) {
  453. spin_unlock_bh(&ptp->lock);
  454. DP_INFO(edev, "Invalid Rx timestamp\n");
  455. return;
  456. }
  457. ns = timecounter_cyc2time(&ptp->tc, timestamp);
  458. spin_unlock_bh(&ptp->lock);
  459. skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
  460. DP_VERBOSE(edev, QED_MSG_DEBUG,
  461. "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
  462. timestamp, ns);
  463. }