ixgbe_common.h 8.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* Copyright(c) 1999 - 2018 Intel Corporation. */
  3. #ifndef _IXGBE_COMMON_H_
  4. #define _IXGBE_COMMON_H_
  5. #include "ixgbe_type.h"
  6. #include "ixgbe.h"
  7. u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
  8. s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
  9. s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
  10. s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
  11. s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
  12. s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
  13. s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
  14. u32 pba_num_size);
  15. s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
  16. enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status);
  17. enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status);
  18. s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
  19. void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
  20. s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
  21. s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
  22. s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
  23. s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw);
  24. s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
  25. s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
  26. s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
  27. u16 words, u16 *data);
  28. s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
  29. s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
  30. u16 words, u16 *data);
  31. s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
  32. s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
  33. u16 words, u16 *data);
  34. s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
  35. u16 *data);
  36. s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
  37. u16 words, u16 *data);
  38. s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
  39. s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
  40. u16 *checksum_val);
  41. s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
  42. s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
  43. u32 enable_addr);
  44. s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
  45. s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
  46. s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
  47. struct net_device *netdev);
  48. s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
  49. s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
  50. s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw);
  51. s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw);
  52. s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
  53. s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
  54. s32 ixgbe_setup_fc_generic(struct ixgbe_hw *);
  55. bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
  56. void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
  57. s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);
  58. void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);
  59. s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
  60. s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  61. s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
  62. s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  63. s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
  64. s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
  65. u32 vind, bool vlan_on, bool vlvf_bypass);
  66. s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
  67. s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
  68. ixgbe_link_speed *speed,
  69. bool *link_up, bool link_up_wait_to_complete);
  70. s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
  71. u16 *wwpn_prefix);
  72. s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);
  73. s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
  74. s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
  75. s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
  76. void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
  77. void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
  78. s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
  79. s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
  80. u8 build, u8 ver, u16 len, const char *str);
  81. u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);
  82. s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *, u32 length,
  83. u32 timeout, bool return_data);
  84. s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 len, u32 timeout);
  85. s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
  86. u32 (*data)[FW_PHY_ACT_DATA_COUNT]);
  87. void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
  88. bool ixgbe_mng_present(struct ixgbe_hw *hw);
  89. bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
  90. void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
  91. u32 headroom, int strategy);
  92. extern const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT];
  93. #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
  94. #define IXGBE_EMC_INTERNAL_DATA 0x00
  95. #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
  96. #define IXGBE_EMC_DIODE1_DATA 0x01
  97. #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
  98. #define IXGBE_EMC_DIODE2_DATA 0x23
  99. #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
  100. #define IXGBE_EMC_DIODE3_DATA 0x2A
  101. #define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30
  102. s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);
  103. s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);
  104. void ixgbe_get_etk_id(struct ixgbe_hw *hw,
  105. struct ixgbe_nvm_version *nvm_ver);
  106. void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
  107. struct ixgbe_nvm_version *nvm_ver);
  108. void ixgbe_get_orom_version(struct ixgbe_hw *hw,
  109. struct ixgbe_nvm_version *nvm_ver);
  110. void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);
  111. void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);
  112. s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
  113. ixgbe_link_speed speed,
  114. bool autoneg_wait_to_complete);
  115. void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
  116. ixgbe_link_speed speed);
  117. #define IXGBE_FAILED_READ_RETRIES 5
  118. #define IXGBE_FAILED_READ_REG 0xffffffffU
  119. #define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU
  120. #define IXGBE_FAILED_READ_CFG_WORD 0xffffU
  121. u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);
  122. void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);
  123. static inline bool ixgbe_removed(void __iomem *addr)
  124. {
  125. return unlikely(!addr);
  126. }
  127. static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value)
  128. {
  129. u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
  130. if (ixgbe_removed(reg_addr))
  131. return;
  132. writel(value, reg_addr + reg);
  133. }
  134. #define IXGBE_WRITE_REG(a, reg, value) ixgbe_write_reg((a), (reg), (value))
  135. #ifndef writeq
  136. #define writeq writeq
  137. static inline void writeq(u64 val, void __iomem *addr)
  138. {
  139. writel((u32)val, addr);
  140. writel((u32)(val >> 32), addr + 4);
  141. }
  142. #endif
  143. static inline void ixgbe_write_reg64(struct ixgbe_hw *hw, u32 reg, u64 value)
  144. {
  145. u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
  146. if (ixgbe_removed(reg_addr))
  147. return;
  148. writeq(value, reg_addr + reg);
  149. }
  150. #define IXGBE_WRITE_REG64(a, reg, value) ixgbe_write_reg64((a), (reg), (value))
  151. u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg);
  152. #define IXGBE_READ_REG(a, reg) ixgbe_read_reg((a), (reg))
  153. #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \
  154. ixgbe_write_reg((a), (reg) + ((offset) << 2), (value))
  155. #define IXGBE_READ_REG_ARRAY(a, reg, offset) \
  156. ixgbe_read_reg((a), (reg) + ((offset) << 2))
  157. #define IXGBE_WRITE_FLUSH(a) ixgbe_read_reg((a), IXGBE_STATUS)
  158. #define ixgbe_hw_to_netdev(hw) (((struct ixgbe_adapter *)(hw)->back)->netdev)
  159. #define hw_dbg(hw, format, arg...) \
  160. netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg)
  161. #define hw_err(hw, format, arg...) \
  162. netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg)
  163. #define e_dev_info(format, arg...) \
  164. dev_info(&adapter->pdev->dev, format, ## arg)
  165. #define e_dev_warn(format, arg...) \
  166. dev_warn(&adapter->pdev->dev, format, ## arg)
  167. #define e_dev_err(format, arg...) \
  168. dev_err(&adapter->pdev->dev, format, ## arg)
  169. #define e_dev_notice(format, arg...) \
  170. dev_notice(&adapter->pdev->dev, format, ## arg)
  171. #define e_info(msglvl, format, arg...) \
  172. netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
  173. #define e_err(msglvl, format, arg...) \
  174. netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
  175. #define e_warn(msglvl, format, arg...) \
  176. netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
  177. #define e_crit(msglvl, format, arg...) \
  178. netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
  179. #endif /* IXGBE_COMMON */