octeon_mailbox.c 10 KB

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  1. /**********************************************************************
  2. * Author: Cavium, Inc.
  3. *
  4. * Contact: support@cavium.com
  5. * Please include "LiquidIO" in the subject.
  6. *
  7. * Copyright (c) 2003-2016 Cavium, Inc.
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more details.
  17. ***********************************************************************/
  18. #include <linux/pci.h>
  19. #include <linux/netdevice.h>
  20. #include "liquidio_common.h"
  21. #include "octeon_droq.h"
  22. #include "octeon_iq.h"
  23. #include "response_manager.h"
  24. #include "octeon_device.h"
  25. #include "octeon_main.h"
  26. #include "octeon_mailbox.h"
  27. #include "cn23xx_pf_device.h"
  28. /**
  29. * octeon_mbox_read:
  30. * @oct: Pointer mailbox
  31. *
  32. * Reads the 8-bytes of data from the mbox register
  33. * Writes back the acknowldgement inidcating completion of read
  34. */
  35. int octeon_mbox_read(struct octeon_mbox *mbox)
  36. {
  37. union octeon_mbox_message msg;
  38. int ret = 0;
  39. spin_lock(&mbox->lock);
  40. msg.u64 = readq(mbox->mbox_read_reg);
  41. if ((msg.u64 == OCTEON_PFVFACK) || (msg.u64 == OCTEON_PFVFSIG)) {
  42. spin_unlock(&mbox->lock);
  43. return 0;
  44. }
  45. if (mbox->state & OCTEON_MBOX_STATE_REQUEST_RECEIVING) {
  46. mbox->mbox_req.data[mbox->mbox_req.recv_len - 1] = msg.u64;
  47. mbox->mbox_req.recv_len++;
  48. } else {
  49. if (mbox->state & OCTEON_MBOX_STATE_RESPONSE_RECEIVING) {
  50. mbox->mbox_resp.data[mbox->mbox_resp.recv_len - 1] =
  51. msg.u64;
  52. mbox->mbox_resp.recv_len++;
  53. } else {
  54. if ((mbox->state & OCTEON_MBOX_STATE_IDLE) &&
  55. (msg.s.type == OCTEON_MBOX_REQUEST)) {
  56. mbox->state &= ~OCTEON_MBOX_STATE_IDLE;
  57. mbox->state |=
  58. OCTEON_MBOX_STATE_REQUEST_RECEIVING;
  59. mbox->mbox_req.msg.u64 = msg.u64;
  60. mbox->mbox_req.q_no = mbox->q_no;
  61. mbox->mbox_req.recv_len = 1;
  62. } else {
  63. if ((mbox->state &
  64. OCTEON_MBOX_STATE_RESPONSE_PENDING) &&
  65. (msg.s.type == OCTEON_MBOX_RESPONSE)) {
  66. mbox->state &=
  67. ~OCTEON_MBOX_STATE_RESPONSE_PENDING;
  68. mbox->state |=
  69. OCTEON_MBOX_STATE_RESPONSE_RECEIVING
  70. ;
  71. mbox->mbox_resp.msg.u64 = msg.u64;
  72. mbox->mbox_resp.q_no = mbox->q_no;
  73. mbox->mbox_resp.recv_len = 1;
  74. } else {
  75. writeq(OCTEON_PFVFERR,
  76. mbox->mbox_read_reg);
  77. mbox->state |= OCTEON_MBOX_STATE_ERROR;
  78. spin_unlock(&mbox->lock);
  79. return 1;
  80. }
  81. }
  82. }
  83. }
  84. if (mbox->state & OCTEON_MBOX_STATE_REQUEST_RECEIVING) {
  85. if (mbox->mbox_req.recv_len < mbox->mbox_req.msg.s.len) {
  86. ret = 0;
  87. } else {
  88. mbox->state &= ~OCTEON_MBOX_STATE_REQUEST_RECEIVING;
  89. mbox->state |= OCTEON_MBOX_STATE_REQUEST_RECEIVED;
  90. ret = 1;
  91. }
  92. } else {
  93. if (mbox->state & OCTEON_MBOX_STATE_RESPONSE_RECEIVING) {
  94. if (mbox->mbox_resp.recv_len <
  95. mbox->mbox_resp.msg.s.len) {
  96. ret = 0;
  97. } else {
  98. mbox->state &=
  99. ~OCTEON_MBOX_STATE_RESPONSE_RECEIVING;
  100. mbox->state |=
  101. OCTEON_MBOX_STATE_RESPONSE_RECEIVED;
  102. ret = 1;
  103. }
  104. } else {
  105. WARN_ON(1);
  106. }
  107. }
  108. writeq(OCTEON_PFVFACK, mbox->mbox_read_reg);
  109. spin_unlock(&mbox->lock);
  110. return ret;
  111. }
  112. /**
  113. * octeon_mbox_write:
  114. * @oct: Pointer Octeon Device
  115. * @mbox_cmd: Cmd to send to mailbox.
  116. *
  117. * Populates the queue specific mbox structure
  118. * with cmd information.
  119. * Write the cmd to mbox register
  120. */
  121. int octeon_mbox_write(struct octeon_device *oct,
  122. struct octeon_mbox_cmd *mbox_cmd)
  123. {
  124. struct octeon_mbox *mbox = oct->mbox[mbox_cmd->q_no];
  125. u32 count, i, ret = OCTEON_MBOX_STATUS_SUCCESS;
  126. long timeout = LIO_MBOX_WRITE_WAIT_TIME;
  127. unsigned long flags;
  128. spin_lock_irqsave(&mbox->lock, flags);
  129. if ((mbox_cmd->msg.s.type == OCTEON_MBOX_RESPONSE) &&
  130. !(mbox->state & OCTEON_MBOX_STATE_REQUEST_RECEIVED)) {
  131. spin_unlock_irqrestore(&mbox->lock, flags);
  132. return OCTEON_MBOX_STATUS_FAILED;
  133. }
  134. if ((mbox_cmd->msg.s.type == OCTEON_MBOX_REQUEST) &&
  135. !(mbox->state & OCTEON_MBOX_STATE_IDLE)) {
  136. spin_unlock_irqrestore(&mbox->lock, flags);
  137. return OCTEON_MBOX_STATUS_BUSY;
  138. }
  139. if (mbox_cmd->msg.s.type == OCTEON_MBOX_REQUEST) {
  140. memcpy(&mbox->mbox_resp, mbox_cmd,
  141. sizeof(struct octeon_mbox_cmd));
  142. mbox->state = OCTEON_MBOX_STATE_RESPONSE_PENDING;
  143. }
  144. spin_unlock_irqrestore(&mbox->lock, flags);
  145. count = 0;
  146. while (readq(mbox->mbox_write_reg) != OCTEON_PFVFSIG) {
  147. schedule_timeout_uninterruptible(timeout);
  148. if (count++ == LIO_MBOX_WRITE_WAIT_CNT) {
  149. ret = OCTEON_MBOX_STATUS_FAILED;
  150. break;
  151. }
  152. }
  153. if (ret == OCTEON_MBOX_STATUS_SUCCESS) {
  154. writeq(mbox_cmd->msg.u64, mbox->mbox_write_reg);
  155. for (i = 0; i < (u32)(mbox_cmd->msg.s.len - 1); i++) {
  156. count = 0;
  157. while (readq(mbox->mbox_write_reg) !=
  158. OCTEON_PFVFACK) {
  159. schedule_timeout_uninterruptible(timeout);
  160. if (count++ == LIO_MBOX_WRITE_WAIT_CNT) {
  161. ret = OCTEON_MBOX_STATUS_FAILED;
  162. break;
  163. }
  164. }
  165. if (ret == OCTEON_MBOX_STATUS_SUCCESS)
  166. writeq(mbox_cmd->data[i], mbox->mbox_write_reg);
  167. else
  168. break;
  169. }
  170. }
  171. spin_lock_irqsave(&mbox->lock, flags);
  172. if (mbox_cmd->msg.s.type == OCTEON_MBOX_RESPONSE) {
  173. mbox->state = OCTEON_MBOX_STATE_IDLE;
  174. writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
  175. } else {
  176. if ((!mbox_cmd->msg.s.resp_needed) ||
  177. (ret == OCTEON_MBOX_STATUS_FAILED)) {
  178. mbox->state &= ~OCTEON_MBOX_STATE_RESPONSE_PENDING;
  179. if (!(mbox->state &
  180. (OCTEON_MBOX_STATE_REQUEST_RECEIVING |
  181. OCTEON_MBOX_STATE_REQUEST_RECEIVED)))
  182. mbox->state = OCTEON_MBOX_STATE_IDLE;
  183. }
  184. }
  185. spin_unlock_irqrestore(&mbox->lock, flags);
  186. return ret;
  187. }
  188. static void get_vf_stats(struct octeon_device *oct,
  189. struct oct_vf_stats *stats)
  190. {
  191. int i;
  192. for (i = 0; i < oct->num_iqs; i++) {
  193. if (!oct->instr_queue[i])
  194. continue;
  195. stats->tx_packets += oct->instr_queue[i]->stats.tx_done;
  196. stats->tx_bytes += oct->instr_queue[i]->stats.tx_tot_bytes;
  197. }
  198. for (i = 0; i < oct->num_oqs; i++) {
  199. if (!oct->droq[i])
  200. continue;
  201. stats->rx_packets += oct->droq[i]->stats.rx_pkts_received;
  202. stats->rx_bytes += oct->droq[i]->stats.rx_bytes_received;
  203. }
  204. }
  205. /**
  206. * octeon_mbox_process_cmd:
  207. * @mbox: Pointer mailbox
  208. * @mbox_cmd: Pointer to command received
  209. *
  210. * Process the cmd received in mbox
  211. */
  212. static int octeon_mbox_process_cmd(struct octeon_mbox *mbox,
  213. struct octeon_mbox_cmd *mbox_cmd)
  214. {
  215. struct octeon_device *oct = mbox->oct_dev;
  216. switch (mbox_cmd->msg.s.cmd) {
  217. case OCTEON_VF_ACTIVE:
  218. dev_dbg(&oct->pci_dev->dev, "got vfactive sending data back\n");
  219. mbox_cmd->msg.s.type = OCTEON_MBOX_RESPONSE;
  220. mbox_cmd->msg.s.resp_needed = 1;
  221. mbox_cmd->msg.s.len = 2;
  222. mbox_cmd->data[0] = 0; /* VF version is in mbox_cmd->data[0] */
  223. ((struct lio_version *)&mbox_cmd->data[0])->major =
  224. LIQUIDIO_BASE_MAJOR_VERSION;
  225. ((struct lio_version *)&mbox_cmd->data[0])->minor =
  226. LIQUIDIO_BASE_MINOR_VERSION;
  227. ((struct lio_version *)&mbox_cmd->data[0])->micro =
  228. LIQUIDIO_BASE_MICRO_VERSION;
  229. memcpy(mbox_cmd->msg.s.params, (uint8_t *)&oct->pfvf_hsword, 6);
  230. /* Sending core cofig info to the corresponding active VF.*/
  231. octeon_mbox_write(oct, mbox_cmd);
  232. break;
  233. case OCTEON_VF_FLR_REQUEST:
  234. dev_info(&oct->pci_dev->dev,
  235. "got a request for FLR from VF that owns DPI ring %u\n",
  236. mbox->q_no);
  237. pcie_capability_set_word(
  238. oct->sriov_info.dpiring_to_vfpcidev_lut[mbox->q_no],
  239. PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
  240. break;
  241. case OCTEON_PF_CHANGED_VF_MACADDR:
  242. if (OCTEON_CN23XX_VF(oct))
  243. octeon_pf_changed_vf_macaddr(oct,
  244. mbox_cmd->msg.s.params);
  245. break;
  246. case OCTEON_GET_VF_STATS:
  247. dev_dbg(&oct->pci_dev->dev, "Got VF stats request. Sending data back\n");
  248. mbox_cmd->msg.s.type = OCTEON_MBOX_RESPONSE;
  249. mbox_cmd->msg.s.resp_needed = 1;
  250. mbox_cmd->msg.s.len = 1 +
  251. sizeof(struct oct_vf_stats) / sizeof(u64);
  252. get_vf_stats(oct, (struct oct_vf_stats *)mbox_cmd->data);
  253. octeon_mbox_write(oct, mbox_cmd);
  254. break;
  255. default:
  256. break;
  257. }
  258. return 0;
  259. }
  260. /**
  261. *octeon_mbox_process_message:
  262. *
  263. * Process the received mbox message.
  264. */
  265. int octeon_mbox_process_message(struct octeon_mbox *mbox)
  266. {
  267. struct octeon_mbox_cmd mbox_cmd;
  268. unsigned long flags;
  269. spin_lock_irqsave(&mbox->lock, flags);
  270. if (mbox->state & OCTEON_MBOX_STATE_ERROR) {
  271. if (mbox->state & (OCTEON_MBOX_STATE_RESPONSE_PENDING |
  272. OCTEON_MBOX_STATE_RESPONSE_RECEIVING)) {
  273. memcpy(&mbox_cmd, &mbox->mbox_resp,
  274. sizeof(struct octeon_mbox_cmd));
  275. mbox->state = OCTEON_MBOX_STATE_IDLE;
  276. writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
  277. spin_unlock_irqrestore(&mbox->lock, flags);
  278. mbox_cmd.recv_status = 1;
  279. if (mbox_cmd.fn)
  280. mbox_cmd.fn(mbox->oct_dev, &mbox_cmd,
  281. mbox_cmd.fn_arg);
  282. return 0;
  283. }
  284. mbox->state = OCTEON_MBOX_STATE_IDLE;
  285. writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
  286. spin_unlock_irqrestore(&mbox->lock, flags);
  287. return 0;
  288. }
  289. if (mbox->state & OCTEON_MBOX_STATE_RESPONSE_RECEIVED) {
  290. memcpy(&mbox_cmd, &mbox->mbox_resp,
  291. sizeof(struct octeon_mbox_cmd));
  292. mbox->state = OCTEON_MBOX_STATE_IDLE;
  293. writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
  294. spin_unlock_irqrestore(&mbox->lock, flags);
  295. mbox_cmd.recv_status = 0;
  296. if (mbox_cmd.fn)
  297. mbox_cmd.fn(mbox->oct_dev, &mbox_cmd, mbox_cmd.fn_arg);
  298. return 0;
  299. }
  300. if (mbox->state & OCTEON_MBOX_STATE_REQUEST_RECEIVED) {
  301. memcpy(&mbox_cmd, &mbox->mbox_req,
  302. sizeof(struct octeon_mbox_cmd));
  303. if (!mbox_cmd.msg.s.resp_needed) {
  304. mbox->state &= ~OCTEON_MBOX_STATE_REQUEST_RECEIVED;
  305. if (!(mbox->state &
  306. OCTEON_MBOX_STATE_RESPONSE_PENDING))
  307. mbox->state = OCTEON_MBOX_STATE_IDLE;
  308. writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
  309. }
  310. spin_unlock_irqrestore(&mbox->lock, flags);
  311. octeon_mbox_process_cmd(mbox, &mbox_cmd);
  312. return 0;
  313. }
  314. spin_unlock_irqrestore(&mbox->lock, flags);
  315. WARN_ON(1);
  316. return 0;
  317. }
  318. int octeon_mbox_cancel(struct octeon_device *oct, int q_no)
  319. {
  320. struct octeon_mbox *mbox = oct->mbox[q_no];
  321. struct octeon_mbox_cmd *mbox_cmd;
  322. unsigned long flags = 0;
  323. spin_lock_irqsave(&mbox->lock, flags);
  324. mbox_cmd = &mbox->mbox_resp;
  325. if (!(mbox->state & OCTEON_MBOX_STATE_RESPONSE_PENDING)) {
  326. spin_unlock_irqrestore(&mbox->lock, flags);
  327. return 1;
  328. }
  329. mbox->state = OCTEON_MBOX_STATE_IDLE;
  330. memset(mbox_cmd, 0, sizeof(*mbox_cmd));
  331. writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
  332. spin_unlock_irqrestore(&mbox->lock, flags);
  333. return 0;
  334. }