xgbe-main.c 16 KB

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  1. /*
  2. * AMD 10Gb Ethernet driver
  3. *
  4. * This file is available to you under your choice of the following two
  5. * licenses:
  6. *
  7. * License 1: GPLv2
  8. *
  9. * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10. *
  11. * This file is free software; you may copy, redistribute and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation, either version 2 of the License, or (at
  14. * your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  23. *
  24. * This file incorporates work covered by the following copyright and
  25. * permission notice:
  26. * The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27. * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28. * Inc. unless otherwise expressly agreed to in writing between Synopsys
  29. * and you.
  30. *
  31. * The Software IS NOT an item of Licensed Software or Licensed Product
  32. * under any End User Software License Agreement or Agreement for Licensed
  33. * Product with Synopsys or any supplement thereto. Permission is hereby
  34. * granted, free of charge, to any person obtaining a copy of this software
  35. * annotated with this license and the Software, to deal in the Software
  36. * without restriction, including without limitation the rights to use,
  37. * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38. * of the Software, and to permit persons to whom the Software is furnished
  39. * to do so, subject to the following conditions:
  40. *
  41. * The above copyright notice and this permission notice shall be included
  42. * in all copies or substantial portions of the Software.
  43. *
  44. * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45. * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47. * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54. * THE POSSIBILITY OF SUCH DAMAGE.
  55. *
  56. *
  57. * License 2: Modified BSD
  58. *
  59. * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60. * All rights reserved.
  61. *
  62. * Redistribution and use in source and binary forms, with or without
  63. * modification, are permitted provided that the following conditions are met:
  64. * * Redistributions of source code must retain the above copyright
  65. * notice, this list of conditions and the following disclaimer.
  66. * * Redistributions in binary form must reproduce the above copyright
  67. * notice, this list of conditions and the following disclaimer in the
  68. * documentation and/or other materials provided with the distribution.
  69. * * Neither the name of Advanced Micro Devices, Inc. nor the
  70. * names of its contributors may be used to endorse or promote products
  71. * derived from this software without specific prior written permission.
  72. *
  73. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76. * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83. *
  84. * This file incorporates work covered by the following copyright and
  85. * permission notice:
  86. * The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87. * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88. * Inc. unless otherwise expressly agreed to in writing between Synopsys
  89. * and you.
  90. *
  91. * The Software IS NOT an item of Licensed Software or Licensed Product
  92. * under any End User Software License Agreement or Agreement for Licensed
  93. * Product with Synopsys or any supplement thereto. Permission is hereby
  94. * granted, free of charge, to any person obtaining a copy of this software
  95. * annotated with this license and the Software, to deal in the Software
  96. * without restriction, including without limitation the rights to use,
  97. * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98. * of the Software, and to permit persons to whom the Software is furnished
  99. * to do so, subject to the following conditions:
  100. *
  101. * The above copyright notice and this permission notice shall be included
  102. * in all copies or substantial portions of the Software.
  103. *
  104. * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  105. * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  106. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  107. * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  108. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  109. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  110. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  111. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  112. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  113. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  114. * THE POSSIBILITY OF SUCH DAMAGE.
  115. */
  116. #include <linux/module.h>
  117. #include <linux/device.h>
  118. #include <linux/spinlock.h>
  119. #include <linux/netdevice.h>
  120. #include <linux/etherdevice.h>
  121. #include <linux/io.h>
  122. #include <linux/notifier.h>
  123. #include "xgbe.h"
  124. #include "xgbe-common.h"
  125. MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
  126. MODULE_LICENSE("Dual BSD/GPL");
  127. MODULE_VERSION(XGBE_DRV_VERSION);
  128. MODULE_DESCRIPTION(XGBE_DRV_DESC);
  129. static int debug = -1;
  130. module_param(debug, int, 0644);
  131. MODULE_PARM_DESC(debug, " Network interface message level setting");
  132. static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
  133. NETIF_MSG_IFUP);
  134. static void xgbe_default_config(struct xgbe_prv_data *pdata)
  135. {
  136. DBGPR("-->xgbe_default_config\n");
  137. pdata->blen = DMA_SBMR_BLEN_64;
  138. pdata->pbl = DMA_PBL_128;
  139. pdata->aal = 1;
  140. pdata->rd_osr_limit = 8;
  141. pdata->wr_osr_limit = 8;
  142. pdata->tx_sf_mode = MTL_TSF_ENABLE;
  143. pdata->tx_threshold = MTL_TX_THRESHOLD_64;
  144. pdata->tx_osp_mode = DMA_OSP_ENABLE;
  145. pdata->rx_sf_mode = MTL_RSF_DISABLE;
  146. pdata->rx_threshold = MTL_RX_THRESHOLD_64;
  147. pdata->pause_autoneg = 1;
  148. pdata->tx_pause = 1;
  149. pdata->rx_pause = 1;
  150. pdata->phy_speed = SPEED_UNKNOWN;
  151. pdata->power_down = 0;
  152. DBGPR("<--xgbe_default_config\n");
  153. }
  154. static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
  155. {
  156. xgbe_init_function_ptrs_dev(&pdata->hw_if);
  157. xgbe_init_function_ptrs_phy(&pdata->phy_if);
  158. xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
  159. xgbe_init_function_ptrs_desc(&pdata->desc_if);
  160. pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
  161. }
  162. struct xgbe_prv_data *xgbe_alloc_pdata(struct device *dev)
  163. {
  164. struct xgbe_prv_data *pdata;
  165. struct net_device *netdev;
  166. netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data),
  167. XGBE_MAX_DMA_CHANNELS);
  168. if (!netdev) {
  169. dev_err(dev, "alloc_etherdev_mq failed\n");
  170. return ERR_PTR(-ENOMEM);
  171. }
  172. SET_NETDEV_DEV(netdev, dev);
  173. pdata = netdev_priv(netdev);
  174. pdata->netdev = netdev;
  175. pdata->dev = dev;
  176. spin_lock_init(&pdata->lock);
  177. spin_lock_init(&pdata->xpcs_lock);
  178. mutex_init(&pdata->rss_mutex);
  179. spin_lock_init(&pdata->tstamp_lock);
  180. mutex_init(&pdata->i2c_mutex);
  181. init_completion(&pdata->i2c_complete);
  182. init_completion(&pdata->mdio_complete);
  183. INIT_LIST_HEAD(&pdata->vxlan_ports);
  184. pdata->msg_enable = netif_msg_init(debug, default_msg_level);
  185. set_bit(XGBE_DOWN, &pdata->dev_state);
  186. set_bit(XGBE_STOPPED, &pdata->dev_state);
  187. return pdata;
  188. }
  189. void xgbe_free_pdata(struct xgbe_prv_data *pdata)
  190. {
  191. struct net_device *netdev = pdata->netdev;
  192. free_netdev(netdev);
  193. }
  194. void xgbe_set_counts(struct xgbe_prv_data *pdata)
  195. {
  196. /* Set all the function pointers */
  197. xgbe_init_all_fptrs(pdata);
  198. /* Populate the hardware features */
  199. xgbe_get_all_hw_features(pdata);
  200. /* Set default max values if not provided */
  201. if (!pdata->tx_max_channel_count)
  202. pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
  203. if (!pdata->rx_max_channel_count)
  204. pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
  205. if (!pdata->tx_max_q_count)
  206. pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
  207. if (!pdata->rx_max_q_count)
  208. pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
  209. /* Calculate the number of Tx and Rx rings to be created
  210. * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
  211. * the number of Tx queues to the number of Tx channels
  212. * enabled
  213. * -Rx (DMA) Channels do not map 1-to-1 so use the actual
  214. * number of Rx queues or maximum allowed
  215. */
  216. pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
  217. pdata->hw_feat.tx_ch_cnt);
  218. pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
  219. pdata->tx_max_channel_count);
  220. pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
  221. pdata->tx_max_q_count);
  222. pdata->tx_q_count = pdata->tx_ring_count;
  223. pdata->rx_ring_count = min_t(unsigned int, num_online_cpus(),
  224. pdata->hw_feat.rx_ch_cnt);
  225. pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
  226. pdata->rx_max_channel_count);
  227. pdata->rx_q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt,
  228. pdata->rx_max_q_count);
  229. if (netif_msg_probe(pdata)) {
  230. dev_dbg(pdata->dev, "TX/RX DMA channel count = %u/%u\n",
  231. pdata->tx_ring_count, pdata->rx_ring_count);
  232. dev_dbg(pdata->dev, "TX/RX hardware queue count = %u/%u\n",
  233. pdata->tx_q_count, pdata->rx_q_count);
  234. }
  235. }
  236. int xgbe_config_netdev(struct xgbe_prv_data *pdata)
  237. {
  238. struct net_device *netdev = pdata->netdev;
  239. struct device *dev = pdata->dev;
  240. int ret;
  241. netdev->irq = pdata->dev_irq;
  242. netdev->base_addr = (unsigned long)pdata->xgmac_regs;
  243. memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
  244. /* Initialize ECC timestamps */
  245. pdata->tx_sec_period = jiffies;
  246. pdata->tx_ded_period = jiffies;
  247. pdata->rx_sec_period = jiffies;
  248. pdata->rx_ded_period = jiffies;
  249. pdata->desc_sec_period = jiffies;
  250. pdata->desc_ded_period = jiffies;
  251. /* Issue software reset to device */
  252. ret = pdata->hw_if.exit(pdata);
  253. if (ret) {
  254. dev_err(dev, "software reset failed\n");
  255. return ret;
  256. }
  257. /* Set default configuration data */
  258. xgbe_default_config(pdata);
  259. /* Set the DMA mask */
  260. ret = dma_set_mask_and_coherent(dev,
  261. DMA_BIT_MASK(pdata->hw_feat.dma_width));
  262. if (ret) {
  263. dev_err(dev, "dma_set_mask_and_coherent failed\n");
  264. return ret;
  265. }
  266. /* Set default max values if not provided */
  267. if (!pdata->tx_max_fifo_size)
  268. pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
  269. if (!pdata->rx_max_fifo_size)
  270. pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
  271. /* Set and validate the number of descriptors for a ring */
  272. BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT);
  273. pdata->tx_desc_count = XGBE_TX_DESC_CNT;
  274. BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
  275. pdata->rx_desc_count = XGBE_RX_DESC_CNT;
  276. /* Adjust the number of queues based on interrupts assigned */
  277. if (pdata->channel_irq_count) {
  278. pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
  279. pdata->channel_irq_count);
  280. pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
  281. pdata->channel_irq_count);
  282. if (netif_msg_probe(pdata))
  283. dev_dbg(pdata->dev,
  284. "adjusted TX/RX DMA channel count = %u/%u\n",
  285. pdata->tx_ring_count, pdata->rx_ring_count);
  286. }
  287. /* Initialize RSS hash key */
  288. netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
  289. XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
  290. XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
  291. XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
  292. /* Call MDIO/PHY initialization routine */
  293. pdata->debugfs_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
  294. ret = pdata->phy_if.phy_init(pdata);
  295. if (ret)
  296. return ret;
  297. /* Set device operations */
  298. netdev->netdev_ops = xgbe_get_netdev_ops();
  299. netdev->ethtool_ops = xgbe_get_ethtool_ops();
  300. #ifdef CONFIG_AMD_XGBE_DCB
  301. netdev->dcbnl_ops = xgbe_get_dcbnl_ops();
  302. #endif
  303. /* Set device features */
  304. netdev->hw_features = NETIF_F_SG |
  305. NETIF_F_IP_CSUM |
  306. NETIF_F_IPV6_CSUM |
  307. NETIF_F_RXCSUM |
  308. NETIF_F_TSO |
  309. NETIF_F_TSO6 |
  310. NETIF_F_GRO |
  311. NETIF_F_HW_VLAN_CTAG_RX |
  312. NETIF_F_HW_VLAN_CTAG_TX |
  313. NETIF_F_HW_VLAN_CTAG_FILTER;
  314. if (pdata->hw_feat.rss)
  315. netdev->hw_features |= NETIF_F_RXHASH;
  316. if (pdata->hw_feat.vxn) {
  317. netdev->hw_enc_features = NETIF_F_SG |
  318. NETIF_F_IP_CSUM |
  319. NETIF_F_IPV6_CSUM |
  320. NETIF_F_RXCSUM |
  321. NETIF_F_TSO |
  322. NETIF_F_TSO6 |
  323. NETIF_F_GRO |
  324. NETIF_F_GSO_UDP_TUNNEL |
  325. NETIF_F_GSO_UDP_TUNNEL_CSUM |
  326. NETIF_F_RX_UDP_TUNNEL_PORT;
  327. netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
  328. NETIF_F_GSO_UDP_TUNNEL_CSUM |
  329. NETIF_F_RX_UDP_TUNNEL_PORT;
  330. pdata->vxlan_offloads_set = 1;
  331. pdata->vxlan_features = NETIF_F_GSO_UDP_TUNNEL |
  332. NETIF_F_GSO_UDP_TUNNEL_CSUM |
  333. NETIF_F_RX_UDP_TUNNEL_PORT;
  334. }
  335. netdev->vlan_features |= NETIF_F_SG |
  336. NETIF_F_IP_CSUM |
  337. NETIF_F_IPV6_CSUM |
  338. NETIF_F_TSO |
  339. NETIF_F_TSO6;
  340. netdev->features |= netdev->hw_features;
  341. pdata->netdev_features = netdev->features;
  342. netdev->priv_flags |= IFF_UNICAST_FLT;
  343. netdev->min_mtu = 0;
  344. netdev->max_mtu = XGMAC_JUMBO_PACKET_MTU;
  345. /* Use default watchdog timeout */
  346. netdev->watchdog_timeo = 0;
  347. xgbe_init_rx_coalesce(pdata);
  348. xgbe_init_tx_coalesce(pdata);
  349. netif_carrier_off(netdev);
  350. ret = register_netdev(netdev);
  351. if (ret) {
  352. dev_err(dev, "net device registration failed\n");
  353. return ret;
  354. }
  355. if (IS_REACHABLE(CONFIG_PTP_1588_CLOCK))
  356. xgbe_ptp_register(pdata);
  357. xgbe_debugfs_init(pdata);
  358. netif_dbg(pdata, drv, pdata->netdev, "%u Tx software queues\n",
  359. pdata->tx_ring_count);
  360. netif_dbg(pdata, drv, pdata->netdev, "%u Rx software queues\n",
  361. pdata->rx_ring_count);
  362. return 0;
  363. }
  364. void xgbe_deconfig_netdev(struct xgbe_prv_data *pdata)
  365. {
  366. struct net_device *netdev = pdata->netdev;
  367. xgbe_debugfs_exit(pdata);
  368. if (IS_REACHABLE(CONFIG_PTP_1588_CLOCK))
  369. xgbe_ptp_unregister(pdata);
  370. unregister_netdev(netdev);
  371. pdata->phy_if.phy_exit(pdata);
  372. }
  373. static int xgbe_netdev_event(struct notifier_block *nb, unsigned long event,
  374. void *data)
  375. {
  376. struct net_device *netdev = netdev_notifier_info_to_dev(data);
  377. struct xgbe_prv_data *pdata = netdev_priv(netdev);
  378. if (netdev->netdev_ops != xgbe_get_netdev_ops())
  379. goto out;
  380. switch (event) {
  381. case NETDEV_CHANGENAME:
  382. xgbe_debugfs_rename(pdata);
  383. break;
  384. default:
  385. break;
  386. }
  387. out:
  388. return NOTIFY_DONE;
  389. }
  390. static struct notifier_block xgbe_netdev_notifier = {
  391. .notifier_call = xgbe_netdev_event,
  392. };
  393. static int __init xgbe_mod_init(void)
  394. {
  395. int ret;
  396. ret = register_netdevice_notifier(&xgbe_netdev_notifier);
  397. if (ret)
  398. return ret;
  399. ret = xgbe_platform_init();
  400. if (ret)
  401. goto err_platform_init;
  402. ret = xgbe_pci_init();
  403. if (ret)
  404. goto err_pci_init;
  405. return 0;
  406. err_pci_init:
  407. xgbe_platform_exit();
  408. err_platform_init:
  409. unregister_netdevice_notifier(&xgbe_netdev_notifier);
  410. return ret;
  411. }
  412. static void __exit xgbe_mod_exit(void)
  413. {
  414. xgbe_pci_exit();
  415. xgbe_platform_exit();
  416. unregister_netdevice_notifier(&xgbe_netdev_notifier);
  417. }
  418. module_init(xgbe_mod_init);
  419. module_exit(xgbe_mod_exit);