tm6000-core.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // tm6000-core.c - driver for TM5600/TM6000/TM6010 USB video capture devices
  3. //
  4. // Copyright (c) 2006-2007 Mauro Carvalho Chehab <mchehab@kernel.org>
  5. //
  6. // Copyright (c) 2007 Michel Ludwig <michel.ludwig@gmail.com>
  7. // - DVB-T support
  8. #include <linux/module.h>
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/usb.h>
  12. #include <linux/i2c.h>
  13. #include "tm6000.h"
  14. #include "tm6000-regs.h"
  15. #include <media/v4l2-common.h>
  16. #include <media/tuner.h>
  17. #define USB_TIMEOUT (5 * HZ) /* ms */
  18. int tm6000_read_write_usb(struct tm6000_core *dev, u8 req_type, u8 req,
  19. u16 value, u16 index, u8 *buf, u16 len)
  20. {
  21. int ret, i;
  22. unsigned int pipe;
  23. u8 *data = NULL;
  24. int delay = 5000;
  25. if (len) {
  26. data = kzalloc(len, GFP_KERNEL);
  27. if (!data)
  28. return -ENOMEM;
  29. }
  30. mutex_lock(&dev->usb_lock);
  31. if (req_type & USB_DIR_IN)
  32. pipe = usb_rcvctrlpipe(dev->udev, 0);
  33. else {
  34. pipe = usb_sndctrlpipe(dev->udev, 0);
  35. memcpy(data, buf, len);
  36. }
  37. if (tm6000_debug & V4L2_DEBUG_I2C) {
  38. printk(KERN_DEBUG "(dev %p, pipe %08x): ", dev->udev, pipe);
  39. printk(KERN_CONT "%s: %02x %02x %02x %02x %02x %02x %02x %02x ",
  40. (req_type & USB_DIR_IN) ? " IN" : "OUT",
  41. req_type, req, value&0xff, value>>8, index&0xff,
  42. index>>8, len&0xff, len>>8);
  43. if (!(req_type & USB_DIR_IN)) {
  44. printk(KERN_CONT ">>> ");
  45. for (i = 0; i < len; i++)
  46. printk(KERN_CONT " %02x", buf[i]);
  47. printk(KERN_CONT "\n");
  48. }
  49. }
  50. ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index,
  51. data, len, USB_TIMEOUT);
  52. if (req_type & USB_DIR_IN)
  53. memcpy(buf, data, len);
  54. if (tm6000_debug & V4L2_DEBUG_I2C) {
  55. if (ret < 0) {
  56. if (req_type & USB_DIR_IN)
  57. printk(KERN_DEBUG "<<< (len=%d)\n", len);
  58. printk(KERN_CONT "%s: Error #%d\n", __func__, ret);
  59. } else if (req_type & USB_DIR_IN) {
  60. printk(KERN_CONT "<<< ");
  61. for (i = 0; i < len; i++)
  62. printk(KERN_CONT " %02x", buf[i]);
  63. printk(KERN_CONT "\n");
  64. }
  65. }
  66. kfree(data);
  67. if (dev->quirks & TM6000_QUIRK_NO_USB_DELAY)
  68. delay = 0;
  69. if (req == REQ_16_SET_GET_I2C_WR1_RDN && !(req_type & USB_DIR_IN)) {
  70. unsigned int tsleep;
  71. /* Calculate delay time, 14000us for 64 bytes */
  72. tsleep = (len * 200) + 200;
  73. if (tsleep < delay)
  74. tsleep = delay;
  75. usleep_range(tsleep, tsleep + 1000);
  76. }
  77. else if (delay)
  78. usleep_range(delay, delay + 1000);
  79. mutex_unlock(&dev->usb_lock);
  80. return ret;
  81. }
  82. int tm6000_set_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
  83. {
  84. return
  85. tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
  86. req, value, index, NULL, 0);
  87. }
  88. EXPORT_SYMBOL_GPL(tm6000_set_reg);
  89. int tm6000_get_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
  90. {
  91. int rc;
  92. u8 buf[1];
  93. rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
  94. value, index, buf, 1);
  95. if (rc < 0)
  96. return rc;
  97. return *buf;
  98. }
  99. EXPORT_SYMBOL_GPL(tm6000_get_reg);
  100. int tm6000_set_reg_mask(struct tm6000_core *dev, u8 req, u16 value,
  101. u16 index, u16 mask)
  102. {
  103. int rc;
  104. u8 buf[1];
  105. u8 new_index;
  106. rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
  107. value, 0, buf, 1);
  108. if (rc < 0)
  109. return rc;
  110. new_index = (buf[0] & ~mask) | (index & mask);
  111. if (new_index == buf[0])
  112. return 0;
  113. return tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
  114. req, value, new_index, NULL, 0);
  115. }
  116. EXPORT_SYMBOL_GPL(tm6000_set_reg_mask);
  117. int tm6000_get_reg16(struct tm6000_core *dev, u8 req, u16 value, u16 index)
  118. {
  119. int rc;
  120. u8 buf[2];
  121. rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
  122. value, index, buf, 2);
  123. if (rc < 0)
  124. return rc;
  125. return buf[1]|buf[0]<<8;
  126. }
  127. int tm6000_get_reg32(struct tm6000_core *dev, u8 req, u16 value, u16 index)
  128. {
  129. int rc;
  130. u8 buf[4];
  131. rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
  132. value, index, buf, 4);
  133. if (rc < 0)
  134. return rc;
  135. return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
  136. }
  137. int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep)
  138. {
  139. int rc;
  140. rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0);
  141. if (rc < 0)
  142. return rc;
  143. msleep(tsleep);
  144. rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1);
  145. msleep(tsleep);
  146. return rc;
  147. }
  148. void tm6000_set_fourcc_format(struct tm6000_core *dev)
  149. {
  150. if (dev->dev_type == TM6010) {
  151. int val;
  152. val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, 0) & 0xfc;
  153. if (dev->fourcc == V4L2_PIX_FMT_UYVY)
  154. tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val);
  155. else
  156. tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val | 1);
  157. } else {
  158. if (dev->fourcc == V4L2_PIX_FMT_UYVY)
  159. tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
  160. else
  161. tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
  162. }
  163. }
  164. static void tm6000_set_vbi(struct tm6000_core *dev)
  165. {
  166. /*
  167. * FIXME:
  168. * VBI lines and start/end are different between 60Hz and 50Hz
  169. * So, it is very likely that we need to change the config to
  170. * something that takes it into account, doing something different
  171. * if (dev->norm & V4L2_STD_525_60)
  172. */
  173. if (dev->dev_type == TM6010) {
  174. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
  175. tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
  176. tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
  177. tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
  178. tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
  179. tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
  180. tm6000_set_reg(dev,
  181. TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
  182. tm6000_set_reg(dev,
  183. TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
  184. tm6000_set_reg(dev,
  185. TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
  186. tm6000_set_reg(dev,
  187. TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
  188. tm6000_set_reg(dev,
  189. TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
  190. tm6000_set_reg(dev,
  191. TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
  192. tm6000_set_reg(dev,
  193. TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
  194. tm6000_set_reg(dev,
  195. TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
  196. tm6000_set_reg(dev,
  197. TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
  198. tm6000_set_reg(dev,
  199. TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
  200. tm6000_set_reg(dev,
  201. TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
  202. tm6000_set_reg(dev,
  203. TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
  204. tm6000_set_reg(dev,
  205. TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
  206. tm6000_set_reg(dev,
  207. TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
  208. tm6000_set_reg(dev,
  209. TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
  210. tm6000_set_reg(dev,
  211. TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
  212. tm6000_set_reg(dev,
  213. TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
  214. tm6000_set_reg(dev,
  215. TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
  216. tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
  217. tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
  218. tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
  219. tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
  220. tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
  221. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
  222. }
  223. }
  224. int tm6000_init_analog_mode(struct tm6000_core *dev)
  225. {
  226. struct v4l2_frequency f;
  227. if (dev->dev_type == TM6010) {
  228. u8 active = TM6010_REQ07_RCC_ACTIVE_IF_AUDIO_ENABLE;
  229. if (!dev->radio)
  230. active |= TM6010_REQ07_RCC_ACTIVE_IF_VIDEO_ENABLE;
  231. /* Enable video and audio */
  232. tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_IF,
  233. active, 0x60);
  234. /* Disable TS input */
  235. tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
  236. 0x00, 0x40);
  237. } else {
  238. /* Enables soft reset */
  239. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
  240. if (dev->scaler)
  241. /* Disable Hfilter and Enable TS Drop err */
  242. tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
  243. else /* Enable Hfilter and disable TS Drop err */
  244. tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
  245. tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
  246. tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x23);
  247. tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
  248. tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
  249. tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
  250. tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f);
  251. /* AP Software reset */
  252. tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
  253. tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
  254. tm6000_set_fourcc_format(dev);
  255. /* Disables soft reset */
  256. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
  257. }
  258. msleep(20);
  259. /* Tuner firmware can now be loaded */
  260. /*
  261. * FIXME: This is a hack! xc3028 "sleeps" when no channel is detected
  262. * for more than a few seconds. Not sure why, as this behavior does
  263. * not happen on other devices with xc3028. So, I suspect that it
  264. * is yet another bug at tm6000. After start sleeping, decoding
  265. * doesn't start automatically. Instead, it requires some
  266. * I2C commands to wake it up. As we want to have image at the
  267. * beginning, we needed to add this hack. The better would be to
  268. * discover some way to make tm6000 to wake up without this hack.
  269. */
  270. f.frequency = dev->freq;
  271. v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
  272. msleep(100);
  273. tm6000_set_standard(dev);
  274. tm6000_set_vbi(dev);
  275. tm6000_set_audio_bitrate(dev, 48000);
  276. /* switch dvb led off */
  277. if (dev->gpio.dvb_led) {
  278. tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
  279. dev->gpio.dvb_led, 0x01);
  280. }
  281. return 0;
  282. }
  283. int tm6000_init_digital_mode(struct tm6000_core *dev)
  284. {
  285. if (dev->dev_type == TM6010) {
  286. /* Disable video and audio */
  287. tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_IF,
  288. 0x00, 0x60);
  289. /* Enable TS input */
  290. tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
  291. 0x40, 0x40);
  292. /* all power down, but not the digital data port */
  293. tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
  294. tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
  295. tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
  296. } else {
  297. tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
  298. tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
  299. tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
  300. tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x08);
  301. tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c);
  302. tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff);
  303. tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0xd8);
  304. tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
  305. tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
  306. tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
  307. tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x37);
  308. tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
  309. tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
  310. tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
  311. tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c);
  312. tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff);
  313. tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0x08);
  314. msleep(50);
  315. tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
  316. msleep(50);
  317. tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
  318. msleep(50);
  319. tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
  320. msleep(100);
  321. }
  322. /* switch dvb led on */
  323. if (dev->gpio.dvb_led) {
  324. tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
  325. dev->gpio.dvb_led, 0x00);
  326. }
  327. return 0;
  328. }
  329. EXPORT_SYMBOL(tm6000_init_digital_mode);
  330. struct reg_init {
  331. u8 req;
  332. u8 reg;
  333. u8 val;
  334. };
  335. /* The meaning of those initializations are unknown */
  336. static struct reg_init tm6000_init_tab[] = {
  337. /* REG VALUE */
  338. { TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f },
  339. { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
  340. { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
  341. { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
  342. { TM6000_REQ07_RDA_CLK_SEL, 0x23 },
  343. { TM6000_REQ07_RDB_OUT_SEL, 0x08 },
  344. { TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x00 },
  345. { TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10 },
  346. { TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00 },
  347. { TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00 },
  348. { TM6000_REQ07_REB_VADC_AADC_MODE, 0x64 }, /* 48000 bits/sample, external input */
  349. { TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL, 0xc2 },
  350. { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
  351. { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
  352. { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
  353. { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
  354. { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
  355. { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
  356. { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
  357. { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
  358. { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
  359. { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
  360. { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
  361. { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
  362. { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
  363. { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
  364. { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
  365. { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
  366. { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
  367. { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
  368. { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
  369. { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
  370. { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
  371. { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
  372. { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
  373. { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
  374. { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
  375. { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
  376. { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
  377. { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
  378. { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
  379. { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
  380. { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
  381. { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
  382. { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
  383. { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
  384. { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
  385. { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
  386. { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
  387. { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
  388. { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
  389. { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
  390. { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
  391. { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
  392. { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
  393. { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
  394. { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
  395. { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
  396. { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
  397. { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
  398. { TM6010_REQ07_RC3_HSTART1, 0x88 },
  399. { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
  400. { TM6010_REQ05_R18_IMASK7, 0x00 },
  401. };
  402. static struct reg_init tm6010_init_tab[] = {
  403. { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
  404. { TM6010_REQ07_RC4_HSTART0, 0xa0 },
  405. { TM6010_REQ07_RC6_HEND0, 0x40 },
  406. { TM6010_REQ07_RCA_VEND0, 0x31 },
  407. { TM6010_REQ07_RCC_ACTIVE_IF, 0xe1 },
  408. { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
  409. { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
  410. { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
  411. { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
  412. { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
  413. { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
  414. { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
  415. { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
  416. { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
  417. { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
  418. { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
  419. { TM6010_REQ07_R3F_RESET, 0x01 },
  420. { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
  421. { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
  422. { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
  423. { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
  424. { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
  425. { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
  426. { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
  427. { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
  428. { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
  429. { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
  430. { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
  431. { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
  432. { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
  433. { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
  434. { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
  435. { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
  436. { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
  437. { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
  438. { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
  439. { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
  440. { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
  441. { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
  442. { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
  443. { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
  444. { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
  445. { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
  446. { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
  447. { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
  448. { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
  449. { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
  450. { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
  451. { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
  452. { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
  453. { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
  454. { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
  455. { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
  456. { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
  457. { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
  458. { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
  459. { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
  460. { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
  461. { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
  462. { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
  463. { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
  464. { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
  465. { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
  466. { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
  467. { TM6010_REQ07_RC3_HSTART1, 0x88 },
  468. { TM6010_REQ07_R3F_RESET, 0x00 },
  469. { TM6010_REQ05_R18_IMASK7, 0x00 },
  470. { TM6010_REQ07_RDC_IR_LEADER1, 0xaa },
  471. { TM6010_REQ07_RDD_IR_LEADER0, 0x30 },
  472. { TM6010_REQ07_RDE_IR_PULSE_CNT1, 0x20 },
  473. { TM6010_REQ07_RDF_IR_PULSE_CNT0, 0xd0 },
  474. { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
  475. { TM6010_REQ07_RD8_IR, 0x0f },
  476. /* set remote wakeup key:any key wakeup */
  477. { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
  478. { TM6010_REQ07_RDA_IR_WAKEUP_SEL, 0xff },
  479. };
  480. int tm6000_init(struct tm6000_core *dev)
  481. {
  482. int board, rc = 0, i, size;
  483. struct reg_init *tab;
  484. /* Check board revision */
  485. board = tm6000_get_reg32(dev, REQ_40_GET_VERSION, 0, 0);
  486. if (board >= 0) {
  487. switch (board & 0xff) {
  488. case 0xf3:
  489. printk(KERN_INFO "Found tm6000\n");
  490. if (dev->dev_type != TM6000)
  491. dev->dev_type = TM6000;
  492. break;
  493. case 0xf4:
  494. printk(KERN_INFO "Found tm6010\n");
  495. if (dev->dev_type != TM6010)
  496. dev->dev_type = TM6010;
  497. break;
  498. default:
  499. printk(KERN_INFO "Unknown board version = 0x%08x\n", board);
  500. }
  501. } else
  502. printk(KERN_ERR "Error %i while retrieving board version\n", board);
  503. if (dev->dev_type == TM6010) {
  504. tab = tm6010_init_tab;
  505. size = ARRAY_SIZE(tm6010_init_tab);
  506. } else {
  507. tab = tm6000_init_tab;
  508. size = ARRAY_SIZE(tm6000_init_tab);
  509. }
  510. /* Load board's initialization table */
  511. for (i = 0; i < size; i++) {
  512. rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val);
  513. if (rc < 0) {
  514. printk(KERN_ERR "Error %i while setting req %d, reg %d to value %d\n",
  515. rc,
  516. tab[i].req, tab[i].reg, tab[i].val);
  517. return rc;
  518. }
  519. }
  520. msleep(5); /* Just to be conservative */
  521. rc = tm6000_cards_setup(dev);
  522. return rc;
  523. }
  524. int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
  525. {
  526. int val = 0;
  527. u8 areg_f0 = 0x60; /* ADC MCLK = 250 Fs */
  528. u8 areg_0a = 0x91; /* SIF 48KHz */
  529. switch (bitrate) {
  530. case 48000:
  531. areg_f0 = 0x60; /* ADC MCLK = 250 Fs */
  532. areg_0a = 0x91; /* SIF 48KHz */
  533. dev->audio_bitrate = bitrate;
  534. break;
  535. case 32000:
  536. areg_f0 = 0x00; /* ADC MCLK = 375 Fs */
  537. areg_0a = 0x90; /* SIF 32KHz */
  538. dev->audio_bitrate = bitrate;
  539. break;
  540. default:
  541. return -EINVAL;
  542. }
  543. /* enable I2S, if we use sif or external I2S device */
  544. if (dev->dev_type == TM6010) {
  545. val = tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, areg_0a);
  546. if (val < 0)
  547. return val;
  548. val = tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
  549. areg_f0, 0xf0);
  550. if (val < 0)
  551. return val;
  552. } else {
  553. val = tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE,
  554. areg_f0, 0xf0);
  555. if (val < 0)
  556. return val;
  557. }
  558. return 0;
  559. }
  560. EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
  561. int tm6000_set_audio_rinput(struct tm6000_core *dev)
  562. {
  563. if (dev->dev_type == TM6010) {
  564. /* Audio crossbar setting, default SIF1 */
  565. u8 areg_f0;
  566. u8 areg_07 = 0x10;
  567. switch (dev->rinput.amux) {
  568. case TM6000_AMUX_SIF1:
  569. case TM6000_AMUX_SIF2:
  570. areg_f0 = 0x03;
  571. areg_07 = 0x30;
  572. break;
  573. case TM6000_AMUX_ADC1:
  574. areg_f0 = 0x00;
  575. break;
  576. case TM6000_AMUX_ADC2:
  577. areg_f0 = 0x08;
  578. break;
  579. case TM6000_AMUX_I2S:
  580. areg_f0 = 0x04;
  581. break;
  582. default:
  583. printk(KERN_INFO "%s: audio input dosn't support\n",
  584. dev->name);
  585. return 0;
  586. break;
  587. }
  588. /* Set audio input crossbar */
  589. tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
  590. areg_f0, 0x0f);
  591. /* Mux overflow workaround */
  592. tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL,
  593. areg_07, 0xf0);
  594. } else {
  595. u8 areg_eb;
  596. /* Audio setting, default LINE1 */
  597. switch (dev->rinput.amux) {
  598. case TM6000_AMUX_ADC1:
  599. areg_eb = 0x00;
  600. break;
  601. case TM6000_AMUX_ADC2:
  602. areg_eb = 0x04;
  603. break;
  604. default:
  605. printk(KERN_INFO "%s: audio input dosn't support\n",
  606. dev->name);
  607. return 0;
  608. break;
  609. }
  610. /* Set audio input */
  611. tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE,
  612. areg_eb, 0x0f);
  613. }
  614. return 0;
  615. }
  616. static void tm6010_set_mute_sif(struct tm6000_core *dev, u8 mute)
  617. {
  618. u8 mute_reg = 0;
  619. if (mute)
  620. mute_reg = 0x08;
  621. tm6000_set_reg_mask(dev, TM6010_REQ08_R0A_A_I2S_MOD, mute_reg, 0x08);
  622. }
  623. static void tm6010_set_mute_adc(struct tm6000_core *dev, u8 mute)
  624. {
  625. u8 mute_reg = 0;
  626. if (mute)
  627. mute_reg = 0x20;
  628. if (dev->dev_type == TM6010) {
  629. tm6000_set_reg_mask(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL,
  630. mute_reg, 0x20);
  631. tm6000_set_reg_mask(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL,
  632. mute_reg, 0x20);
  633. } else {
  634. tm6000_set_reg_mask(dev, TM6000_REQ07_REC_VADC_AADC_LVOL,
  635. mute_reg, 0x20);
  636. tm6000_set_reg_mask(dev, TM6000_REQ07_RED_VADC_AADC_RVOL,
  637. mute_reg, 0x20);
  638. }
  639. }
  640. int tm6000_tvaudio_set_mute(struct tm6000_core *dev, u8 mute)
  641. {
  642. enum tm6000_mux mux;
  643. if (dev->radio)
  644. mux = dev->rinput.amux;
  645. else
  646. mux = dev->vinput[dev->input].amux;
  647. switch (mux) {
  648. case TM6000_AMUX_SIF1:
  649. case TM6000_AMUX_SIF2:
  650. if (dev->dev_type == TM6010)
  651. tm6010_set_mute_sif(dev, mute);
  652. else {
  653. printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has SIF audio inputs. Please check the %s configuration.\n",
  654. dev->name);
  655. return -EINVAL;
  656. }
  657. break;
  658. case TM6000_AMUX_ADC1:
  659. case TM6000_AMUX_ADC2:
  660. tm6010_set_mute_adc(dev, mute);
  661. break;
  662. default:
  663. return -EINVAL;
  664. break;
  665. }
  666. return 0;
  667. }
  668. static void tm6010_set_volume_sif(struct tm6000_core *dev, int vol)
  669. {
  670. u8 vol_reg;
  671. vol_reg = vol & 0x0F;
  672. if (vol < 0)
  673. vol_reg |= 0x40;
  674. tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, vol_reg);
  675. tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, vol_reg);
  676. }
  677. static void tm6010_set_volume_adc(struct tm6000_core *dev, int vol)
  678. {
  679. u8 vol_reg;
  680. vol_reg = (vol + 0x10) & 0x1f;
  681. if (dev->dev_type == TM6010) {
  682. tm6000_set_reg(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL, vol_reg);
  683. tm6000_set_reg(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL, vol_reg);
  684. } else {
  685. tm6000_set_reg(dev, TM6000_REQ07_REC_VADC_AADC_LVOL, vol_reg);
  686. tm6000_set_reg(dev, TM6000_REQ07_RED_VADC_AADC_RVOL, vol_reg);
  687. }
  688. }
  689. void tm6000_set_volume(struct tm6000_core *dev, int vol)
  690. {
  691. enum tm6000_mux mux;
  692. if (dev->radio) {
  693. mux = dev->rinput.amux;
  694. vol += 8; /* Offset to 0 dB */
  695. } else
  696. mux = dev->vinput[dev->input].amux;
  697. switch (mux) {
  698. case TM6000_AMUX_SIF1:
  699. case TM6000_AMUX_SIF2:
  700. if (dev->dev_type == TM6010)
  701. tm6010_set_volume_sif(dev, vol);
  702. else
  703. printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has SIF audio inputs. Please check the %s configuration.\n",
  704. dev->name);
  705. break;
  706. case TM6000_AMUX_ADC1:
  707. case TM6000_AMUX_ADC2:
  708. tm6010_set_volume_adc(dev, vol);
  709. break;
  710. default:
  711. break;
  712. }
  713. }
  714. static LIST_HEAD(tm6000_devlist);
  715. static DEFINE_MUTEX(tm6000_devlist_mutex);
  716. /*
  717. * tm6000_realease_resource()
  718. */
  719. void tm6000_remove_from_devlist(struct tm6000_core *dev)
  720. {
  721. mutex_lock(&tm6000_devlist_mutex);
  722. list_del(&dev->devlist);
  723. mutex_unlock(&tm6000_devlist_mutex);
  724. };
  725. void tm6000_add_into_devlist(struct tm6000_core *dev)
  726. {
  727. mutex_lock(&tm6000_devlist_mutex);
  728. list_add_tail(&dev->devlist, &tm6000_devlist);
  729. mutex_unlock(&tm6000_devlist_mutex);
  730. };
  731. /*
  732. * Extension interface
  733. */
  734. static LIST_HEAD(tm6000_extension_devlist);
  735. int tm6000_call_fillbuf(struct tm6000_core *dev, enum tm6000_ops_type type,
  736. char *buf, int size)
  737. {
  738. struct tm6000_ops *ops = NULL;
  739. /* FIXME: tm6000_extension_devlist_lock should be a spinlock */
  740. if (!list_empty(&tm6000_extension_devlist)) {
  741. list_for_each_entry(ops, &tm6000_extension_devlist, next) {
  742. if (ops->fillbuf && ops->type == type)
  743. ops->fillbuf(dev, buf, size);
  744. }
  745. }
  746. return 0;
  747. }
  748. int tm6000_register_extension(struct tm6000_ops *ops)
  749. {
  750. struct tm6000_core *dev = NULL;
  751. mutex_lock(&tm6000_devlist_mutex);
  752. list_add_tail(&ops->next, &tm6000_extension_devlist);
  753. list_for_each_entry(dev, &tm6000_devlist, devlist) {
  754. ops->init(dev);
  755. printk(KERN_INFO "%s: Initialized (%s) extension\n",
  756. dev->name, ops->name);
  757. }
  758. mutex_unlock(&tm6000_devlist_mutex);
  759. return 0;
  760. }
  761. EXPORT_SYMBOL(tm6000_register_extension);
  762. void tm6000_unregister_extension(struct tm6000_ops *ops)
  763. {
  764. struct tm6000_core *dev = NULL;
  765. mutex_lock(&tm6000_devlist_mutex);
  766. list_for_each_entry(dev, &tm6000_devlist, devlist)
  767. ops->fini(dev);
  768. printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name);
  769. list_del(&ops->next);
  770. mutex_unlock(&tm6000_devlist_mutex);
  771. }
  772. EXPORT_SYMBOL(tm6000_unregister_extension);
  773. void tm6000_init_extension(struct tm6000_core *dev)
  774. {
  775. struct tm6000_ops *ops = NULL;
  776. mutex_lock(&tm6000_devlist_mutex);
  777. if (!list_empty(&tm6000_extension_devlist)) {
  778. list_for_each_entry(ops, &tm6000_extension_devlist, next) {
  779. if (ops->init)
  780. ops->init(dev);
  781. }
  782. }
  783. mutex_unlock(&tm6000_devlist_mutex);
  784. }
  785. void tm6000_close_extension(struct tm6000_core *dev)
  786. {
  787. struct tm6000_ops *ops = NULL;
  788. mutex_lock(&tm6000_devlist_mutex);
  789. if (!list_empty(&tm6000_extension_devlist)) {
  790. list_for_each_entry(ops, &tm6000_extension_devlist, next) {
  791. if (ops->fini)
  792. ops->fini(dev);
  793. }
  794. }
  795. mutex_unlock(&tm6000_devlist_mutex);
  796. }