fimc-isp.c 20 KB

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  1. /*
  2. * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
  3. *
  4. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  5. *
  6. * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
  7. * Younghwan Joo <yhwan.joo@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  14. #include <linux/device.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/printk.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/slab.h>
  23. #include <linux/types.h>
  24. #include <media/v4l2-device.h>
  25. #include "media-dev.h"
  26. #include "fimc-isp-video.h"
  27. #include "fimc-is-command.h"
  28. #include "fimc-is-param.h"
  29. #include "fimc-is-regs.h"
  30. #include "fimc-is.h"
  31. int fimc_isp_debug;
  32. module_param_named(debug_isp, fimc_isp_debug, int, S_IRUGO | S_IWUSR);
  33. static const struct fimc_fmt fimc_isp_formats[FIMC_ISP_NUM_FORMATS] = {
  34. {
  35. .name = "RAW8 (GRBG)",
  36. .fourcc = V4L2_PIX_FMT_SGRBG8,
  37. .depth = { 8 },
  38. .color = FIMC_FMT_RAW8,
  39. .memplanes = 1,
  40. .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
  41. }, {
  42. .name = "RAW10 (GRBG)",
  43. .fourcc = V4L2_PIX_FMT_SGRBG10,
  44. .depth = { 10 },
  45. .color = FIMC_FMT_RAW10,
  46. .memplanes = 1,
  47. .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
  48. }, {
  49. .name = "RAW12 (GRBG)",
  50. .fourcc = V4L2_PIX_FMT_SGRBG12,
  51. .depth = { 12 },
  52. .color = FIMC_FMT_RAW12,
  53. .memplanes = 1,
  54. .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
  55. },
  56. };
  57. /**
  58. * fimc_isp_find_format - lookup color format by fourcc or media bus code
  59. * @pixelformat: fourcc to match, ignored if null
  60. * @mbus_code: media bus code to match, ignored if null
  61. * @index: index to the fimc_isp_formats array, ignored if negative
  62. */
  63. const struct fimc_fmt *fimc_isp_find_format(const u32 *pixelformat,
  64. const u32 *mbus_code, int index)
  65. {
  66. const struct fimc_fmt *fmt, *def_fmt = NULL;
  67. unsigned int i;
  68. int id = 0;
  69. if (index >= (int)ARRAY_SIZE(fimc_isp_formats))
  70. return NULL;
  71. for (i = 0; i < ARRAY_SIZE(fimc_isp_formats); ++i) {
  72. fmt = &fimc_isp_formats[i];
  73. if (pixelformat && fmt->fourcc == *pixelformat)
  74. return fmt;
  75. if (mbus_code && fmt->mbus_code == *mbus_code)
  76. return fmt;
  77. if (index == id)
  78. def_fmt = fmt;
  79. id++;
  80. }
  81. return def_fmt;
  82. }
  83. void fimc_isp_irq_handler(struct fimc_is *is)
  84. {
  85. is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20));
  86. is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21));
  87. fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP);
  88. fimc_isp_video_irq_handler(is);
  89. wake_up(&is->irq_queue);
  90. }
  91. /* Capture subdev media entity operations */
  92. static int fimc_is_link_setup(struct media_entity *entity,
  93. const struct media_pad *local,
  94. const struct media_pad *remote, u32 flags)
  95. {
  96. return 0;
  97. }
  98. static const struct media_entity_operations fimc_is_subdev_media_ops = {
  99. .link_setup = fimc_is_link_setup,
  100. };
  101. static int fimc_is_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  102. struct v4l2_subdev_pad_config *cfg,
  103. struct v4l2_subdev_mbus_code_enum *code)
  104. {
  105. const struct fimc_fmt *fmt;
  106. fmt = fimc_isp_find_format(NULL, NULL, code->index);
  107. if (!fmt)
  108. return -EINVAL;
  109. code->code = fmt->mbus_code;
  110. return 0;
  111. }
  112. static int fimc_isp_subdev_get_fmt(struct v4l2_subdev *sd,
  113. struct v4l2_subdev_pad_config *cfg,
  114. struct v4l2_subdev_format *fmt)
  115. {
  116. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  117. struct v4l2_mbus_framefmt *mf = &fmt->format;
  118. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  119. *mf = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
  120. return 0;
  121. }
  122. mf->colorspace = V4L2_COLORSPACE_SRGB;
  123. mutex_lock(&isp->subdev_lock);
  124. if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
  125. /* ISP OTF input image format */
  126. *mf = isp->sink_fmt;
  127. } else {
  128. /* ISP OTF output image format */
  129. *mf = isp->src_fmt;
  130. if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
  131. mf->colorspace = V4L2_COLORSPACE_JPEG;
  132. mf->code = MEDIA_BUS_FMT_YUV10_1X30;
  133. }
  134. }
  135. mutex_unlock(&isp->subdev_lock);
  136. isp_dbg(1, sd, "%s: pad%d: fmt: 0x%x, %dx%d\n", __func__,
  137. fmt->pad, mf->code, mf->width, mf->height);
  138. return 0;
  139. }
  140. static void __isp_subdev_try_format(struct fimc_isp *isp,
  141. struct v4l2_subdev_pad_config *cfg,
  142. struct v4l2_subdev_format *fmt)
  143. {
  144. struct v4l2_mbus_framefmt *mf = &fmt->format;
  145. struct v4l2_mbus_framefmt *format;
  146. mf->colorspace = V4L2_COLORSPACE_SRGB;
  147. if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
  148. v4l_bound_align_image(&mf->width, FIMC_ISP_SINK_WIDTH_MIN,
  149. FIMC_ISP_SINK_WIDTH_MAX, 0,
  150. &mf->height, FIMC_ISP_SINK_HEIGHT_MIN,
  151. FIMC_ISP_SINK_HEIGHT_MAX, 0, 0);
  152. mf->code = MEDIA_BUS_FMT_SGRBG10_1X10;
  153. } else {
  154. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
  155. format = v4l2_subdev_get_try_format(&isp->subdev, cfg,
  156. FIMC_ISP_SD_PAD_SINK);
  157. else
  158. format = &isp->sink_fmt;
  159. /* Allow changing format only on sink pad */
  160. mf->width = format->width - FIMC_ISP_CAC_MARGIN_WIDTH;
  161. mf->height = format->height - FIMC_ISP_CAC_MARGIN_HEIGHT;
  162. if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
  163. mf->code = MEDIA_BUS_FMT_YUV10_1X30;
  164. mf->colorspace = V4L2_COLORSPACE_JPEG;
  165. } else {
  166. mf->code = format->code;
  167. }
  168. }
  169. }
  170. static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,
  171. struct v4l2_subdev_pad_config *cfg,
  172. struct v4l2_subdev_format *fmt)
  173. {
  174. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  175. struct fimc_is *is = fimc_isp_to_is(isp);
  176. struct v4l2_mbus_framefmt *mf = &fmt->format;
  177. int ret = 0;
  178. isp_dbg(1, sd, "%s: pad%d: code: 0x%x, %dx%d\n",
  179. __func__, fmt->pad, mf->code, mf->width, mf->height);
  180. mutex_lock(&isp->subdev_lock);
  181. __isp_subdev_try_format(isp, cfg, fmt);
  182. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  183. mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
  184. *mf = fmt->format;
  185. /* Propagate format to the source pads */
  186. if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
  187. struct v4l2_subdev_format format = *fmt;
  188. unsigned int pad;
  189. for (pad = FIMC_ISP_SD_PAD_SRC_FIFO;
  190. pad < FIMC_ISP_SD_PADS_NUM; pad++) {
  191. format.pad = pad;
  192. __isp_subdev_try_format(isp, cfg, &format);
  193. mf = v4l2_subdev_get_try_format(sd, cfg, pad);
  194. *mf = format.format;
  195. }
  196. }
  197. } else {
  198. if (sd->entity.stream_count == 0) {
  199. if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
  200. struct v4l2_subdev_format format = *fmt;
  201. isp->sink_fmt = *mf;
  202. format.pad = FIMC_ISP_SD_PAD_SRC_DMA;
  203. __isp_subdev_try_format(isp, cfg, &format);
  204. isp->src_fmt = format.format;
  205. __is_set_frame_size(is, &isp->src_fmt);
  206. } else {
  207. isp->src_fmt = *mf;
  208. }
  209. } else {
  210. ret = -EBUSY;
  211. }
  212. }
  213. mutex_unlock(&isp->subdev_lock);
  214. return ret;
  215. }
  216. static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
  217. {
  218. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  219. struct fimc_is *is = fimc_isp_to_is(isp);
  220. int ret;
  221. isp_dbg(1, sd, "%s: on: %d\n", __func__, on);
  222. if (!test_bit(IS_ST_INIT_DONE, &is->state))
  223. return -EBUSY;
  224. fimc_is_mem_barrier();
  225. if (on) {
  226. if (__get_pending_param_count(is)) {
  227. ret = fimc_is_itf_s_param(is, true);
  228. if (ret < 0)
  229. return ret;
  230. }
  231. isp_dbg(1, sd, "changing mode to %d\n", is->config_index);
  232. ret = fimc_is_itf_mode_change(is);
  233. if (ret)
  234. return -EINVAL;
  235. clear_bit(IS_ST_STREAM_ON, &is->state);
  236. fimc_is_hw_stream_on(is);
  237. ret = fimc_is_wait_event(is, IS_ST_STREAM_ON, 1,
  238. FIMC_IS_CONFIG_TIMEOUT);
  239. if (ret < 0) {
  240. v4l2_err(sd, "stream on timeout\n");
  241. return ret;
  242. }
  243. } else {
  244. clear_bit(IS_ST_STREAM_OFF, &is->state);
  245. fimc_is_hw_stream_off(is);
  246. ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
  247. FIMC_IS_CONFIG_TIMEOUT);
  248. if (ret < 0) {
  249. v4l2_err(sd, "stream off timeout\n");
  250. return ret;
  251. }
  252. is->setfile.sub_index = 0;
  253. }
  254. return 0;
  255. }
  256. static int fimc_isp_subdev_s_power(struct v4l2_subdev *sd, int on)
  257. {
  258. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  259. struct fimc_is *is = fimc_isp_to_is(isp);
  260. int ret = 0;
  261. pr_debug("on: %d\n", on);
  262. if (on) {
  263. ret = pm_runtime_get_sync(&is->pdev->dev);
  264. if (ret < 0)
  265. return ret;
  266. set_bit(IS_ST_PWR_ON, &is->state);
  267. ret = fimc_is_start_firmware(is);
  268. if (ret < 0) {
  269. v4l2_err(sd, "firmware booting failed\n");
  270. pm_runtime_put(&is->pdev->dev);
  271. return ret;
  272. }
  273. set_bit(IS_ST_PWR_SUBIP_ON, &is->state);
  274. ret = fimc_is_hw_initialize(is);
  275. } else {
  276. /* Close sensor */
  277. if (!test_bit(IS_ST_PWR_ON, &is->state)) {
  278. fimc_is_hw_close_sensor(is, 0);
  279. ret = fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 0,
  280. FIMC_IS_CONFIG_TIMEOUT);
  281. if (ret < 0) {
  282. v4l2_err(sd, "sensor close timeout\n");
  283. return ret;
  284. }
  285. }
  286. /* SUB IP power off */
  287. if (test_bit(IS_ST_PWR_SUBIP_ON, &is->state)) {
  288. fimc_is_hw_subip_power_off(is);
  289. ret = fimc_is_wait_event(is, IS_ST_PWR_SUBIP_ON, 0,
  290. FIMC_IS_CONFIG_TIMEOUT);
  291. if (ret < 0) {
  292. v4l2_err(sd, "sub-IP power off timeout\n");
  293. return ret;
  294. }
  295. }
  296. fimc_is_cpu_set_power(is, 0);
  297. pm_runtime_put_sync(&is->pdev->dev);
  298. clear_bit(IS_ST_PWR_ON, &is->state);
  299. clear_bit(IS_ST_INIT_DONE, &is->state);
  300. is->state = 0;
  301. is->config[is->config_index].p_region_index[0] = 0;
  302. is->config[is->config_index].p_region_index[1] = 0;
  303. set_bit(IS_ST_IDLE, &is->state);
  304. wmb();
  305. }
  306. return ret;
  307. }
  308. static int fimc_isp_subdev_open(struct v4l2_subdev *sd,
  309. struct v4l2_subdev_fh *fh)
  310. {
  311. struct v4l2_mbus_framefmt *format;
  312. struct v4l2_mbus_framefmt fmt = {
  313. .colorspace = V4L2_COLORSPACE_SRGB,
  314. .code = fimc_isp_formats[0].mbus_code,
  315. .width = DEFAULT_PREVIEW_STILL_WIDTH + FIMC_ISP_CAC_MARGIN_WIDTH,
  316. .height = DEFAULT_PREVIEW_STILL_HEIGHT + FIMC_ISP_CAC_MARGIN_HEIGHT,
  317. .field = V4L2_FIELD_NONE,
  318. };
  319. format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SINK);
  320. *format = fmt;
  321. format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SRC_FIFO);
  322. fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
  323. fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  324. *format = fmt;
  325. format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SRC_DMA);
  326. *format = fmt;
  327. return 0;
  328. }
  329. static int fimc_isp_subdev_registered(struct v4l2_subdev *sd)
  330. {
  331. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  332. int ret;
  333. /* Use pipeline object allocated by the media device. */
  334. isp->video_capture.ve.pipe = v4l2_get_subdev_hostdata(sd);
  335. ret = fimc_isp_video_device_register(isp, sd->v4l2_dev,
  336. V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
  337. if (ret < 0)
  338. isp->video_capture.ve.pipe = NULL;
  339. return ret;
  340. }
  341. static void fimc_isp_subdev_unregistered(struct v4l2_subdev *sd)
  342. {
  343. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  344. fimc_isp_video_device_unregister(isp,
  345. V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
  346. }
  347. static const struct v4l2_subdev_internal_ops fimc_is_subdev_internal_ops = {
  348. .registered = fimc_isp_subdev_registered,
  349. .unregistered = fimc_isp_subdev_unregistered,
  350. .open = fimc_isp_subdev_open,
  351. };
  352. static const struct v4l2_subdev_pad_ops fimc_is_subdev_pad_ops = {
  353. .enum_mbus_code = fimc_is_subdev_enum_mbus_code,
  354. .get_fmt = fimc_isp_subdev_get_fmt,
  355. .set_fmt = fimc_isp_subdev_set_fmt,
  356. };
  357. static const struct v4l2_subdev_video_ops fimc_is_subdev_video_ops = {
  358. .s_stream = fimc_isp_subdev_s_stream,
  359. };
  360. static const struct v4l2_subdev_core_ops fimc_is_core_ops = {
  361. .s_power = fimc_isp_subdev_s_power,
  362. };
  363. static const struct v4l2_subdev_ops fimc_is_subdev_ops = {
  364. .core = &fimc_is_core_ops,
  365. .video = &fimc_is_subdev_video_ops,
  366. .pad = &fimc_is_subdev_pad_ops,
  367. };
  368. static int __ctrl_set_white_balance(struct fimc_is *is, int value)
  369. {
  370. switch (value) {
  371. case V4L2_WHITE_BALANCE_AUTO:
  372. __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
  373. break;
  374. case V4L2_WHITE_BALANCE_DAYLIGHT:
  375. __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
  376. ISP_AWB_ILLUMINATION_DAYLIGHT);
  377. break;
  378. case V4L2_WHITE_BALANCE_CLOUDY:
  379. __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
  380. ISP_AWB_ILLUMINATION_CLOUDY);
  381. break;
  382. case V4L2_WHITE_BALANCE_INCANDESCENT:
  383. __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
  384. ISP_AWB_ILLUMINATION_TUNGSTEN);
  385. break;
  386. case V4L2_WHITE_BALANCE_FLUORESCENT:
  387. __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
  388. ISP_AWB_ILLUMINATION_FLUORESCENT);
  389. break;
  390. default:
  391. return -EINVAL;
  392. }
  393. return 0;
  394. }
  395. static int __ctrl_set_aewb_lock(struct fimc_is *is,
  396. struct v4l2_ctrl *ctrl)
  397. {
  398. bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
  399. bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
  400. struct isp_param *isp = &is->is_p_region->parameter.isp;
  401. int cmd, ret;
  402. cmd = ae_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
  403. isp->aa.cmd = cmd;
  404. isp->aa.target = ISP_AA_TARGET_AE;
  405. fimc_is_set_param_bit(is, PARAM_ISP_AA);
  406. is->af.ae_lock_state = ae_lock;
  407. wmb();
  408. ret = fimc_is_itf_s_param(is, false);
  409. if (ret < 0)
  410. return ret;
  411. cmd = awb_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
  412. isp->aa.cmd = cmd;
  413. isp->aa.target = ISP_AA_TARGET_AE;
  414. fimc_is_set_param_bit(is, PARAM_ISP_AA);
  415. is->af.awb_lock_state = awb_lock;
  416. wmb();
  417. return fimc_is_itf_s_param(is, false);
  418. }
  419. /* Supported manual ISO values */
  420. static const s64 iso_qmenu[] = {
  421. 50, 100, 200, 400, 800,
  422. };
  423. static int __ctrl_set_iso(struct fimc_is *is, int value)
  424. {
  425. unsigned int idx, iso;
  426. if (value == V4L2_ISO_SENSITIVITY_AUTO) {
  427. __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
  428. return 0;
  429. }
  430. idx = is->isp.ctrls.iso->val;
  431. if (idx >= ARRAY_SIZE(iso_qmenu))
  432. return -EINVAL;
  433. iso = iso_qmenu[idx];
  434. __is_set_isp_iso(is, ISP_ISO_COMMAND_MANUAL, iso);
  435. return 0;
  436. }
  437. static int __ctrl_set_metering(struct fimc_is *is, unsigned int value)
  438. {
  439. unsigned int val;
  440. switch (value) {
  441. case V4L2_EXPOSURE_METERING_AVERAGE:
  442. val = ISP_METERING_COMMAND_AVERAGE;
  443. break;
  444. case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
  445. val = ISP_METERING_COMMAND_CENTER;
  446. break;
  447. case V4L2_EXPOSURE_METERING_SPOT:
  448. val = ISP_METERING_COMMAND_SPOT;
  449. break;
  450. case V4L2_EXPOSURE_METERING_MATRIX:
  451. val = ISP_METERING_COMMAND_MATRIX;
  452. break;
  453. default:
  454. return -EINVAL;
  455. }
  456. __is_set_isp_metering(is, IS_METERING_CONFIG_CMD, val);
  457. return 0;
  458. }
  459. static int __ctrl_set_afc(struct fimc_is *is, int value)
  460. {
  461. switch (value) {
  462. case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
  463. __is_set_isp_afc(is, ISP_AFC_COMMAND_DISABLE, 0);
  464. break;
  465. case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
  466. __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 50);
  467. break;
  468. case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
  469. __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 60);
  470. break;
  471. case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
  472. __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
  473. break;
  474. default:
  475. return -EINVAL;
  476. }
  477. return 0;
  478. }
  479. static int __ctrl_set_image_effect(struct fimc_is *is, int value)
  480. {
  481. static const u8 effects[][2] = {
  482. { V4L2_COLORFX_NONE, ISP_IMAGE_EFFECT_DISABLE },
  483. { V4L2_COLORFX_BW, ISP_IMAGE_EFFECT_MONOCHROME },
  484. { V4L2_COLORFX_SEPIA, ISP_IMAGE_EFFECT_SEPIA },
  485. { V4L2_COLORFX_NEGATIVE, ISP_IMAGE_EFFECT_NEGATIVE_MONO },
  486. { 16 /* TODO */, ISP_IMAGE_EFFECT_NEGATIVE_COLOR },
  487. };
  488. int i;
  489. for (i = 0; i < ARRAY_SIZE(effects); i++) {
  490. if (effects[i][0] != value)
  491. continue;
  492. __is_set_isp_effect(is, effects[i][1]);
  493. return 0;
  494. }
  495. return -EINVAL;
  496. }
  497. static int fimc_is_s_ctrl(struct v4l2_ctrl *ctrl)
  498. {
  499. struct fimc_isp *isp = ctrl_to_fimc_isp(ctrl);
  500. struct fimc_is *is = fimc_isp_to_is(isp);
  501. bool set_param = true;
  502. int ret = 0;
  503. switch (ctrl->id) {
  504. case V4L2_CID_CONTRAST:
  505. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST,
  506. ctrl->val);
  507. break;
  508. case V4L2_CID_SATURATION:
  509. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SATURATION,
  510. ctrl->val);
  511. break;
  512. case V4L2_CID_SHARPNESS:
  513. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS,
  514. ctrl->val);
  515. break;
  516. case V4L2_CID_EXPOSURE_ABSOLUTE:
  517. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE,
  518. ctrl->val);
  519. break;
  520. case V4L2_CID_BRIGHTNESS:
  521. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS,
  522. ctrl->val);
  523. break;
  524. case V4L2_CID_HUE:
  525. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE,
  526. ctrl->val);
  527. break;
  528. case V4L2_CID_EXPOSURE_METERING:
  529. ret = __ctrl_set_metering(is, ctrl->val);
  530. break;
  531. case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
  532. ret = __ctrl_set_white_balance(is, ctrl->val);
  533. break;
  534. case V4L2_CID_3A_LOCK:
  535. ret = __ctrl_set_aewb_lock(is, ctrl);
  536. set_param = false;
  537. break;
  538. case V4L2_CID_ISO_SENSITIVITY_AUTO:
  539. ret = __ctrl_set_iso(is, ctrl->val);
  540. break;
  541. case V4L2_CID_POWER_LINE_FREQUENCY:
  542. ret = __ctrl_set_afc(is, ctrl->val);
  543. break;
  544. case V4L2_CID_COLORFX:
  545. __ctrl_set_image_effect(is, ctrl->val);
  546. break;
  547. default:
  548. ret = -EINVAL;
  549. break;
  550. }
  551. if (ret < 0) {
  552. v4l2_err(&isp->subdev, "Failed to set control: %s (%d)\n",
  553. ctrl->name, ctrl->val);
  554. return ret;
  555. }
  556. if (set_param && test_bit(IS_ST_STREAM_ON, &is->state))
  557. return fimc_is_itf_s_param(is, true);
  558. return 0;
  559. }
  560. static const struct v4l2_ctrl_ops fimc_isp_ctrl_ops = {
  561. .s_ctrl = fimc_is_s_ctrl,
  562. };
  563. static void __isp_subdev_set_default_format(struct fimc_isp *isp)
  564. {
  565. struct fimc_is *is = fimc_isp_to_is(isp);
  566. isp->sink_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH +
  567. FIMC_ISP_CAC_MARGIN_WIDTH;
  568. isp->sink_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT +
  569. FIMC_ISP_CAC_MARGIN_HEIGHT;
  570. isp->sink_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
  571. isp->src_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
  572. isp->src_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  573. isp->src_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
  574. __is_set_frame_size(is, &isp->src_fmt);
  575. }
  576. int fimc_isp_subdev_create(struct fimc_isp *isp)
  577. {
  578. const struct v4l2_ctrl_ops *ops = &fimc_isp_ctrl_ops;
  579. struct v4l2_ctrl_handler *handler = &isp->ctrls.handler;
  580. struct v4l2_subdev *sd = &isp->subdev;
  581. struct fimc_isp_ctrls *ctrls = &isp->ctrls;
  582. int ret;
  583. mutex_init(&isp->subdev_lock);
  584. v4l2_subdev_init(sd, &fimc_is_subdev_ops);
  585. sd->owner = THIS_MODULE;
  586. sd->grp_id = GRP_ID_FIMC_IS;
  587. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  588. snprintf(sd->name, sizeof(sd->name), "FIMC-IS-ISP");
  589. sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
  590. isp->subdev_pads[FIMC_ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  591. isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
  592. isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
  593. ret = media_entity_pads_init(&sd->entity, FIMC_ISP_SD_PADS_NUM,
  594. isp->subdev_pads);
  595. if (ret)
  596. return ret;
  597. v4l2_ctrl_handler_init(handler, 20);
  598. ctrls->saturation = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SATURATION,
  599. -2, 2, 1, 0);
  600. ctrls->brightness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_BRIGHTNESS,
  601. -4, 4, 1, 0);
  602. ctrls->contrast = v4l2_ctrl_new_std(handler, ops, V4L2_CID_CONTRAST,
  603. -2, 2, 1, 0);
  604. ctrls->sharpness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SHARPNESS,
  605. -2, 2, 1, 0);
  606. ctrls->hue = v4l2_ctrl_new_std(handler, ops, V4L2_CID_HUE,
  607. -2, 2, 1, 0);
  608. ctrls->auto_wb = v4l2_ctrl_new_std_menu(handler, ops,
  609. V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
  610. 8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);
  611. ctrls->exposure = v4l2_ctrl_new_std(handler, ops,
  612. V4L2_CID_EXPOSURE_ABSOLUTE,
  613. -4, 4, 1, 0);
  614. ctrls->exp_metering = v4l2_ctrl_new_std_menu(handler, ops,
  615. V4L2_CID_EXPOSURE_METERING, 3,
  616. ~0xf, V4L2_EXPOSURE_METERING_AVERAGE);
  617. v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_POWER_LINE_FREQUENCY,
  618. V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
  619. V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
  620. /* ISO sensitivity */
  621. ctrls->auto_iso = v4l2_ctrl_new_std_menu(handler, ops,
  622. V4L2_CID_ISO_SENSITIVITY_AUTO, 1, 0,
  623. V4L2_ISO_SENSITIVITY_AUTO);
  624. ctrls->iso = v4l2_ctrl_new_int_menu(handler, ops,
  625. V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
  626. ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
  627. ctrls->aewb_lock = v4l2_ctrl_new_std(handler, ops,
  628. V4L2_CID_3A_LOCK, 0, 0x3, 0, 0);
  629. /* TODO: Add support for NEGATIVE_COLOR option */
  630. ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_COLORFX,
  631. V4L2_COLORFX_SET_CBCR + 1, ~0x1000f, V4L2_COLORFX_NONE);
  632. if (handler->error) {
  633. media_entity_cleanup(&sd->entity);
  634. return handler->error;
  635. }
  636. v4l2_ctrl_auto_cluster(2, &ctrls->auto_iso,
  637. V4L2_ISO_SENSITIVITY_MANUAL, false);
  638. sd->ctrl_handler = handler;
  639. sd->internal_ops = &fimc_is_subdev_internal_ops;
  640. sd->entity.ops = &fimc_is_subdev_media_ops;
  641. v4l2_set_subdevdata(sd, isp);
  642. __isp_subdev_set_default_format(isp);
  643. return 0;
  644. }
  645. void fimc_isp_subdev_destroy(struct fimc_isp *isp)
  646. {
  647. struct v4l2_subdev *sd = &isp->subdev;
  648. v4l2_device_unregister_subdev(sd);
  649. media_entity_cleanup(&sd->entity);
  650. v4l2_ctrl_handler_free(&isp->ctrls.handler);
  651. v4l2_set_subdevdata(sd, NULL);
  652. }