pt1.c 31 KB

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  1. /*
  2. * driver for Earthsoft PT1/PT2
  3. *
  4. * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
  5. *
  6. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  7. * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/sched.h>
  21. #include <linux/sched/signal.h>
  22. #include <linux/hrtimer.h>
  23. #include <linux/delay.h>
  24. #include <linux/module.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/pci.h>
  28. #include <linux/kthread.h>
  29. #include <linux/freezer.h>
  30. #include <linux/ratelimit.h>
  31. #include <linux/string.h>
  32. #include <linux/i2c.h>
  33. #include <media/dvbdev.h>
  34. #include <media/dvb_demux.h>
  35. #include <media/dmxdev.h>
  36. #include <media/dvb_net.h>
  37. #include <media/dvb_frontend.h>
  38. #include "tc90522.h"
  39. #include "qm1d1b0004.h"
  40. #include "dvb-pll.h"
  41. #define DRIVER_NAME "earth-pt1"
  42. #define PT1_PAGE_SHIFT 12
  43. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  44. #define PT1_NR_UPACKETS 1024
  45. #define PT1_NR_BUFS 511
  46. struct pt1_buffer_page {
  47. __le32 upackets[PT1_NR_UPACKETS];
  48. };
  49. struct pt1_table_page {
  50. __le32 next_pfn;
  51. __le32 buf_pfns[PT1_NR_BUFS];
  52. };
  53. struct pt1_buffer {
  54. struct pt1_buffer_page *page;
  55. dma_addr_t addr;
  56. };
  57. struct pt1_table {
  58. struct pt1_table_page *page;
  59. dma_addr_t addr;
  60. struct pt1_buffer bufs[PT1_NR_BUFS];
  61. };
  62. enum pt1_fe_clk {
  63. PT1_FE_CLK_20MHZ, /* PT1 */
  64. PT1_FE_CLK_25MHZ, /* PT2 */
  65. };
  66. #define PT1_NR_ADAPS 4
  67. struct pt1_adapter;
  68. struct pt1 {
  69. struct pci_dev *pdev;
  70. void __iomem *regs;
  71. struct i2c_adapter i2c_adap;
  72. int i2c_running;
  73. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  74. struct pt1_table *tables;
  75. struct task_struct *kthread;
  76. int table_index;
  77. int buf_index;
  78. struct mutex lock;
  79. int power;
  80. int reset;
  81. enum pt1_fe_clk fe_clk;
  82. };
  83. struct pt1_adapter {
  84. struct pt1 *pt1;
  85. int index;
  86. u8 *buf;
  87. int upacket_count;
  88. int packet_count;
  89. int st_count;
  90. struct dvb_adapter adap;
  91. struct dvb_demux demux;
  92. int users;
  93. struct dmxdev dmxdev;
  94. struct dvb_frontend *fe;
  95. struct i2c_client *demod_i2c_client;
  96. struct i2c_client *tuner_i2c_client;
  97. int (*orig_set_voltage)(struct dvb_frontend *fe,
  98. enum fe_sec_voltage voltage);
  99. int (*orig_sleep)(struct dvb_frontend *fe);
  100. int (*orig_init)(struct dvb_frontend *fe);
  101. enum fe_sec_voltage voltage;
  102. int sleep;
  103. };
  104. union pt1_tuner_config {
  105. struct qm1d1b0004_config qm1d1b0004;
  106. struct dvb_pll_config tda6651;
  107. };
  108. struct pt1_config {
  109. struct i2c_board_info demod_info;
  110. struct tc90522_config demod_cfg;
  111. struct i2c_board_info tuner_info;
  112. union pt1_tuner_config tuner_cfg;
  113. };
  114. static const struct pt1_config pt1_configs[PT1_NR_ADAPS] = {
  115. {
  116. .demod_info = {
  117. I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x1b),
  118. },
  119. .tuner_info = {
  120. I2C_BOARD_INFO("qm1d1b0004", 0x60),
  121. },
  122. },
  123. {
  124. .demod_info = {
  125. I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x1a),
  126. },
  127. .tuner_info = {
  128. I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
  129. },
  130. },
  131. {
  132. .demod_info = {
  133. I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x19),
  134. },
  135. .tuner_info = {
  136. I2C_BOARD_INFO("qm1d1b0004", 0x60),
  137. },
  138. },
  139. {
  140. .demod_info = {
  141. I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x18),
  142. },
  143. .tuner_info = {
  144. I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
  145. },
  146. },
  147. };
  148. static const u8 va1j5jf8007s_20mhz_configs[][2] = {
  149. {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01},
  150. {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0},
  151. {0x52, 0x89}, {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69},
  152. {0x87, 0x04}, {0x8e, 0x02}, {0xa3, 0xf7}, {0xa5, 0xc0},
  153. };
  154. static const u8 va1j5jf8007s_25mhz_configs[][2] = {
  155. {0x04, 0x02}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01}, {0x1c, 0x0a},
  156. {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0}, {0x52, 0x89},
  157. {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69}, {0x87, 0x04},
  158. {0x8e, 0x26}, {0xa3, 0xf7}, {0xa5, 0xc0},
  159. };
  160. static const u8 va1j5jf8007t_20mhz_configs[][2] = {
  161. {0x03, 0x90}, {0x14, 0x8f}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2},
  162. {0x22, 0x83}, {0x31, 0x0d}, {0x32, 0xe0}, {0x39, 0xd3}, {0x3a, 0x00},
  163. {0x3b, 0x11}, {0x3c, 0x3f},
  164. {0x5c, 0x40}, {0x5f, 0x80}, {0x75, 0x02}, {0x76, 0x4e}, {0x77, 0x03},
  165. {0xef, 0x01}
  166. };
  167. static const u8 va1j5jf8007t_25mhz_configs[][2] = {
  168. {0x03, 0x90}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, {0x22, 0x83},
  169. {0x3a, 0x04}, {0x3b, 0x11}, {0x3c, 0x3f}, {0x5c, 0x40}, {0x5f, 0x80},
  170. {0x75, 0x0a}, {0x76, 0x4c}, {0x77, 0x03}, {0xef, 0x01}
  171. };
  172. static int config_demod(struct i2c_client *cl, enum pt1_fe_clk clk)
  173. {
  174. int ret;
  175. bool is_sat;
  176. const u8 (*cfg_data)[2];
  177. int i, len;
  178. is_sat = !strncmp(cl->name, TC90522_I2C_DEV_SAT,
  179. strlen(TC90522_I2C_DEV_SAT));
  180. if (is_sat) {
  181. struct i2c_msg msg[2];
  182. u8 wbuf, rbuf;
  183. wbuf = 0x07;
  184. msg[0].addr = cl->addr;
  185. msg[0].flags = 0;
  186. msg[0].len = 1;
  187. msg[0].buf = &wbuf;
  188. msg[1].addr = cl->addr;
  189. msg[1].flags = I2C_M_RD;
  190. msg[1].len = 1;
  191. msg[1].buf = &rbuf;
  192. ret = i2c_transfer(cl->adapter, msg, 2);
  193. if (ret < 0)
  194. return ret;
  195. if (rbuf != 0x41)
  196. return -EIO;
  197. }
  198. /* frontend init */
  199. if (clk == PT1_FE_CLK_20MHZ) {
  200. if (is_sat) {
  201. cfg_data = va1j5jf8007s_20mhz_configs;
  202. len = ARRAY_SIZE(va1j5jf8007s_20mhz_configs);
  203. } else {
  204. cfg_data = va1j5jf8007t_20mhz_configs;
  205. len = ARRAY_SIZE(va1j5jf8007t_20mhz_configs);
  206. }
  207. } else {
  208. if (is_sat) {
  209. cfg_data = va1j5jf8007s_25mhz_configs;
  210. len = ARRAY_SIZE(va1j5jf8007s_25mhz_configs);
  211. } else {
  212. cfg_data = va1j5jf8007t_25mhz_configs;
  213. len = ARRAY_SIZE(va1j5jf8007t_25mhz_configs);
  214. }
  215. }
  216. for (i = 0; i < len; i++) {
  217. ret = i2c_master_send(cl, cfg_data[i], 2);
  218. if (ret < 0)
  219. return ret;
  220. }
  221. return 0;
  222. }
  223. /*
  224. * Init registers for (each pair of) terrestrial/satellite block in demod.
  225. * Note that resetting terr. block also resets its peer sat. block as well.
  226. * This function must be called before configuring any demod block
  227. * (before pt1_wakeup(), fe->ops.init()).
  228. */
  229. static int pt1_demod_block_init(struct pt1 *pt1)
  230. {
  231. struct i2c_client *cl;
  232. u8 buf[2] = {0x01, 0x80};
  233. int ret;
  234. int i;
  235. /* reset all terr. & sat. pairs first */
  236. for (i = 0; i < PT1_NR_ADAPS; i++) {
  237. cl = pt1->adaps[i]->demod_i2c_client;
  238. if (strncmp(cl->name, TC90522_I2C_DEV_TER,
  239. strlen(TC90522_I2C_DEV_TER)))
  240. continue;
  241. ret = i2c_master_send(cl, buf, 2);
  242. if (ret < 0)
  243. return ret;
  244. usleep_range(30000, 50000);
  245. }
  246. for (i = 0; i < PT1_NR_ADAPS; i++) {
  247. cl = pt1->adaps[i]->demod_i2c_client;
  248. if (strncmp(cl->name, TC90522_I2C_DEV_SAT,
  249. strlen(TC90522_I2C_DEV_SAT)))
  250. continue;
  251. ret = i2c_master_send(cl, buf, 2);
  252. if (ret < 0)
  253. return ret;
  254. usleep_range(30000, 50000);
  255. }
  256. return 0;
  257. }
  258. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  259. {
  260. writel(data, pt1->regs + reg * 4);
  261. }
  262. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  263. {
  264. return readl(pt1->regs + reg * 4);
  265. }
  266. static unsigned int pt1_nr_tables = 8;
  267. module_param_named(nr_tables, pt1_nr_tables, uint, 0);
  268. static void pt1_increment_table_count(struct pt1 *pt1)
  269. {
  270. pt1_write_reg(pt1, 0, 0x00000020);
  271. }
  272. static void pt1_init_table_count(struct pt1 *pt1)
  273. {
  274. pt1_write_reg(pt1, 0, 0x00000010);
  275. }
  276. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  277. {
  278. pt1_write_reg(pt1, 5, first_pfn);
  279. pt1_write_reg(pt1, 0, 0x0c000040);
  280. }
  281. static void pt1_unregister_tables(struct pt1 *pt1)
  282. {
  283. pt1_write_reg(pt1, 0, 0x08080000);
  284. }
  285. static int pt1_sync(struct pt1 *pt1)
  286. {
  287. int i;
  288. for (i = 0; i < 57; i++) {
  289. if (pt1_read_reg(pt1, 0) & 0x20000000)
  290. return 0;
  291. pt1_write_reg(pt1, 0, 0x00000008);
  292. }
  293. dev_err(&pt1->pdev->dev, "could not sync\n");
  294. return -EIO;
  295. }
  296. static u64 pt1_identify(struct pt1 *pt1)
  297. {
  298. int i;
  299. u64 id;
  300. id = 0;
  301. for (i = 0; i < 57; i++) {
  302. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  303. pt1_write_reg(pt1, 0, 0x00000008);
  304. }
  305. return id;
  306. }
  307. static int pt1_unlock(struct pt1 *pt1)
  308. {
  309. int i;
  310. pt1_write_reg(pt1, 0, 0x00000008);
  311. for (i = 0; i < 3; i++) {
  312. if (pt1_read_reg(pt1, 0) & 0x80000000)
  313. return 0;
  314. usleep_range(1000, 2000);
  315. }
  316. dev_err(&pt1->pdev->dev, "could not unlock\n");
  317. return -EIO;
  318. }
  319. static int pt1_reset_pci(struct pt1 *pt1)
  320. {
  321. int i;
  322. pt1_write_reg(pt1, 0, 0x01010000);
  323. pt1_write_reg(pt1, 0, 0x01000000);
  324. for (i = 0; i < 10; i++) {
  325. if (pt1_read_reg(pt1, 0) & 0x00000001)
  326. return 0;
  327. usleep_range(1000, 2000);
  328. }
  329. dev_err(&pt1->pdev->dev, "could not reset PCI\n");
  330. return -EIO;
  331. }
  332. static int pt1_reset_ram(struct pt1 *pt1)
  333. {
  334. int i;
  335. pt1_write_reg(pt1, 0, 0x02020000);
  336. pt1_write_reg(pt1, 0, 0x02000000);
  337. for (i = 0; i < 10; i++) {
  338. if (pt1_read_reg(pt1, 0) & 0x00000002)
  339. return 0;
  340. usleep_range(1000, 2000);
  341. }
  342. dev_err(&pt1->pdev->dev, "could not reset RAM\n");
  343. return -EIO;
  344. }
  345. static int pt1_do_enable_ram(struct pt1 *pt1)
  346. {
  347. int i, j;
  348. u32 status;
  349. status = pt1_read_reg(pt1, 0) & 0x00000004;
  350. pt1_write_reg(pt1, 0, 0x00000002);
  351. for (i = 0; i < 10; i++) {
  352. for (j = 0; j < 1024; j++) {
  353. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  354. return 0;
  355. }
  356. usleep_range(1000, 2000);
  357. }
  358. dev_err(&pt1->pdev->dev, "could not enable RAM\n");
  359. return -EIO;
  360. }
  361. static int pt1_enable_ram(struct pt1 *pt1)
  362. {
  363. int i, ret;
  364. int phase;
  365. usleep_range(1000, 2000);
  366. phase = pt1->pdev->device == 0x211a ? 128 : 166;
  367. for (i = 0; i < phase; i++) {
  368. ret = pt1_do_enable_ram(pt1);
  369. if (ret < 0)
  370. return ret;
  371. }
  372. return 0;
  373. }
  374. static void pt1_disable_ram(struct pt1 *pt1)
  375. {
  376. pt1_write_reg(pt1, 0, 0x0b0b0000);
  377. }
  378. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  379. {
  380. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  381. }
  382. static void pt1_init_streams(struct pt1 *pt1)
  383. {
  384. int i;
  385. for (i = 0; i < PT1_NR_ADAPS; i++)
  386. pt1_set_stream(pt1, i, 0);
  387. }
  388. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  389. {
  390. u32 upacket;
  391. int i;
  392. int index;
  393. struct pt1_adapter *adap;
  394. int offset;
  395. u8 *buf;
  396. int sc;
  397. if (!page->upackets[PT1_NR_UPACKETS - 1])
  398. return 0;
  399. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  400. upacket = le32_to_cpu(page->upackets[i]);
  401. index = (upacket >> 29) - 1;
  402. if (index < 0 || index >= PT1_NR_ADAPS)
  403. continue;
  404. adap = pt1->adaps[index];
  405. if (upacket >> 25 & 1)
  406. adap->upacket_count = 0;
  407. else if (!adap->upacket_count)
  408. continue;
  409. if (upacket >> 24 & 1)
  410. printk_ratelimited(KERN_INFO "earth-pt1: device buffer overflowing. table[%d] buf[%d]\n",
  411. pt1->table_index, pt1->buf_index);
  412. sc = upacket >> 26 & 0x7;
  413. if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7))
  414. printk_ratelimited(KERN_INFO "earth-pt1: data loss in streamID(adapter)[%d]\n",
  415. index);
  416. adap->st_count = sc;
  417. buf = adap->buf;
  418. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  419. buf[offset] = upacket >> 16;
  420. buf[offset + 1] = upacket >> 8;
  421. if (adap->upacket_count != 62)
  422. buf[offset + 2] = upacket;
  423. if (++adap->upacket_count >= 63) {
  424. adap->upacket_count = 0;
  425. if (++adap->packet_count >= 21) {
  426. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  427. adap->packet_count = 0;
  428. }
  429. }
  430. }
  431. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  432. return 1;
  433. }
  434. static int pt1_thread(void *data)
  435. {
  436. struct pt1 *pt1;
  437. struct pt1_buffer_page *page;
  438. bool was_frozen;
  439. #define PT1_FETCH_DELAY 10
  440. #define PT1_FETCH_DELAY_DELTA 2
  441. pt1 = data;
  442. set_freezable();
  443. while (!kthread_freezable_should_stop(&was_frozen)) {
  444. if (was_frozen) {
  445. int i;
  446. for (i = 0; i < PT1_NR_ADAPS; i++)
  447. pt1_set_stream(pt1, i, !!pt1->adaps[i]->users);
  448. }
  449. page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page;
  450. if (!pt1_filter(pt1, page)) {
  451. ktime_t delay;
  452. delay = ktime_set(0, PT1_FETCH_DELAY * NSEC_PER_MSEC);
  453. set_current_state(TASK_INTERRUPTIBLE);
  454. schedule_hrtimeout_range(&delay,
  455. PT1_FETCH_DELAY_DELTA * NSEC_PER_MSEC,
  456. HRTIMER_MODE_REL);
  457. continue;
  458. }
  459. if (++pt1->buf_index >= PT1_NR_BUFS) {
  460. pt1_increment_table_count(pt1);
  461. pt1->buf_index = 0;
  462. if (++pt1->table_index >= pt1_nr_tables)
  463. pt1->table_index = 0;
  464. }
  465. }
  466. return 0;
  467. }
  468. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  469. {
  470. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  471. }
  472. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  473. {
  474. void *page;
  475. dma_addr_t addr;
  476. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  477. GFP_KERNEL);
  478. if (page == NULL)
  479. return NULL;
  480. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  481. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  482. *addrp = addr;
  483. *pfnp = addr >> PT1_PAGE_SHIFT;
  484. return page;
  485. }
  486. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  487. {
  488. pt1_free_page(pt1, buf->page, buf->addr);
  489. }
  490. static int
  491. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  492. {
  493. struct pt1_buffer_page *page;
  494. dma_addr_t addr;
  495. page = pt1_alloc_page(pt1, &addr, pfnp);
  496. if (page == NULL)
  497. return -ENOMEM;
  498. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  499. buf->page = page;
  500. buf->addr = addr;
  501. return 0;
  502. }
  503. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  504. {
  505. int i;
  506. for (i = 0; i < PT1_NR_BUFS; i++)
  507. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  508. pt1_free_page(pt1, table->page, table->addr);
  509. }
  510. static int
  511. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  512. {
  513. struct pt1_table_page *page;
  514. dma_addr_t addr;
  515. int i, ret;
  516. u32 buf_pfn;
  517. page = pt1_alloc_page(pt1, &addr, pfnp);
  518. if (page == NULL)
  519. return -ENOMEM;
  520. for (i = 0; i < PT1_NR_BUFS; i++) {
  521. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  522. if (ret < 0)
  523. goto err;
  524. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  525. }
  526. pt1_increment_table_count(pt1);
  527. table->page = page;
  528. table->addr = addr;
  529. return 0;
  530. err:
  531. while (i--)
  532. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  533. pt1_free_page(pt1, page, addr);
  534. return ret;
  535. }
  536. static void pt1_cleanup_tables(struct pt1 *pt1)
  537. {
  538. struct pt1_table *tables;
  539. int i;
  540. tables = pt1->tables;
  541. pt1_unregister_tables(pt1);
  542. for (i = 0; i < pt1_nr_tables; i++)
  543. pt1_cleanup_table(pt1, &tables[i]);
  544. vfree(tables);
  545. }
  546. static int pt1_init_tables(struct pt1 *pt1)
  547. {
  548. struct pt1_table *tables;
  549. int i, ret;
  550. u32 first_pfn, pfn;
  551. if (!pt1_nr_tables)
  552. return 0;
  553. tables = vmalloc(array_size(pt1_nr_tables, sizeof(struct pt1_table)));
  554. if (tables == NULL)
  555. return -ENOMEM;
  556. pt1_init_table_count(pt1);
  557. i = 0;
  558. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  559. if (ret)
  560. goto err;
  561. i++;
  562. while (i < pt1_nr_tables) {
  563. ret = pt1_init_table(pt1, &tables[i], &pfn);
  564. if (ret)
  565. goto err;
  566. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  567. i++;
  568. }
  569. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  570. pt1_register_tables(pt1, first_pfn);
  571. pt1->tables = tables;
  572. return 0;
  573. err:
  574. while (i--)
  575. pt1_cleanup_table(pt1, &tables[i]);
  576. vfree(tables);
  577. return ret;
  578. }
  579. static int pt1_start_polling(struct pt1 *pt1)
  580. {
  581. int ret = 0;
  582. mutex_lock(&pt1->lock);
  583. if (!pt1->kthread) {
  584. pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1");
  585. if (IS_ERR(pt1->kthread)) {
  586. ret = PTR_ERR(pt1->kthread);
  587. pt1->kthread = NULL;
  588. }
  589. }
  590. mutex_unlock(&pt1->lock);
  591. return ret;
  592. }
  593. static int pt1_start_feed(struct dvb_demux_feed *feed)
  594. {
  595. struct pt1_adapter *adap;
  596. adap = container_of(feed->demux, struct pt1_adapter, demux);
  597. if (!adap->users++) {
  598. int ret;
  599. ret = pt1_start_polling(adap->pt1);
  600. if (ret)
  601. return ret;
  602. pt1_set_stream(adap->pt1, adap->index, 1);
  603. }
  604. return 0;
  605. }
  606. static void pt1_stop_polling(struct pt1 *pt1)
  607. {
  608. int i, count;
  609. mutex_lock(&pt1->lock);
  610. for (i = 0, count = 0; i < PT1_NR_ADAPS; i++)
  611. count += pt1->adaps[i]->users;
  612. if (count == 0 && pt1->kthread) {
  613. kthread_stop(pt1->kthread);
  614. pt1->kthread = NULL;
  615. }
  616. mutex_unlock(&pt1->lock);
  617. }
  618. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  619. {
  620. struct pt1_adapter *adap;
  621. adap = container_of(feed->demux, struct pt1_adapter, demux);
  622. if (!--adap->users) {
  623. pt1_set_stream(adap->pt1, adap->index, 0);
  624. pt1_stop_polling(adap->pt1);
  625. }
  626. return 0;
  627. }
  628. static void
  629. pt1_update_power(struct pt1 *pt1)
  630. {
  631. int bits;
  632. int i;
  633. struct pt1_adapter *adap;
  634. static const int sleep_bits[] = {
  635. 1 << 4,
  636. 1 << 6 | 1 << 7,
  637. 1 << 5,
  638. 1 << 6 | 1 << 8,
  639. };
  640. bits = pt1->power | !pt1->reset << 3;
  641. mutex_lock(&pt1->lock);
  642. for (i = 0; i < PT1_NR_ADAPS; i++) {
  643. adap = pt1->adaps[i];
  644. switch (adap->voltage) {
  645. case SEC_VOLTAGE_13: /* actually 11V */
  646. bits |= 1 << 2;
  647. break;
  648. case SEC_VOLTAGE_18: /* actually 15V */
  649. bits |= 1 << 1 | 1 << 2;
  650. break;
  651. default:
  652. break;
  653. }
  654. /* XXX: The bits should be changed depending on adap->sleep. */
  655. bits |= sleep_bits[i];
  656. }
  657. pt1_write_reg(pt1, 1, bits);
  658. mutex_unlock(&pt1->lock);
  659. }
  660. static int pt1_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
  661. {
  662. struct pt1_adapter *adap;
  663. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  664. adap->voltage = voltage;
  665. pt1_update_power(adap->pt1);
  666. if (adap->orig_set_voltage)
  667. return adap->orig_set_voltage(fe, voltage);
  668. else
  669. return 0;
  670. }
  671. static int pt1_sleep(struct dvb_frontend *fe)
  672. {
  673. struct pt1_adapter *adap;
  674. int ret;
  675. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  676. ret = 0;
  677. if (adap->orig_sleep)
  678. ret = adap->orig_sleep(fe);
  679. adap->sleep = 1;
  680. pt1_update_power(adap->pt1);
  681. return ret;
  682. }
  683. static int pt1_wakeup(struct dvb_frontend *fe)
  684. {
  685. struct pt1_adapter *adap;
  686. int ret;
  687. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  688. adap->sleep = 0;
  689. pt1_update_power(adap->pt1);
  690. usleep_range(1000, 2000);
  691. ret = config_demod(adap->demod_i2c_client, adap->pt1->fe_clk);
  692. if (ret == 0 && adap->orig_init)
  693. ret = adap->orig_init(fe);
  694. return ret;
  695. }
  696. static void pt1_free_adapter(struct pt1_adapter *adap)
  697. {
  698. adap->demux.dmx.close(&adap->demux.dmx);
  699. dvb_dmxdev_release(&adap->dmxdev);
  700. dvb_dmx_release(&adap->demux);
  701. dvb_unregister_adapter(&adap->adap);
  702. free_page((unsigned long)adap->buf);
  703. kfree(adap);
  704. }
  705. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  706. static struct pt1_adapter *
  707. pt1_alloc_adapter(struct pt1 *pt1)
  708. {
  709. struct pt1_adapter *adap;
  710. void *buf;
  711. struct dvb_adapter *dvb_adap;
  712. struct dvb_demux *demux;
  713. struct dmxdev *dmxdev;
  714. int ret;
  715. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  716. if (!adap) {
  717. ret = -ENOMEM;
  718. goto err;
  719. }
  720. adap->pt1 = pt1;
  721. adap->voltage = SEC_VOLTAGE_OFF;
  722. adap->sleep = 1;
  723. buf = (u8 *)__get_free_page(GFP_KERNEL);
  724. if (!buf) {
  725. ret = -ENOMEM;
  726. goto err_kfree;
  727. }
  728. adap->buf = buf;
  729. adap->upacket_count = 0;
  730. adap->packet_count = 0;
  731. adap->st_count = -1;
  732. dvb_adap = &adap->adap;
  733. dvb_adap->priv = adap;
  734. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  735. &pt1->pdev->dev, adapter_nr);
  736. if (ret < 0)
  737. goto err_free_page;
  738. demux = &adap->demux;
  739. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  740. demux->priv = adap;
  741. demux->feednum = 256;
  742. demux->filternum = 256;
  743. demux->start_feed = pt1_start_feed;
  744. demux->stop_feed = pt1_stop_feed;
  745. demux->write_to_decoder = NULL;
  746. ret = dvb_dmx_init(demux);
  747. if (ret < 0)
  748. goto err_unregister_adapter;
  749. dmxdev = &adap->dmxdev;
  750. dmxdev->filternum = 256;
  751. dmxdev->demux = &demux->dmx;
  752. dmxdev->capabilities = 0;
  753. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  754. if (ret < 0)
  755. goto err_dmx_release;
  756. return adap;
  757. err_dmx_release:
  758. dvb_dmx_release(demux);
  759. err_unregister_adapter:
  760. dvb_unregister_adapter(dvb_adap);
  761. err_free_page:
  762. free_page((unsigned long)buf);
  763. err_kfree:
  764. kfree(adap);
  765. err:
  766. return ERR_PTR(ret);
  767. }
  768. static void pt1_cleanup_adapters(struct pt1 *pt1)
  769. {
  770. int i;
  771. for (i = 0; i < PT1_NR_ADAPS; i++)
  772. pt1_free_adapter(pt1->adaps[i]);
  773. }
  774. static int pt1_init_adapters(struct pt1 *pt1)
  775. {
  776. int i;
  777. struct pt1_adapter *adap;
  778. int ret;
  779. for (i = 0; i < PT1_NR_ADAPS; i++) {
  780. adap = pt1_alloc_adapter(pt1);
  781. if (IS_ERR(adap)) {
  782. ret = PTR_ERR(adap);
  783. goto err;
  784. }
  785. adap->index = i;
  786. pt1->adaps[i] = adap;
  787. }
  788. return 0;
  789. err:
  790. while (i--)
  791. pt1_free_adapter(pt1->adaps[i]);
  792. return ret;
  793. }
  794. static void pt1_cleanup_frontend(struct pt1_adapter *adap)
  795. {
  796. dvb_unregister_frontend(adap->fe);
  797. dvb_module_release(adap->tuner_i2c_client);
  798. dvb_module_release(adap->demod_i2c_client);
  799. }
  800. static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
  801. {
  802. int ret;
  803. adap->orig_set_voltage = fe->ops.set_voltage;
  804. adap->orig_sleep = fe->ops.sleep;
  805. adap->orig_init = fe->ops.init;
  806. fe->ops.set_voltage = pt1_set_voltage;
  807. fe->ops.sleep = pt1_sleep;
  808. fe->ops.init = pt1_wakeup;
  809. ret = dvb_register_frontend(&adap->adap, fe);
  810. if (ret < 0)
  811. return ret;
  812. adap->fe = fe;
  813. return 0;
  814. }
  815. static void pt1_cleanup_frontends(struct pt1 *pt1)
  816. {
  817. int i;
  818. for (i = 0; i < PT1_NR_ADAPS; i++)
  819. pt1_cleanup_frontend(pt1->adaps[i]);
  820. }
  821. static int pt1_init_frontends(struct pt1 *pt1)
  822. {
  823. int i;
  824. int ret;
  825. for (i = 0; i < ARRAY_SIZE(pt1_configs); i++) {
  826. const struct i2c_board_info *info;
  827. struct tc90522_config dcfg;
  828. struct i2c_client *cl;
  829. info = &pt1_configs[i].demod_info;
  830. dcfg = pt1_configs[i].demod_cfg;
  831. dcfg.tuner_i2c = NULL;
  832. ret = -ENODEV;
  833. cl = dvb_module_probe("tc90522", info->type, &pt1->i2c_adap,
  834. info->addr, &dcfg);
  835. if (!cl)
  836. goto fe_unregister;
  837. pt1->adaps[i]->demod_i2c_client = cl;
  838. if (!strncmp(cl->name, TC90522_I2C_DEV_SAT,
  839. strlen(TC90522_I2C_DEV_SAT))) {
  840. struct qm1d1b0004_config tcfg;
  841. info = &pt1_configs[i].tuner_info;
  842. tcfg = pt1_configs[i].tuner_cfg.qm1d1b0004;
  843. tcfg.fe = dcfg.fe;
  844. cl = dvb_module_probe("qm1d1b0004",
  845. info->type, dcfg.tuner_i2c,
  846. info->addr, &tcfg);
  847. } else {
  848. struct dvb_pll_config tcfg;
  849. info = &pt1_configs[i].tuner_info;
  850. tcfg = pt1_configs[i].tuner_cfg.tda6651;
  851. tcfg.fe = dcfg.fe;
  852. cl = dvb_module_probe("dvb_pll",
  853. info->type, dcfg.tuner_i2c,
  854. info->addr, &tcfg);
  855. }
  856. if (!cl)
  857. goto demod_release;
  858. pt1->adaps[i]->tuner_i2c_client = cl;
  859. ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe);
  860. if (ret < 0)
  861. goto tuner_release;
  862. }
  863. ret = pt1_demod_block_init(pt1);
  864. if (ret < 0)
  865. goto fe_unregister;
  866. return 0;
  867. tuner_release:
  868. dvb_module_release(pt1->adaps[i]->tuner_i2c_client);
  869. demod_release:
  870. dvb_module_release(pt1->adaps[i]->demod_i2c_client);
  871. fe_unregister:
  872. dev_warn(&pt1->pdev->dev, "failed to init FE(%d).\n", i);
  873. i--;
  874. for (; i >= 0; i--) {
  875. dvb_unregister_frontend(pt1->adaps[i]->fe);
  876. dvb_module_release(pt1->adaps[i]->tuner_i2c_client);
  877. dvb_module_release(pt1->adaps[i]->demod_i2c_client);
  878. }
  879. return ret;
  880. }
  881. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  882. int clock, int data, int next_addr)
  883. {
  884. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  885. !clock << 11 | !data << 10 | next_addr);
  886. }
  887. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  888. {
  889. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  890. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  891. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  892. *addrp = addr + 3;
  893. }
  894. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  895. {
  896. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  897. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  898. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  899. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  900. *addrp = addr + 4;
  901. }
  902. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  903. {
  904. int i;
  905. for (i = 0; i < 8; i++)
  906. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  907. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  908. *addrp = addr;
  909. }
  910. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  911. {
  912. int i;
  913. for (i = 0; i < 8; i++)
  914. pt1_i2c_read_bit(pt1, addr, &addr);
  915. pt1_i2c_write_bit(pt1, addr, &addr, last);
  916. *addrp = addr;
  917. }
  918. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  919. {
  920. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  921. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  922. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  923. *addrp = addr + 3;
  924. }
  925. static void
  926. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  927. {
  928. int i;
  929. pt1_i2c_prepare(pt1, addr, &addr);
  930. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  931. for (i = 0; i < msg->len; i++)
  932. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  933. *addrp = addr;
  934. }
  935. static void
  936. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  937. {
  938. int i;
  939. pt1_i2c_prepare(pt1, addr, &addr);
  940. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  941. for (i = 0; i < msg->len; i++)
  942. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  943. *addrp = addr;
  944. }
  945. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  946. {
  947. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  948. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  949. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  950. pt1_write_reg(pt1, 0, 0x00000004);
  951. do {
  952. if (signal_pending(current))
  953. return -EINTR;
  954. usleep_range(1000, 2000);
  955. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  956. return 0;
  957. }
  958. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  959. {
  960. int addr;
  961. addr = 0;
  962. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  963. addr = addr + 1;
  964. if (!pt1->i2c_running) {
  965. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  966. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  967. addr = addr + 2;
  968. pt1->i2c_running = 1;
  969. }
  970. *addrp = addr;
  971. }
  972. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  973. {
  974. struct pt1 *pt1;
  975. int i;
  976. struct i2c_msg *msg, *next_msg;
  977. int addr, ret;
  978. u16 len;
  979. u32 word;
  980. pt1 = i2c_get_adapdata(adap);
  981. for (i = 0; i < num; i++) {
  982. msg = &msgs[i];
  983. if (msg->flags & I2C_M_RD)
  984. return -ENOTSUPP;
  985. if (i + 1 < num)
  986. next_msg = &msgs[i + 1];
  987. else
  988. next_msg = NULL;
  989. if (next_msg && next_msg->flags & I2C_M_RD) {
  990. i++;
  991. len = next_msg->len;
  992. if (len > 4)
  993. return -ENOTSUPP;
  994. pt1_i2c_begin(pt1, &addr);
  995. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  996. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  997. ret = pt1_i2c_end(pt1, addr);
  998. if (ret < 0)
  999. return ret;
  1000. word = pt1_read_reg(pt1, 2);
  1001. while (len--) {
  1002. next_msg->buf[len] = word;
  1003. word >>= 8;
  1004. }
  1005. } else {
  1006. pt1_i2c_begin(pt1, &addr);
  1007. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  1008. ret = pt1_i2c_end(pt1, addr);
  1009. if (ret < 0)
  1010. return ret;
  1011. }
  1012. }
  1013. return num;
  1014. }
  1015. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  1016. {
  1017. return I2C_FUNC_I2C;
  1018. }
  1019. static const struct i2c_algorithm pt1_i2c_algo = {
  1020. .master_xfer = pt1_i2c_xfer,
  1021. .functionality = pt1_i2c_func,
  1022. };
  1023. static void pt1_i2c_wait(struct pt1 *pt1)
  1024. {
  1025. int i;
  1026. for (i = 0; i < 128; i++)
  1027. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  1028. }
  1029. static void pt1_i2c_init(struct pt1 *pt1)
  1030. {
  1031. int i;
  1032. for (i = 0; i < 1024; i++)
  1033. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  1034. }
  1035. #ifdef CONFIG_PM_SLEEP
  1036. static int pt1_suspend(struct device *dev)
  1037. {
  1038. struct pci_dev *pdev = to_pci_dev(dev);
  1039. struct pt1 *pt1 = pci_get_drvdata(pdev);
  1040. pt1_init_streams(pt1);
  1041. pt1_disable_ram(pt1);
  1042. pt1->power = 0;
  1043. pt1->reset = 1;
  1044. pt1_update_power(pt1);
  1045. return 0;
  1046. }
  1047. static int pt1_resume(struct device *dev)
  1048. {
  1049. struct pci_dev *pdev = to_pci_dev(dev);
  1050. struct pt1 *pt1 = pci_get_drvdata(pdev);
  1051. int ret;
  1052. int i;
  1053. pt1->power = 0;
  1054. pt1->reset = 1;
  1055. pt1_update_power(pt1);
  1056. pt1_i2c_init(pt1);
  1057. pt1_i2c_wait(pt1);
  1058. ret = pt1_sync(pt1);
  1059. if (ret < 0)
  1060. goto resume_err;
  1061. pt1_identify(pt1);
  1062. ret = pt1_unlock(pt1);
  1063. if (ret < 0)
  1064. goto resume_err;
  1065. ret = pt1_reset_pci(pt1);
  1066. if (ret < 0)
  1067. goto resume_err;
  1068. ret = pt1_reset_ram(pt1);
  1069. if (ret < 0)
  1070. goto resume_err;
  1071. ret = pt1_enable_ram(pt1);
  1072. if (ret < 0)
  1073. goto resume_err;
  1074. pt1_init_streams(pt1);
  1075. pt1->power = 1;
  1076. pt1_update_power(pt1);
  1077. msleep(20);
  1078. pt1->reset = 0;
  1079. pt1_update_power(pt1);
  1080. usleep_range(1000, 2000);
  1081. ret = pt1_demod_block_init(pt1);
  1082. if (ret < 0)
  1083. goto resume_err;
  1084. for (i = 0; i < PT1_NR_ADAPS; i++)
  1085. dvb_frontend_reinitialise(pt1->adaps[i]->fe);
  1086. pt1_init_table_count(pt1);
  1087. for (i = 0; i < pt1_nr_tables; i++) {
  1088. int j;
  1089. for (j = 0; j < PT1_NR_BUFS; j++)
  1090. pt1->tables[i].bufs[j].page->upackets[PT1_NR_UPACKETS-1]
  1091. = 0;
  1092. pt1_increment_table_count(pt1);
  1093. }
  1094. pt1_register_tables(pt1, pt1->tables[0].addr >> PT1_PAGE_SHIFT);
  1095. pt1->table_index = 0;
  1096. pt1->buf_index = 0;
  1097. for (i = 0; i < PT1_NR_ADAPS; i++) {
  1098. pt1->adaps[i]->upacket_count = 0;
  1099. pt1->adaps[i]->packet_count = 0;
  1100. pt1->adaps[i]->st_count = -1;
  1101. }
  1102. return 0;
  1103. resume_err:
  1104. dev_info(&pt1->pdev->dev, "failed to resume PT1/PT2.");
  1105. return 0; /* resume anyway */
  1106. }
  1107. #endif /* CONFIG_PM_SLEEP */
  1108. static void pt1_remove(struct pci_dev *pdev)
  1109. {
  1110. struct pt1 *pt1;
  1111. void __iomem *regs;
  1112. pt1 = pci_get_drvdata(pdev);
  1113. regs = pt1->regs;
  1114. if (pt1->kthread)
  1115. kthread_stop(pt1->kthread);
  1116. pt1_cleanup_tables(pt1);
  1117. pt1_cleanup_frontends(pt1);
  1118. pt1_disable_ram(pt1);
  1119. pt1->power = 0;
  1120. pt1->reset = 1;
  1121. pt1_update_power(pt1);
  1122. pt1_cleanup_adapters(pt1);
  1123. i2c_del_adapter(&pt1->i2c_adap);
  1124. kfree(pt1);
  1125. pci_iounmap(pdev, regs);
  1126. pci_release_regions(pdev);
  1127. pci_disable_device(pdev);
  1128. }
  1129. static int pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1130. {
  1131. int ret;
  1132. void __iomem *regs;
  1133. struct pt1 *pt1;
  1134. struct i2c_adapter *i2c_adap;
  1135. ret = pci_enable_device(pdev);
  1136. if (ret < 0)
  1137. goto err;
  1138. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1139. if (ret < 0)
  1140. goto err_pci_disable_device;
  1141. pci_set_master(pdev);
  1142. ret = pci_request_regions(pdev, DRIVER_NAME);
  1143. if (ret < 0)
  1144. goto err_pci_disable_device;
  1145. regs = pci_iomap(pdev, 0, 0);
  1146. if (!regs) {
  1147. ret = -EIO;
  1148. goto err_pci_release_regions;
  1149. }
  1150. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  1151. if (!pt1) {
  1152. ret = -ENOMEM;
  1153. goto err_pci_iounmap;
  1154. }
  1155. mutex_init(&pt1->lock);
  1156. pt1->pdev = pdev;
  1157. pt1->regs = regs;
  1158. pt1->fe_clk = (pdev->device == 0x211a) ?
  1159. PT1_FE_CLK_20MHZ : PT1_FE_CLK_25MHZ;
  1160. pci_set_drvdata(pdev, pt1);
  1161. ret = pt1_init_adapters(pt1);
  1162. if (ret < 0)
  1163. goto err_kfree;
  1164. mutex_init(&pt1->lock);
  1165. pt1->power = 0;
  1166. pt1->reset = 1;
  1167. pt1_update_power(pt1);
  1168. i2c_adap = &pt1->i2c_adap;
  1169. i2c_adap->algo = &pt1_i2c_algo;
  1170. i2c_adap->algo_data = NULL;
  1171. i2c_adap->dev.parent = &pdev->dev;
  1172. strcpy(i2c_adap->name, DRIVER_NAME);
  1173. i2c_set_adapdata(i2c_adap, pt1);
  1174. ret = i2c_add_adapter(i2c_adap);
  1175. if (ret < 0)
  1176. goto err_pt1_cleanup_adapters;
  1177. pt1_i2c_init(pt1);
  1178. pt1_i2c_wait(pt1);
  1179. ret = pt1_sync(pt1);
  1180. if (ret < 0)
  1181. goto err_i2c_del_adapter;
  1182. pt1_identify(pt1);
  1183. ret = pt1_unlock(pt1);
  1184. if (ret < 0)
  1185. goto err_i2c_del_adapter;
  1186. ret = pt1_reset_pci(pt1);
  1187. if (ret < 0)
  1188. goto err_i2c_del_adapter;
  1189. ret = pt1_reset_ram(pt1);
  1190. if (ret < 0)
  1191. goto err_i2c_del_adapter;
  1192. ret = pt1_enable_ram(pt1);
  1193. if (ret < 0)
  1194. goto err_i2c_del_adapter;
  1195. pt1_init_streams(pt1);
  1196. pt1->power = 1;
  1197. pt1_update_power(pt1);
  1198. msleep(20);
  1199. pt1->reset = 0;
  1200. pt1_update_power(pt1);
  1201. usleep_range(1000, 2000);
  1202. ret = pt1_init_frontends(pt1);
  1203. if (ret < 0)
  1204. goto err_pt1_disable_ram;
  1205. ret = pt1_init_tables(pt1);
  1206. if (ret < 0)
  1207. goto err_pt1_cleanup_frontends;
  1208. return 0;
  1209. err_pt1_cleanup_frontends:
  1210. pt1_cleanup_frontends(pt1);
  1211. err_pt1_disable_ram:
  1212. pt1_disable_ram(pt1);
  1213. pt1->power = 0;
  1214. pt1->reset = 1;
  1215. pt1_update_power(pt1);
  1216. err_i2c_del_adapter:
  1217. i2c_del_adapter(i2c_adap);
  1218. err_pt1_cleanup_adapters:
  1219. pt1_cleanup_adapters(pt1);
  1220. err_kfree:
  1221. kfree(pt1);
  1222. err_pci_iounmap:
  1223. pci_iounmap(pdev, regs);
  1224. err_pci_release_regions:
  1225. pci_release_regions(pdev);
  1226. err_pci_disable_device:
  1227. pci_disable_device(pdev);
  1228. err:
  1229. return ret;
  1230. }
  1231. static const struct pci_device_id pt1_id_table[] = {
  1232. { PCI_DEVICE(0x10ee, 0x211a) },
  1233. { PCI_DEVICE(0x10ee, 0x222a) },
  1234. { },
  1235. };
  1236. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  1237. static SIMPLE_DEV_PM_OPS(pt1_pm_ops, pt1_suspend, pt1_resume);
  1238. static struct pci_driver pt1_driver = {
  1239. .name = DRIVER_NAME,
  1240. .probe = pt1_probe,
  1241. .remove = pt1_remove,
  1242. .id_table = pt1_id_table,
  1243. .driver.pm = &pt1_pm_ops,
  1244. };
  1245. module_pci_driver(pt1_driver);
  1246. MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
  1247. MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
  1248. MODULE_LICENSE("GPL");