cx88-dvb.c 48 KB

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  1. /*
  2. * device driver for Conexant 2388x based TV cards
  3. * MPEG Transport Stream (DVB) routines
  4. *
  5. * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
  6. * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include "cx88.h"
  19. #include "dvb-pll.h"
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/device.h>
  23. #include <linux/fs.h>
  24. #include <linux/kthread.h>
  25. #include <linux/file.h>
  26. #include <linux/suspend.h>
  27. #include <media/v4l2-common.h>
  28. #include "mt352.h"
  29. #include "mt352_priv.h"
  30. #include "cx88-vp3054-i2c.h"
  31. #include "zl10353.h"
  32. #include "cx22702.h"
  33. #include "or51132.h"
  34. #include "lgdt330x.h"
  35. #include "s5h1409.h"
  36. #include "xc4000.h"
  37. #include "xc5000.h"
  38. #include "nxt200x.h"
  39. #include "cx24123.h"
  40. #include "isl6421.h"
  41. #include "tuner-simple.h"
  42. #include "tda9887.h"
  43. #include "s5h1411.h"
  44. #include "stv0299.h"
  45. #include "z0194a.h"
  46. #include "stv0288.h"
  47. #include "stb6000.h"
  48. #include "cx24116.h"
  49. #include "stv0900.h"
  50. #include "stb6100.h"
  51. #include "stb6100_proc.h"
  52. #include "mb86a16.h"
  53. #include "ts2020.h"
  54. #include "ds3000.h"
  55. MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
  56. MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  57. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  58. MODULE_LICENSE("GPL");
  59. MODULE_VERSION(CX88_VERSION);
  60. static unsigned int debug;
  61. module_param(debug, int, 0644);
  62. MODULE_PARM_DESC(debug, "enable debug messages [dvb]");
  63. static unsigned int dvb_buf_tscnt = 32;
  64. module_param(dvb_buf_tscnt, int, 0644);
  65. MODULE_PARM_DESC(dvb_buf_tscnt, "DVB Buffer TS count [dvb]");
  66. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  67. #define dprintk(level, fmt, arg...) do { \
  68. if (debug >= level) \
  69. printk(KERN_DEBUG pr_fmt("%s: dvb:" fmt), \
  70. __func__, ##arg); \
  71. } while (0)
  72. /* ------------------------------------------------------------------ */
  73. static int queue_setup(struct vb2_queue *q,
  74. unsigned int *num_buffers, unsigned int *num_planes,
  75. unsigned int sizes[], struct device *alloc_devs[])
  76. {
  77. struct cx8802_dev *dev = q->drv_priv;
  78. *num_planes = 1;
  79. dev->ts_packet_size = 188 * 4;
  80. dev->ts_packet_count = dvb_buf_tscnt;
  81. sizes[0] = dev->ts_packet_size * dev->ts_packet_count;
  82. *num_buffers = dvb_buf_tscnt;
  83. return 0;
  84. }
  85. static int buffer_prepare(struct vb2_buffer *vb)
  86. {
  87. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  88. struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
  89. struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
  90. return cx8802_buf_prepare(vb->vb2_queue, dev, buf);
  91. }
  92. static void buffer_finish(struct vb2_buffer *vb)
  93. {
  94. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  95. struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
  96. struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
  97. struct cx88_riscmem *risc = &buf->risc;
  98. if (risc->cpu)
  99. pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
  100. memset(risc, 0, sizeof(*risc));
  101. }
  102. static void buffer_queue(struct vb2_buffer *vb)
  103. {
  104. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  105. struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
  106. struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
  107. cx8802_buf_queue(dev, buf);
  108. }
  109. static int start_streaming(struct vb2_queue *q, unsigned int count)
  110. {
  111. struct cx8802_dev *dev = q->drv_priv;
  112. struct cx88_dmaqueue *dmaq = &dev->mpegq;
  113. struct cx88_buffer *buf;
  114. buf = list_entry(dmaq->active.next, struct cx88_buffer, list);
  115. cx8802_start_dma(dev, dmaq, buf);
  116. return 0;
  117. }
  118. static void stop_streaming(struct vb2_queue *q)
  119. {
  120. struct cx8802_dev *dev = q->drv_priv;
  121. struct cx88_dmaqueue *dmaq = &dev->mpegq;
  122. unsigned long flags;
  123. cx8802_cancel_buffers(dev);
  124. spin_lock_irqsave(&dev->slock, flags);
  125. while (!list_empty(&dmaq->active)) {
  126. struct cx88_buffer *buf = list_entry(dmaq->active.next,
  127. struct cx88_buffer, list);
  128. list_del(&buf->list);
  129. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  130. }
  131. spin_unlock_irqrestore(&dev->slock, flags);
  132. }
  133. static const struct vb2_ops dvb_qops = {
  134. .queue_setup = queue_setup,
  135. .buf_prepare = buffer_prepare,
  136. .buf_finish = buffer_finish,
  137. .buf_queue = buffer_queue,
  138. .wait_prepare = vb2_ops_wait_prepare,
  139. .wait_finish = vb2_ops_wait_finish,
  140. .start_streaming = start_streaming,
  141. .stop_streaming = stop_streaming,
  142. };
  143. /* ------------------------------------------------------------------ */
  144. static int cx88_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
  145. {
  146. struct cx8802_dev *dev = fe->dvb->priv;
  147. struct cx8802_driver *drv = NULL;
  148. int ret = 0;
  149. int fe_id;
  150. fe_id = vb2_dvb_find_frontend(&dev->frontends, fe);
  151. if (!fe_id) {
  152. pr_err("%s() No frontend found\n", __func__);
  153. return -EINVAL;
  154. }
  155. mutex_lock(&dev->core->lock);
  156. drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
  157. if (drv) {
  158. if (acquire) {
  159. dev->frontends.active_fe_id = fe_id;
  160. ret = drv->request_acquire(drv);
  161. } else {
  162. ret = drv->request_release(drv);
  163. dev->frontends.active_fe_id = 0;
  164. }
  165. }
  166. mutex_unlock(&dev->core->lock);
  167. return ret;
  168. }
  169. static void cx88_dvb_gate_ctrl(struct cx88_core *core, int open)
  170. {
  171. struct vb2_dvb_frontends *f;
  172. struct vb2_dvb_frontend *fe;
  173. if (!core->dvbdev)
  174. return;
  175. f = &core->dvbdev->frontends;
  176. if (!f)
  177. return;
  178. if (f->gate <= 1) /* undefined or fe0 */
  179. fe = vb2_dvb_get_frontend(f, 1);
  180. else
  181. fe = vb2_dvb_get_frontend(f, f->gate);
  182. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  183. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  184. }
  185. /* ------------------------------------------------------------------ */
  186. static int dvico_fusionhdtv_demod_init(struct dvb_frontend *fe)
  187. {
  188. static const u8 clock_config[] = { CLOCK_CTL, 0x38, 0x39 };
  189. static const u8 reset[] = { RESET, 0x80 };
  190. static const u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
  191. static const u8 agc_cfg[] = { AGC_TARGET, 0x24, 0x20 };
  192. static const u8 gpp_ctl_cfg[] = { GPP_CTL, 0x33 };
  193. static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  194. mt352_write(fe, clock_config, sizeof(clock_config));
  195. udelay(200);
  196. mt352_write(fe, reset, sizeof(reset));
  197. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  198. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  199. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  200. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  201. return 0;
  202. }
  203. static int dvico_dual_demod_init(struct dvb_frontend *fe)
  204. {
  205. static const u8 clock_config[] = { CLOCK_CTL, 0x38, 0x38 };
  206. static const u8 reset[] = { RESET, 0x80 };
  207. static const u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
  208. static const u8 agc_cfg[] = { AGC_TARGET, 0x28, 0x20 };
  209. static const u8 gpp_ctl_cfg[] = { GPP_CTL, 0x33 };
  210. static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  211. mt352_write(fe, clock_config, sizeof(clock_config));
  212. udelay(200);
  213. mt352_write(fe, reset, sizeof(reset));
  214. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  215. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  216. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  217. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  218. return 0;
  219. }
  220. static int dntv_live_dvbt_demod_init(struct dvb_frontend *fe)
  221. {
  222. static const u8 clock_config[] = { 0x89, 0x38, 0x39 };
  223. static const u8 reset[] = { 0x50, 0x80 };
  224. static const u8 adc_ctl_1_cfg[] = { 0x8E, 0x40 };
  225. static const u8 agc_cfg[] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
  226. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  227. static const u8 dntv_extra[] = { 0xB5, 0x7A };
  228. static const u8 capt_range_cfg[] = { 0x75, 0x32 };
  229. mt352_write(fe, clock_config, sizeof(clock_config));
  230. udelay(2000);
  231. mt352_write(fe, reset, sizeof(reset));
  232. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  233. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  234. udelay(2000);
  235. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  236. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  237. return 0;
  238. }
  239. static const struct mt352_config dvico_fusionhdtv = {
  240. .demod_address = 0x0f,
  241. .demod_init = dvico_fusionhdtv_demod_init,
  242. };
  243. static const struct mt352_config dntv_live_dvbt_config = {
  244. .demod_address = 0x0f,
  245. .demod_init = dntv_live_dvbt_demod_init,
  246. };
  247. static const struct mt352_config dvico_fusionhdtv_dual = {
  248. .demod_address = 0x0f,
  249. .demod_init = dvico_dual_demod_init,
  250. };
  251. static const struct zl10353_config cx88_terratec_cinergy_ht_pci_mkii_config = {
  252. .demod_address = (0x1e >> 1),
  253. .no_tuner = 1,
  254. .if2 = 45600,
  255. };
  256. static const struct mb86a16_config twinhan_vp1027 = {
  257. .demod_address = 0x08,
  258. };
  259. #if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054)
  260. static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend *fe)
  261. {
  262. static const u8 clock_config[] = { 0x89, 0x38, 0x38 };
  263. static const u8 reset[] = { 0x50, 0x80 };
  264. static const u8 adc_ctl_1_cfg[] = { 0x8E, 0x40 };
  265. static const u8 agc_cfg[] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
  266. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  267. static const u8 dntv_extra[] = { 0xB5, 0x7A };
  268. static const u8 capt_range_cfg[] = { 0x75, 0x32 };
  269. mt352_write(fe, clock_config, sizeof(clock_config));
  270. udelay(2000);
  271. mt352_write(fe, reset, sizeof(reset));
  272. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  273. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  274. udelay(2000);
  275. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  276. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  277. return 0;
  278. }
  279. static const struct mt352_config dntv_live_dvbt_pro_config = {
  280. .demod_address = 0x0f,
  281. .no_tuner = 1,
  282. .demod_init = dntv_live_dvbt_pro_demod_init,
  283. };
  284. #endif
  285. static const struct zl10353_config dvico_fusionhdtv_hybrid = {
  286. .demod_address = 0x0f,
  287. .no_tuner = 1,
  288. };
  289. static const struct zl10353_config dvico_fusionhdtv_xc3028 = {
  290. .demod_address = 0x0f,
  291. .if2 = 45600,
  292. .no_tuner = 1,
  293. };
  294. static const struct mt352_config dvico_fusionhdtv_mt352_xc3028 = {
  295. .demod_address = 0x0f,
  296. .if2 = 4560,
  297. .no_tuner = 1,
  298. .demod_init = dvico_fusionhdtv_demod_init,
  299. };
  300. static const struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
  301. .demod_address = 0x0f,
  302. };
  303. static const struct cx22702_config connexant_refboard_config = {
  304. .demod_address = 0x43,
  305. .output_mode = CX22702_SERIAL_OUTPUT,
  306. };
  307. static const struct cx22702_config hauppauge_hvr_config = {
  308. .demod_address = 0x63,
  309. .output_mode = CX22702_SERIAL_OUTPUT,
  310. };
  311. static int or51132_set_ts_param(struct dvb_frontend *fe, int is_punctured)
  312. {
  313. struct cx8802_dev *dev = fe->dvb->priv;
  314. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  315. return 0;
  316. }
  317. static const struct or51132_config pchdtv_hd3000 = {
  318. .demod_address = 0x15,
  319. .set_ts_params = or51132_set_ts_param,
  320. };
  321. static int lgdt330x_pll_rf_set(struct dvb_frontend *fe, int index)
  322. {
  323. struct cx8802_dev *dev = fe->dvb->priv;
  324. struct cx88_core *core = dev->core;
  325. dprintk(1, "%s: index = %d\n", __func__, index);
  326. if (index == 0)
  327. cx_clear(MO_GP0_IO, 8);
  328. else
  329. cx_set(MO_GP0_IO, 8);
  330. return 0;
  331. }
  332. static int lgdt330x_set_ts_param(struct dvb_frontend *fe, int is_punctured)
  333. {
  334. struct cx8802_dev *dev = fe->dvb->priv;
  335. if (is_punctured)
  336. dev->ts_gen_cntrl |= 0x04;
  337. else
  338. dev->ts_gen_cntrl &= ~0x04;
  339. return 0;
  340. }
  341. static struct lgdt330x_config fusionhdtv_3_gold = {
  342. .demod_chip = LGDT3302,
  343. .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
  344. .set_ts_params = lgdt330x_set_ts_param,
  345. };
  346. static const struct lgdt330x_config fusionhdtv_5_gold = {
  347. .demod_chip = LGDT3303,
  348. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  349. .set_ts_params = lgdt330x_set_ts_param,
  350. };
  351. static const struct lgdt330x_config pchdtv_hd5500 = {
  352. .demod_chip = LGDT3303,
  353. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  354. .set_ts_params = lgdt330x_set_ts_param,
  355. };
  356. static int nxt200x_set_ts_param(struct dvb_frontend *fe, int is_punctured)
  357. {
  358. struct cx8802_dev *dev = fe->dvb->priv;
  359. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  360. return 0;
  361. }
  362. static const struct nxt200x_config ati_hdtvwonder = {
  363. .demod_address = 0x0a,
  364. .set_ts_params = nxt200x_set_ts_param,
  365. };
  366. static int cx24123_set_ts_param(struct dvb_frontend *fe,
  367. int is_punctured)
  368. {
  369. struct cx8802_dev *dev = fe->dvb->priv;
  370. dev->ts_gen_cntrl = 0x02;
  371. return 0;
  372. }
  373. static int kworld_dvbs_100_set_voltage(struct dvb_frontend *fe,
  374. enum fe_sec_voltage voltage)
  375. {
  376. struct cx8802_dev *dev = fe->dvb->priv;
  377. struct cx88_core *core = dev->core;
  378. if (voltage == SEC_VOLTAGE_OFF)
  379. cx_write(MO_GP0_IO, 0x000006fb);
  380. else
  381. cx_write(MO_GP0_IO, 0x000006f9);
  382. if (core->prev_set_voltage)
  383. return core->prev_set_voltage(fe, voltage);
  384. return 0;
  385. }
  386. static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
  387. enum fe_sec_voltage voltage)
  388. {
  389. struct cx8802_dev *dev = fe->dvb->priv;
  390. struct cx88_core *core = dev->core;
  391. if (voltage == SEC_VOLTAGE_OFF) {
  392. dprintk(1, "LNB Voltage OFF\n");
  393. cx_write(MO_GP0_IO, 0x0000efff);
  394. }
  395. if (core->prev_set_voltage)
  396. return core->prev_set_voltage(fe, voltage);
  397. return 0;
  398. }
  399. static int tevii_dvbs_set_voltage(struct dvb_frontend *fe,
  400. enum fe_sec_voltage voltage)
  401. {
  402. struct cx8802_dev *dev = fe->dvb->priv;
  403. struct cx88_core *core = dev->core;
  404. cx_set(MO_GP0_IO, 0x6040);
  405. switch (voltage) {
  406. case SEC_VOLTAGE_13:
  407. cx_clear(MO_GP0_IO, 0x20);
  408. break;
  409. case SEC_VOLTAGE_18:
  410. cx_set(MO_GP0_IO, 0x20);
  411. break;
  412. case SEC_VOLTAGE_OFF:
  413. cx_clear(MO_GP0_IO, 0x20);
  414. break;
  415. }
  416. if (core->prev_set_voltage)
  417. return core->prev_set_voltage(fe, voltage);
  418. return 0;
  419. }
  420. static int vp1027_set_voltage(struct dvb_frontend *fe,
  421. enum fe_sec_voltage voltage)
  422. {
  423. struct cx8802_dev *dev = fe->dvb->priv;
  424. struct cx88_core *core = dev->core;
  425. switch (voltage) {
  426. case SEC_VOLTAGE_13:
  427. dprintk(1, "LNB SEC Voltage=13\n");
  428. cx_write(MO_GP0_IO, 0x00001220);
  429. break;
  430. case SEC_VOLTAGE_18:
  431. dprintk(1, "LNB SEC Voltage=18\n");
  432. cx_write(MO_GP0_IO, 0x00001222);
  433. break;
  434. case SEC_VOLTAGE_OFF:
  435. dprintk(1, "LNB Voltage OFF\n");
  436. cx_write(MO_GP0_IO, 0x00001230);
  437. break;
  438. }
  439. if (core->prev_set_voltage)
  440. return core->prev_set_voltage(fe, voltage);
  441. return 0;
  442. }
  443. static const struct cx24123_config geniatech_dvbs_config = {
  444. .demod_address = 0x55,
  445. .set_ts_params = cx24123_set_ts_param,
  446. };
  447. static const struct cx24123_config hauppauge_novas_config = {
  448. .demod_address = 0x55,
  449. .set_ts_params = cx24123_set_ts_param,
  450. };
  451. static const struct cx24123_config kworld_dvbs_100_config = {
  452. .demod_address = 0x15,
  453. .set_ts_params = cx24123_set_ts_param,
  454. .lnb_polarity = 1,
  455. };
  456. static const struct s5h1409_config pinnacle_pctv_hd_800i_config = {
  457. .demod_address = 0x32 >> 1,
  458. .output_mode = S5H1409_PARALLEL_OUTPUT,
  459. .gpio = S5H1409_GPIO_ON,
  460. .qam_if = 44000,
  461. .inversion = S5H1409_INVERSION_OFF,
  462. .status_mode = S5H1409_DEMODLOCKING,
  463. .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK,
  464. };
  465. static const struct s5h1409_config dvico_hdtv5_pci_nano_config = {
  466. .demod_address = 0x32 >> 1,
  467. .output_mode = S5H1409_SERIAL_OUTPUT,
  468. .gpio = S5H1409_GPIO_OFF,
  469. .inversion = S5H1409_INVERSION_OFF,
  470. .status_mode = S5H1409_DEMODLOCKING,
  471. .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
  472. };
  473. static const struct s5h1409_config kworld_atsc_120_config = {
  474. .demod_address = 0x32 >> 1,
  475. .output_mode = S5H1409_SERIAL_OUTPUT,
  476. .gpio = S5H1409_GPIO_OFF,
  477. .inversion = S5H1409_INVERSION_OFF,
  478. .status_mode = S5H1409_DEMODLOCKING,
  479. .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
  480. };
  481. static const struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
  482. .i2c_address = 0x64,
  483. .if_khz = 5380,
  484. };
  485. static const struct zl10353_config cx88_pinnacle_hybrid_pctv = {
  486. .demod_address = (0x1e >> 1),
  487. .no_tuner = 1,
  488. .if2 = 45600,
  489. };
  490. static const struct zl10353_config cx88_geniatech_x8000_mt = {
  491. .demod_address = (0x1e >> 1),
  492. .no_tuner = 1,
  493. .disable_i2c_gate_ctrl = 1,
  494. };
  495. static const struct s5h1411_config dvico_fusionhdtv7_config = {
  496. .output_mode = S5H1411_SERIAL_OUTPUT,
  497. .gpio = S5H1411_GPIO_ON,
  498. .mpeg_timing = S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
  499. .qam_if = S5H1411_IF_44000,
  500. .vsb_if = S5H1411_IF_44000,
  501. .inversion = S5H1411_INVERSION_OFF,
  502. .status_mode = S5H1411_DEMODLOCKING
  503. };
  504. static const struct xc5000_config dvico_fusionhdtv7_tuner_config = {
  505. .i2c_address = 0xc2 >> 1,
  506. .if_khz = 5380,
  507. };
  508. static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
  509. {
  510. struct dvb_frontend *fe;
  511. struct vb2_dvb_frontend *fe0 = NULL;
  512. struct xc2028_ctrl ctl;
  513. struct xc2028_config cfg = {
  514. .i2c_adap = &dev->core->i2c_adap,
  515. .i2c_addr = addr,
  516. .ctrl = &ctl,
  517. };
  518. /* Get the first frontend */
  519. fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
  520. if (!fe0)
  521. return -EINVAL;
  522. if (!fe0->dvb.frontend) {
  523. pr_err("dvb frontend not attached. Can't attach xc3028\n");
  524. return -EINVAL;
  525. }
  526. /*
  527. * Some xc3028 devices may be hidden by an I2C gate. This is known
  528. * to happen with some s5h1409-based devices.
  529. * Now that I2C gate is open, sets up xc3028 configuration
  530. */
  531. cx88_setup_xc3028(dev->core, &ctl);
  532. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, &cfg);
  533. if (!fe) {
  534. pr_err("xc3028 attach failed\n");
  535. dvb_frontend_detach(fe0->dvb.frontend);
  536. dvb_unregister_frontend(fe0->dvb.frontend);
  537. fe0->dvb.frontend = NULL;
  538. return -EINVAL;
  539. }
  540. pr_info("xc3028 attached\n");
  541. return 0;
  542. }
  543. static int attach_xc4000(struct cx8802_dev *dev, struct xc4000_config *cfg)
  544. {
  545. struct dvb_frontend *fe;
  546. struct vb2_dvb_frontend *fe0 = NULL;
  547. /* Get the first frontend */
  548. fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
  549. if (!fe0)
  550. return -EINVAL;
  551. if (!fe0->dvb.frontend) {
  552. pr_err("dvb frontend not attached. Can't attach xc4000\n");
  553. return -EINVAL;
  554. }
  555. fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, &dev->core->i2c_adap,
  556. cfg);
  557. if (!fe) {
  558. pr_err("xc4000 attach failed\n");
  559. dvb_frontend_detach(fe0->dvb.frontend);
  560. dvb_unregister_frontend(fe0->dvb.frontend);
  561. fe0->dvb.frontend = NULL;
  562. return -EINVAL;
  563. }
  564. pr_info("xc4000 attached\n");
  565. return 0;
  566. }
  567. static int cx24116_set_ts_param(struct dvb_frontend *fe,
  568. int is_punctured)
  569. {
  570. struct cx8802_dev *dev = fe->dvb->priv;
  571. dev->ts_gen_cntrl = 0x2;
  572. return 0;
  573. }
  574. static int stv0900_set_ts_param(struct dvb_frontend *fe,
  575. int is_punctured)
  576. {
  577. struct cx8802_dev *dev = fe->dvb->priv;
  578. dev->ts_gen_cntrl = 0;
  579. return 0;
  580. }
  581. static int cx24116_reset_device(struct dvb_frontend *fe)
  582. {
  583. struct cx8802_dev *dev = fe->dvb->priv;
  584. struct cx88_core *core = dev->core;
  585. /* Reset the part */
  586. /* Put the cx24116 into reset */
  587. cx_write(MO_SRST_IO, 0);
  588. usleep_range(10000, 20000);
  589. /* Take the cx24116 out of reset */
  590. cx_write(MO_SRST_IO, 1);
  591. usleep_range(10000, 20000);
  592. return 0;
  593. }
  594. static const struct cx24116_config hauppauge_hvr4000_config = {
  595. .demod_address = 0x05,
  596. .set_ts_params = cx24116_set_ts_param,
  597. .reset_device = cx24116_reset_device,
  598. };
  599. static const struct cx24116_config tevii_s460_config = {
  600. .demod_address = 0x55,
  601. .set_ts_params = cx24116_set_ts_param,
  602. .reset_device = cx24116_reset_device,
  603. };
  604. static int ds3000_set_ts_param(struct dvb_frontend *fe,
  605. int is_punctured)
  606. {
  607. struct cx8802_dev *dev = fe->dvb->priv;
  608. dev->ts_gen_cntrl = 4;
  609. return 0;
  610. }
  611. static struct ds3000_config tevii_ds3000_config = {
  612. .demod_address = 0x68,
  613. .set_ts_params = ds3000_set_ts_param,
  614. };
  615. static struct ts2020_config tevii_ts2020_config = {
  616. .tuner_address = 0x60,
  617. .clk_out_div = 1,
  618. };
  619. static const struct stv0900_config prof_7301_stv0900_config = {
  620. .demod_address = 0x6a,
  621. /* demod_mode = 0,*/
  622. .xtal = 27000000,
  623. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  624. .diseqc_mode = 2,/* 2/3 PWM */
  625. .tun1_maddress = 0,/* 0x60 */
  626. .tun1_adc = 0,/* 2 Vpp */
  627. .path1_mode = 3,
  628. .set_ts_params = stv0900_set_ts_param,
  629. };
  630. static const struct stb6100_config prof_7301_stb6100_config = {
  631. .tuner_address = 0x60,
  632. .refclock = 27000000,
  633. };
  634. static const struct stv0299_config tevii_tuner_sharp_config = {
  635. .demod_address = 0x68,
  636. .inittab = sharp_z0194a_inittab,
  637. .mclk = 88000000UL,
  638. .invert = 1,
  639. .skip_reinit = 0,
  640. .lock_output = 1,
  641. .volt13_op0_op1 = STV0299_VOLT13_OP1,
  642. .min_delay_ms = 100,
  643. .set_symbol_rate = sharp_z0194a_set_symbol_rate,
  644. .set_ts_params = cx24116_set_ts_param,
  645. };
  646. static const struct stv0288_config tevii_tuner_earda_config = {
  647. .demod_address = 0x68,
  648. .min_delay_ms = 100,
  649. .set_ts_params = cx24116_set_ts_param,
  650. };
  651. static int cx8802_alloc_frontends(struct cx8802_dev *dev)
  652. {
  653. struct cx88_core *core = dev->core;
  654. struct vb2_dvb_frontend *fe = NULL;
  655. int i;
  656. mutex_init(&dev->frontends.lock);
  657. INIT_LIST_HEAD(&dev->frontends.felist);
  658. if (!core->board.num_frontends)
  659. return -ENODEV;
  660. pr_info("%s: allocating %d frontend(s)\n", __func__,
  661. core->board.num_frontends);
  662. for (i = 1; i <= core->board.num_frontends; i++) {
  663. fe = vb2_dvb_alloc_frontend(&dev->frontends, i);
  664. if (!fe) {
  665. pr_err("%s() failed to alloc\n", __func__);
  666. vb2_dvb_dealloc_frontends(&dev->frontends);
  667. return -ENOMEM;
  668. }
  669. }
  670. return 0;
  671. }
  672. static const u8 samsung_smt_7020_inittab[] = {
  673. 0x01, 0x15,
  674. 0x02, 0x00,
  675. 0x03, 0x00,
  676. 0x04, 0x7D,
  677. 0x05, 0x0F,
  678. 0x06, 0x02,
  679. 0x07, 0x00,
  680. 0x08, 0x60,
  681. 0x0A, 0xC2,
  682. 0x0B, 0x00,
  683. 0x0C, 0x01,
  684. 0x0D, 0x81,
  685. 0x0E, 0x44,
  686. 0x0F, 0x09,
  687. 0x10, 0x3C,
  688. 0x11, 0x84,
  689. 0x12, 0xDA,
  690. 0x13, 0x99,
  691. 0x14, 0x8D,
  692. 0x15, 0xCE,
  693. 0x16, 0xE8,
  694. 0x17, 0x43,
  695. 0x18, 0x1C,
  696. 0x19, 0x1B,
  697. 0x1A, 0x1D,
  698. 0x1C, 0x12,
  699. 0x1D, 0x00,
  700. 0x1E, 0x00,
  701. 0x1F, 0x00,
  702. 0x20, 0x00,
  703. 0x21, 0x00,
  704. 0x22, 0x00,
  705. 0x23, 0x00,
  706. 0x28, 0x02,
  707. 0x29, 0x28,
  708. 0x2A, 0x14,
  709. 0x2B, 0x0F,
  710. 0x2C, 0x09,
  711. 0x2D, 0x05,
  712. 0x31, 0x1F,
  713. 0x32, 0x19,
  714. 0x33, 0xFC,
  715. 0x34, 0x13,
  716. 0xff, 0xff,
  717. };
  718. static int samsung_smt_7020_tuner_set_params(struct dvb_frontend *fe)
  719. {
  720. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  721. struct cx8802_dev *dev = fe->dvb->priv;
  722. u8 buf[4];
  723. u32 div;
  724. struct i2c_msg msg = {
  725. .addr = 0x61,
  726. .flags = 0,
  727. .buf = buf,
  728. .len = sizeof(buf) };
  729. div = c->frequency / 125;
  730. buf[0] = (div >> 8) & 0x7f;
  731. buf[1] = div & 0xff;
  732. buf[2] = 0x84; /* 0xC4 */
  733. buf[3] = 0x00;
  734. if (c->frequency < 1500000)
  735. buf[3] |= 0x10;
  736. if (fe->ops.i2c_gate_ctrl)
  737. fe->ops.i2c_gate_ctrl(fe, 1);
  738. if (i2c_transfer(&dev->core->i2c_adap, &msg, 1) != 1)
  739. return -EIO;
  740. return 0;
  741. }
  742. static int samsung_smt_7020_set_tone(struct dvb_frontend *fe,
  743. enum fe_sec_tone_mode tone)
  744. {
  745. struct cx8802_dev *dev = fe->dvb->priv;
  746. struct cx88_core *core = dev->core;
  747. cx_set(MO_GP0_IO, 0x0800);
  748. switch (tone) {
  749. case SEC_TONE_ON:
  750. cx_set(MO_GP0_IO, 0x08);
  751. break;
  752. case SEC_TONE_OFF:
  753. cx_clear(MO_GP0_IO, 0x08);
  754. break;
  755. default:
  756. return -EINVAL;
  757. }
  758. return 0;
  759. }
  760. static int samsung_smt_7020_set_voltage(struct dvb_frontend *fe,
  761. enum fe_sec_voltage voltage)
  762. {
  763. struct cx8802_dev *dev = fe->dvb->priv;
  764. struct cx88_core *core = dev->core;
  765. u8 data;
  766. struct i2c_msg msg = {
  767. .addr = 8,
  768. .flags = 0,
  769. .buf = &data,
  770. .len = sizeof(data) };
  771. cx_set(MO_GP0_IO, 0x8000);
  772. switch (voltage) {
  773. case SEC_VOLTAGE_OFF:
  774. break;
  775. case SEC_VOLTAGE_13:
  776. data = ISL6421_EN1 | ISL6421_LLC1;
  777. cx_clear(MO_GP0_IO, 0x80);
  778. break;
  779. case SEC_VOLTAGE_18:
  780. data = ISL6421_EN1 | ISL6421_LLC1 | ISL6421_VSEL1;
  781. cx_clear(MO_GP0_IO, 0x80);
  782. break;
  783. default:
  784. return -EINVAL;
  785. }
  786. return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO;
  787. }
  788. static int samsung_smt_7020_stv0299_set_symbol_rate(struct dvb_frontend *fe,
  789. u32 srate, u32 ratio)
  790. {
  791. u8 aclk = 0;
  792. u8 bclk = 0;
  793. if (srate < 1500000) {
  794. aclk = 0xb7;
  795. bclk = 0x47;
  796. } else if (srate < 3000000) {
  797. aclk = 0xb7;
  798. bclk = 0x4b;
  799. } else if (srate < 7000000) {
  800. aclk = 0xb7;
  801. bclk = 0x4f;
  802. } else if (srate < 14000000) {
  803. aclk = 0xb7;
  804. bclk = 0x53;
  805. } else if (srate < 30000000) {
  806. aclk = 0xb6;
  807. bclk = 0x53;
  808. } else if (srate < 45000000) {
  809. aclk = 0xb4;
  810. bclk = 0x51;
  811. }
  812. stv0299_writereg(fe, 0x13, aclk);
  813. stv0299_writereg(fe, 0x14, bclk);
  814. stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
  815. stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
  816. stv0299_writereg(fe, 0x21, ratio & 0xf0);
  817. return 0;
  818. }
  819. static const struct stv0299_config samsung_stv0299_config = {
  820. .demod_address = 0x68,
  821. .inittab = samsung_smt_7020_inittab,
  822. .mclk = 88000000UL,
  823. .invert = 0,
  824. .skip_reinit = 0,
  825. .lock_output = STV0299_LOCKOUTPUT_LK,
  826. .volt13_op0_op1 = STV0299_VOLT13_OP1,
  827. .min_delay_ms = 100,
  828. .set_symbol_rate = samsung_smt_7020_stv0299_set_symbol_rate,
  829. };
  830. static int dvb_register(struct cx8802_dev *dev)
  831. {
  832. struct cx88_core *core = dev->core;
  833. struct vb2_dvb_frontend *fe0, *fe1 = NULL;
  834. int mfe_shared = 0; /* bus not shared by default */
  835. int res = -EINVAL;
  836. if (core->i2c_rc != 0) {
  837. pr_err("no i2c-bus available, cannot attach dvb drivers\n");
  838. goto frontend_detach;
  839. }
  840. /* Get the first frontend */
  841. fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
  842. if (!fe0)
  843. goto frontend_detach;
  844. /* multi-frontend gate control is undefined or defaults to fe0 */
  845. dev->frontends.gate = 0;
  846. /* Sets the gate control callback to be used by i2c command calls */
  847. core->gate_ctrl = cx88_dvb_gate_ctrl;
  848. /* init frontend(s) */
  849. switch (core->boardnr) {
  850. case CX88_BOARD_HAUPPAUGE_DVB_T1:
  851. fe0->dvb.frontend = dvb_attach(cx22702_attach,
  852. &connexant_refboard_config,
  853. &core->i2c_adap);
  854. if (fe0->dvb.frontend) {
  855. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  856. 0x61, &core->i2c_adap,
  857. DVB_PLL_THOMSON_DTT759X))
  858. goto frontend_detach;
  859. }
  860. break;
  861. case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
  862. case CX88_BOARD_CONEXANT_DVB_T1:
  863. case CX88_BOARD_KWORLD_DVB_T_CX22702:
  864. case CX88_BOARD_WINFAST_DTV1000:
  865. fe0->dvb.frontend = dvb_attach(cx22702_attach,
  866. &connexant_refboard_config,
  867. &core->i2c_adap);
  868. if (fe0->dvb.frontend) {
  869. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  870. 0x60, &core->i2c_adap,
  871. DVB_PLL_THOMSON_DTT7579))
  872. goto frontend_detach;
  873. }
  874. break;
  875. case CX88_BOARD_WINFAST_DTV2000H:
  876. case CX88_BOARD_HAUPPAUGE_HVR1100:
  877. case CX88_BOARD_HAUPPAUGE_HVR1100LP:
  878. case CX88_BOARD_HAUPPAUGE_HVR1300:
  879. fe0->dvb.frontend = dvb_attach(cx22702_attach,
  880. &hauppauge_hvr_config,
  881. &core->i2c_adap);
  882. if (fe0->dvb.frontend) {
  883. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  884. &core->i2c_adap, 0x61,
  885. TUNER_PHILIPS_FMD1216ME_MK3))
  886. goto frontend_detach;
  887. }
  888. break;
  889. case CX88_BOARD_WINFAST_DTV2000H_J:
  890. fe0->dvb.frontend = dvb_attach(cx22702_attach,
  891. &hauppauge_hvr_config,
  892. &core->i2c_adap);
  893. if (fe0->dvb.frontend) {
  894. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  895. &core->i2c_adap, 0x61,
  896. TUNER_PHILIPS_FMD1216MEX_MK3))
  897. goto frontend_detach;
  898. }
  899. break;
  900. case CX88_BOARD_HAUPPAUGE_HVR3000:
  901. /* MFE frontend 1 */
  902. mfe_shared = 1;
  903. dev->frontends.gate = 2;
  904. /* DVB-S init */
  905. fe0->dvb.frontend = dvb_attach(cx24123_attach,
  906. &hauppauge_novas_config,
  907. &dev->core->i2c_adap);
  908. if (fe0->dvb.frontend) {
  909. if (!dvb_attach(isl6421_attach,
  910. fe0->dvb.frontend,
  911. &dev->core->i2c_adap,
  912. 0x08, ISL6421_DCL, 0x00, false))
  913. goto frontend_detach;
  914. }
  915. /* MFE frontend 2 */
  916. fe1 = vb2_dvb_get_frontend(&dev->frontends, 2);
  917. if (!fe1)
  918. goto frontend_detach;
  919. /* DVB-T init */
  920. fe1->dvb.frontend = dvb_attach(cx22702_attach,
  921. &hauppauge_hvr_config,
  922. &dev->core->i2c_adap);
  923. if (fe1->dvb.frontend) {
  924. fe1->dvb.frontend->id = 1;
  925. if (!dvb_attach(simple_tuner_attach,
  926. fe1->dvb.frontend,
  927. &dev->core->i2c_adap,
  928. 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
  929. goto frontend_detach;
  930. }
  931. break;
  932. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
  933. fe0->dvb.frontend = dvb_attach(mt352_attach,
  934. &dvico_fusionhdtv,
  935. &core->i2c_adap);
  936. if (fe0->dvb.frontend) {
  937. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  938. 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
  939. goto frontend_detach;
  940. break;
  941. }
  942. /* ZL10353 replaces MT352 on later cards */
  943. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  944. &dvico_fusionhdtv_plus_v1_1,
  945. &core->i2c_adap);
  946. if (fe0->dvb.frontend) {
  947. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  948. 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
  949. goto frontend_detach;
  950. }
  951. break;
  952. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
  953. /*
  954. * The tin box says DEE1601, but it seems to be DTT7579
  955. * compatible, with a slightly different MT352 AGC gain.
  956. */
  957. fe0->dvb.frontend = dvb_attach(mt352_attach,
  958. &dvico_fusionhdtv_dual,
  959. &core->i2c_adap);
  960. if (fe0->dvb.frontend) {
  961. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  962. 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
  963. goto frontend_detach;
  964. break;
  965. }
  966. /* ZL10353 replaces MT352 on later cards */
  967. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  968. &dvico_fusionhdtv_plus_v1_1,
  969. &core->i2c_adap);
  970. if (fe0->dvb.frontend) {
  971. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  972. 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
  973. goto frontend_detach;
  974. }
  975. break;
  976. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
  977. fe0->dvb.frontend = dvb_attach(mt352_attach,
  978. &dvico_fusionhdtv,
  979. &core->i2c_adap);
  980. if (fe0->dvb.frontend) {
  981. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  982. 0x61, NULL, DVB_PLL_LG_Z201))
  983. goto frontend_detach;
  984. }
  985. break;
  986. case CX88_BOARD_KWORLD_DVB_T:
  987. case CX88_BOARD_DNTV_LIVE_DVB_T:
  988. case CX88_BOARD_ADSTECH_DVB_T_PCI:
  989. fe0->dvb.frontend = dvb_attach(mt352_attach,
  990. &dntv_live_dvbt_config,
  991. &core->i2c_adap);
  992. if (fe0->dvb.frontend) {
  993. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  994. 0x61, NULL, DVB_PLL_UNKNOWN_1))
  995. goto frontend_detach;
  996. }
  997. break;
  998. case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
  999. #if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054)
  1000. /* MT352 is on a secondary I2C bus made from some GPIO lines */
  1001. fe0->dvb.frontend = dvb_attach(mt352_attach,
  1002. &dntv_live_dvbt_pro_config,
  1003. &dev->vp3054->adap);
  1004. if (fe0->dvb.frontend) {
  1005. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1006. &core->i2c_adap, 0x61,
  1007. TUNER_PHILIPS_FMD1216ME_MK3))
  1008. goto frontend_detach;
  1009. }
  1010. #else
  1011. pr_err("built without vp3054 support\n");
  1012. #endif
  1013. break;
  1014. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
  1015. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1016. &dvico_fusionhdtv_hybrid,
  1017. &core->i2c_adap);
  1018. if (fe0->dvb.frontend) {
  1019. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1020. &core->i2c_adap, 0x61,
  1021. TUNER_THOMSON_FE6600))
  1022. goto frontend_detach;
  1023. }
  1024. break;
  1025. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
  1026. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1027. &dvico_fusionhdtv_xc3028,
  1028. &core->i2c_adap);
  1029. if (!fe0->dvb.frontend)
  1030. fe0->dvb.frontend = dvb_attach(mt352_attach,
  1031. &dvico_fusionhdtv_mt352_xc3028,
  1032. &core->i2c_adap);
  1033. /*
  1034. * On this board, the demod provides the I2C bus pullup.
  1035. * We must not permit gate_ctrl to be performed, or
  1036. * the xc3028 cannot communicate on the bus.
  1037. */
  1038. if (fe0->dvb.frontend)
  1039. fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  1040. if (attach_xc3028(0x61, dev) < 0)
  1041. goto frontend_detach;
  1042. break;
  1043. case CX88_BOARD_PCHDTV_HD3000:
  1044. fe0->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
  1045. &core->i2c_adap);
  1046. if (fe0->dvb.frontend) {
  1047. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1048. &core->i2c_adap, 0x61,
  1049. TUNER_THOMSON_DTT761X))
  1050. goto frontend_detach;
  1051. }
  1052. break;
  1053. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  1054. dev->ts_gen_cntrl = 0x08;
  1055. /* Do a hardware reset of chip before using it. */
  1056. cx_clear(MO_GP0_IO, 1);
  1057. msleep(100);
  1058. cx_set(MO_GP0_IO, 1);
  1059. msleep(200);
  1060. /* Select RF connector callback */
  1061. fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
  1062. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  1063. &fusionhdtv_3_gold,
  1064. 0x0e,
  1065. &core->i2c_adap);
  1066. if (fe0->dvb.frontend) {
  1067. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1068. &core->i2c_adap, 0x61,
  1069. TUNER_MICROTUNE_4042FI5))
  1070. goto frontend_detach;
  1071. }
  1072. break;
  1073. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  1074. dev->ts_gen_cntrl = 0x08;
  1075. /* Do a hardware reset of chip before using it. */
  1076. cx_clear(MO_GP0_IO, 1);
  1077. msleep(100);
  1078. cx_set(MO_GP0_IO, 9);
  1079. msleep(200);
  1080. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  1081. &fusionhdtv_3_gold,
  1082. 0x0e,
  1083. &core->i2c_adap);
  1084. if (fe0->dvb.frontend) {
  1085. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1086. &core->i2c_adap, 0x61,
  1087. TUNER_THOMSON_DTT761X))
  1088. goto frontend_detach;
  1089. }
  1090. break;
  1091. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  1092. dev->ts_gen_cntrl = 0x08;
  1093. /* Do a hardware reset of chip before using it. */
  1094. cx_clear(MO_GP0_IO, 1);
  1095. msleep(100);
  1096. cx_set(MO_GP0_IO, 1);
  1097. msleep(200);
  1098. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  1099. &fusionhdtv_5_gold,
  1100. 0x0e,
  1101. &core->i2c_adap);
  1102. if (fe0->dvb.frontend) {
  1103. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1104. &core->i2c_adap, 0x61,
  1105. TUNER_LG_TDVS_H06XF))
  1106. goto frontend_detach;
  1107. if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
  1108. &core->i2c_adap, 0x43))
  1109. goto frontend_detach;
  1110. }
  1111. break;
  1112. case CX88_BOARD_PCHDTV_HD5500:
  1113. dev->ts_gen_cntrl = 0x08;
  1114. /* Do a hardware reset of chip before using it. */
  1115. cx_clear(MO_GP0_IO, 1);
  1116. msleep(100);
  1117. cx_set(MO_GP0_IO, 1);
  1118. msleep(200);
  1119. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  1120. &pchdtv_hd5500,
  1121. 0x59,
  1122. &core->i2c_adap);
  1123. if (fe0->dvb.frontend) {
  1124. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1125. &core->i2c_adap, 0x61,
  1126. TUNER_LG_TDVS_H06XF))
  1127. goto frontend_detach;
  1128. if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
  1129. &core->i2c_adap, 0x43))
  1130. goto frontend_detach;
  1131. }
  1132. break;
  1133. case CX88_BOARD_ATI_HDTVWONDER:
  1134. fe0->dvb.frontend = dvb_attach(nxt200x_attach,
  1135. &ati_hdtvwonder,
  1136. &core->i2c_adap);
  1137. if (fe0->dvb.frontend) {
  1138. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1139. &core->i2c_adap, 0x61,
  1140. TUNER_PHILIPS_TUV1236D))
  1141. goto frontend_detach;
  1142. }
  1143. break;
  1144. case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
  1145. case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
  1146. fe0->dvb.frontend = dvb_attach(cx24123_attach,
  1147. &hauppauge_novas_config,
  1148. &core->i2c_adap);
  1149. if (fe0->dvb.frontend) {
  1150. bool override_tone;
  1151. if (core->model == 92001)
  1152. override_tone = true;
  1153. else
  1154. override_tone = false;
  1155. if (!dvb_attach(isl6421_attach, fe0->dvb.frontend,
  1156. &core->i2c_adap, 0x08, ISL6421_DCL,
  1157. 0x00, override_tone))
  1158. goto frontend_detach;
  1159. }
  1160. break;
  1161. case CX88_BOARD_KWORLD_DVBS_100:
  1162. fe0->dvb.frontend = dvb_attach(cx24123_attach,
  1163. &kworld_dvbs_100_config,
  1164. &core->i2c_adap);
  1165. if (fe0->dvb.frontend) {
  1166. core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
  1167. fe0->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
  1168. }
  1169. break;
  1170. case CX88_BOARD_GENIATECH_DVBS:
  1171. fe0->dvb.frontend = dvb_attach(cx24123_attach,
  1172. &geniatech_dvbs_config,
  1173. &core->i2c_adap);
  1174. if (fe0->dvb.frontend) {
  1175. core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
  1176. fe0->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
  1177. }
  1178. break;
  1179. case CX88_BOARD_PINNACLE_PCTV_HD_800i:
  1180. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  1181. &pinnacle_pctv_hd_800i_config,
  1182. &core->i2c_adap);
  1183. if (fe0->dvb.frontend) {
  1184. if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
  1185. &core->i2c_adap,
  1186. &pinnacle_pctv_hd_800i_tuner_config))
  1187. goto frontend_detach;
  1188. }
  1189. break;
  1190. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  1191. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  1192. &dvico_hdtv5_pci_nano_config,
  1193. &core->i2c_adap);
  1194. if (fe0->dvb.frontend) {
  1195. struct dvb_frontend *fe;
  1196. struct xc2028_config cfg = {
  1197. .i2c_adap = &core->i2c_adap,
  1198. .i2c_addr = 0x61,
  1199. };
  1200. static struct xc2028_ctrl ctl = {
  1201. .fname = XC2028_DEFAULT_FIRMWARE,
  1202. .max_len = 64,
  1203. .scode_table = XC3028_FE_OREN538,
  1204. };
  1205. fe = dvb_attach(xc2028_attach,
  1206. fe0->dvb.frontend, &cfg);
  1207. if (fe && fe->ops.tuner_ops.set_config)
  1208. fe->ops.tuner_ops.set_config(fe, &ctl);
  1209. }
  1210. break;
  1211. case CX88_BOARD_PINNACLE_HYBRID_PCTV:
  1212. case CX88_BOARD_WINFAST_DTV1800H:
  1213. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1214. &cx88_pinnacle_hybrid_pctv,
  1215. &core->i2c_adap);
  1216. if (fe0->dvb.frontend) {
  1217. fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  1218. if (attach_xc3028(0x61, dev) < 0)
  1219. goto frontend_detach;
  1220. }
  1221. break;
  1222. case CX88_BOARD_WINFAST_DTV1800H_XC4000:
  1223. case CX88_BOARD_WINFAST_DTV2000H_PLUS:
  1224. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1225. &cx88_pinnacle_hybrid_pctv,
  1226. &core->i2c_adap);
  1227. if (fe0->dvb.frontend) {
  1228. struct xc4000_config cfg = {
  1229. .i2c_address = 0x61,
  1230. .default_pm = 0,
  1231. .dvb_amplitude = 134,
  1232. .set_smoothedcvbs = 1,
  1233. .if_khz = 4560
  1234. };
  1235. fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  1236. if (attach_xc4000(dev, &cfg) < 0)
  1237. goto frontend_detach;
  1238. }
  1239. break;
  1240. case CX88_BOARD_GENIATECH_X8000_MT:
  1241. dev->ts_gen_cntrl = 0x00;
  1242. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1243. &cx88_geniatech_x8000_mt,
  1244. &core->i2c_adap);
  1245. if (attach_xc3028(0x61, dev) < 0)
  1246. goto frontend_detach;
  1247. break;
  1248. case CX88_BOARD_KWORLD_ATSC_120:
  1249. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  1250. &kworld_atsc_120_config,
  1251. &core->i2c_adap);
  1252. if (attach_xc3028(0x61, dev) < 0)
  1253. goto frontend_detach;
  1254. break;
  1255. case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
  1256. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1257. &dvico_fusionhdtv7_config,
  1258. &core->i2c_adap);
  1259. if (fe0->dvb.frontend) {
  1260. if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
  1261. &core->i2c_adap,
  1262. &dvico_fusionhdtv7_tuner_config))
  1263. goto frontend_detach;
  1264. }
  1265. break;
  1266. case CX88_BOARD_HAUPPAUGE_HVR4000:
  1267. /* MFE frontend 1 */
  1268. mfe_shared = 1;
  1269. dev->frontends.gate = 2;
  1270. /* DVB-S/S2 Init */
  1271. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1272. &hauppauge_hvr4000_config,
  1273. &dev->core->i2c_adap);
  1274. if (fe0->dvb.frontend) {
  1275. if (!dvb_attach(isl6421_attach,
  1276. fe0->dvb.frontend,
  1277. &dev->core->i2c_adap,
  1278. 0x08, ISL6421_DCL, 0x00, false))
  1279. goto frontend_detach;
  1280. }
  1281. /* MFE frontend 2 */
  1282. fe1 = vb2_dvb_get_frontend(&dev->frontends, 2);
  1283. if (!fe1)
  1284. goto frontend_detach;
  1285. /* DVB-T Init */
  1286. fe1->dvb.frontend = dvb_attach(cx22702_attach,
  1287. &hauppauge_hvr_config,
  1288. &dev->core->i2c_adap);
  1289. if (fe1->dvb.frontend) {
  1290. fe1->dvb.frontend->id = 1;
  1291. if (!dvb_attach(simple_tuner_attach,
  1292. fe1->dvb.frontend,
  1293. &dev->core->i2c_adap,
  1294. 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
  1295. goto frontend_detach;
  1296. }
  1297. break;
  1298. case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
  1299. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1300. &hauppauge_hvr4000_config,
  1301. &dev->core->i2c_adap);
  1302. if (fe0->dvb.frontend) {
  1303. if (!dvb_attach(isl6421_attach,
  1304. fe0->dvb.frontend,
  1305. &dev->core->i2c_adap,
  1306. 0x08, ISL6421_DCL, 0x00, false))
  1307. goto frontend_detach;
  1308. }
  1309. break;
  1310. case CX88_BOARD_PROF_6200:
  1311. case CX88_BOARD_TBS_8910:
  1312. case CX88_BOARD_TEVII_S420:
  1313. fe0->dvb.frontend = dvb_attach(stv0299_attach,
  1314. &tevii_tuner_sharp_config,
  1315. &core->i2c_adap);
  1316. if (fe0->dvb.frontend) {
  1317. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x60,
  1318. &core->i2c_adap, DVB_PLL_OPERA1))
  1319. goto frontend_detach;
  1320. core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
  1321. fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
  1322. } else {
  1323. fe0->dvb.frontend = dvb_attach(stv0288_attach,
  1324. &tevii_tuner_earda_config,
  1325. &core->i2c_adap);
  1326. if (fe0->dvb.frontend) {
  1327. if (!dvb_attach(stb6000_attach,
  1328. fe0->dvb.frontend, 0x61,
  1329. &core->i2c_adap))
  1330. goto frontend_detach;
  1331. core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
  1332. fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
  1333. }
  1334. }
  1335. break;
  1336. case CX88_BOARD_TEVII_S460:
  1337. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1338. &tevii_s460_config,
  1339. &core->i2c_adap);
  1340. if (fe0->dvb.frontend)
  1341. fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
  1342. break;
  1343. case CX88_BOARD_TEVII_S464:
  1344. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  1345. &tevii_ds3000_config,
  1346. &core->i2c_adap);
  1347. if (fe0->dvb.frontend) {
  1348. dvb_attach(ts2020_attach, fe0->dvb.frontend,
  1349. &tevii_ts2020_config, &core->i2c_adap);
  1350. fe0->dvb.frontend->ops.set_voltage =
  1351. tevii_dvbs_set_voltage;
  1352. }
  1353. break;
  1354. case CX88_BOARD_OMICOM_SS4_PCI:
  1355. case CX88_BOARD_TBS_8920:
  1356. case CX88_BOARD_PROF_7300:
  1357. case CX88_BOARD_SATTRADE_ST4200:
  1358. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1359. &hauppauge_hvr4000_config,
  1360. &core->i2c_adap);
  1361. if (fe0->dvb.frontend)
  1362. fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
  1363. break;
  1364. case CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII:
  1365. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1366. &cx88_terratec_cinergy_ht_pci_mkii_config,
  1367. &core->i2c_adap);
  1368. if (fe0->dvb.frontend) {
  1369. fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  1370. if (attach_xc3028(0x61, dev) < 0)
  1371. goto frontend_detach;
  1372. }
  1373. break;
  1374. case CX88_BOARD_PROF_7301:{
  1375. struct dvb_tuner_ops *tuner_ops = NULL;
  1376. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  1377. &prof_7301_stv0900_config,
  1378. &core->i2c_adap, 0);
  1379. if (fe0->dvb.frontend) {
  1380. if (!dvb_attach(stb6100_attach, fe0->dvb.frontend,
  1381. &prof_7301_stb6100_config,
  1382. &core->i2c_adap))
  1383. goto frontend_detach;
  1384. tuner_ops = &fe0->dvb.frontend->ops.tuner_ops;
  1385. tuner_ops->set_frequency = stb6100_set_freq;
  1386. tuner_ops->get_frequency = stb6100_get_freq;
  1387. tuner_ops->set_bandwidth = stb6100_set_bandw;
  1388. tuner_ops->get_bandwidth = stb6100_get_bandw;
  1389. core->prev_set_voltage =
  1390. fe0->dvb.frontend->ops.set_voltage;
  1391. fe0->dvb.frontend->ops.set_voltage =
  1392. tevii_dvbs_set_voltage;
  1393. }
  1394. break;
  1395. }
  1396. case CX88_BOARD_SAMSUNG_SMT_7020:
  1397. dev->ts_gen_cntrl = 0x08;
  1398. cx_set(MO_GP0_IO, 0x0101);
  1399. cx_clear(MO_GP0_IO, 0x01);
  1400. msleep(100);
  1401. cx_set(MO_GP0_IO, 0x01);
  1402. msleep(200);
  1403. fe0->dvb.frontend = dvb_attach(stv0299_attach,
  1404. &samsung_stv0299_config,
  1405. &dev->core->i2c_adap);
  1406. if (fe0->dvb.frontend) {
  1407. fe0->dvb.frontend->ops.tuner_ops.set_params =
  1408. samsung_smt_7020_tuner_set_params;
  1409. fe0->dvb.frontend->tuner_priv =
  1410. &dev->core->i2c_adap;
  1411. fe0->dvb.frontend->ops.set_voltage =
  1412. samsung_smt_7020_set_voltage;
  1413. fe0->dvb.frontend->ops.set_tone =
  1414. samsung_smt_7020_set_tone;
  1415. }
  1416. break;
  1417. case CX88_BOARD_TWINHAN_VP1027_DVBS:
  1418. dev->ts_gen_cntrl = 0x00;
  1419. fe0->dvb.frontend = dvb_attach(mb86a16_attach,
  1420. &twinhan_vp1027,
  1421. &core->i2c_adap);
  1422. if (fe0->dvb.frontend) {
  1423. core->prev_set_voltage =
  1424. fe0->dvb.frontend->ops.set_voltage;
  1425. fe0->dvb.frontend->ops.set_voltage =
  1426. vp1027_set_voltage;
  1427. }
  1428. break;
  1429. default:
  1430. pr_err("The frontend of your DVB/ATSC card isn't supported yet\n");
  1431. break;
  1432. }
  1433. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  1434. pr_err("frontend initialization failed\n");
  1435. goto frontend_detach;
  1436. }
  1437. /* define general-purpose callback pointer */
  1438. fe0->dvb.frontend->callback = cx88_tuner_callback;
  1439. /* Ensure all frontends negotiate bus access */
  1440. fe0->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  1441. if (fe1)
  1442. fe1->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  1443. /* Put the tuner in standby to keep it quiet */
  1444. call_all(core, tuner, standby);
  1445. /* register everything */
  1446. res = vb2_dvb_register_bus(&dev->frontends, THIS_MODULE, dev,
  1447. &dev->pci->dev, NULL, adapter_nr,
  1448. mfe_shared);
  1449. if (res)
  1450. goto frontend_detach;
  1451. return res;
  1452. frontend_detach:
  1453. core->gate_ctrl = NULL;
  1454. vb2_dvb_dealloc_frontends(&dev->frontends);
  1455. return res;
  1456. }
  1457. /* ----------------------------------------------------------- */
  1458. /* CX8802 MPEG -> mini driver - We have been given the hardware */
  1459. static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
  1460. {
  1461. struct cx88_core *core = drv->core;
  1462. int err = 0;
  1463. dprintk(1, "%s\n", __func__);
  1464. switch (core->boardnr) {
  1465. case CX88_BOARD_HAUPPAUGE_HVR1300:
  1466. /* We arrive here with either the cx23416 or the cx22702
  1467. * on the bus. Take the bus from the cx23416 and enable the
  1468. * cx22702 demod
  1469. */
  1470. /* Toggle reset on cx22702 leaving i2c active */
  1471. cx_set(MO_GP0_IO, 0x00000080);
  1472. udelay(1000);
  1473. cx_clear(MO_GP0_IO, 0x00000080);
  1474. udelay(50);
  1475. cx_set(MO_GP0_IO, 0x00000080);
  1476. udelay(1000);
  1477. /* enable the cx22702 pins */
  1478. cx_clear(MO_GP0_IO, 0x00000004);
  1479. udelay(1000);
  1480. break;
  1481. case CX88_BOARD_HAUPPAUGE_HVR3000:
  1482. case CX88_BOARD_HAUPPAUGE_HVR4000:
  1483. /* Toggle reset on cx22702 leaving i2c active */
  1484. cx_set(MO_GP0_IO, 0x00000080);
  1485. udelay(1000);
  1486. cx_clear(MO_GP0_IO, 0x00000080);
  1487. udelay(50);
  1488. cx_set(MO_GP0_IO, 0x00000080);
  1489. udelay(1000);
  1490. switch (core->dvbdev->frontends.active_fe_id) {
  1491. case 1: /* DVB-S/S2 Enabled */
  1492. /* tri-state the cx22702 pins */
  1493. cx_set(MO_GP0_IO, 0x00000004);
  1494. /* Take the cx24116/cx24123 out of reset */
  1495. cx_write(MO_SRST_IO, 1);
  1496. core->dvbdev->ts_gen_cntrl = 0x02; /* Parallel IO */
  1497. break;
  1498. case 2: /* DVB-T Enabled */
  1499. /* Put the cx24116/cx24123 into reset */
  1500. cx_write(MO_SRST_IO, 0);
  1501. /* enable the cx22702 pins */
  1502. cx_clear(MO_GP0_IO, 0x00000004);
  1503. core->dvbdev->ts_gen_cntrl = 0x0c; /* Serial IO */
  1504. break;
  1505. }
  1506. udelay(1000);
  1507. break;
  1508. case CX88_BOARD_WINFAST_DTV2000H_PLUS:
  1509. /* set RF input to AIR for DVB-T (GPIO 16) */
  1510. cx_write(MO_GP2_IO, 0x0101);
  1511. break;
  1512. default:
  1513. err = -ENODEV;
  1514. }
  1515. return err;
  1516. }
  1517. /* CX8802 MPEG -> mini driver - We no longer have the hardware */
  1518. static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
  1519. {
  1520. struct cx88_core *core = drv->core;
  1521. int err = 0;
  1522. dprintk(1, "%s\n", __func__);
  1523. switch (core->boardnr) {
  1524. case CX88_BOARD_HAUPPAUGE_HVR1300:
  1525. /* Do Nothing, leave the cx22702 on the bus. */
  1526. break;
  1527. case CX88_BOARD_HAUPPAUGE_HVR3000:
  1528. case CX88_BOARD_HAUPPAUGE_HVR4000:
  1529. break;
  1530. default:
  1531. err = -ENODEV;
  1532. }
  1533. return err;
  1534. }
  1535. static int cx8802_dvb_probe(struct cx8802_driver *drv)
  1536. {
  1537. struct cx88_core *core = drv->core;
  1538. struct cx8802_dev *dev = drv->core->dvbdev;
  1539. int err;
  1540. struct vb2_dvb_frontend *fe;
  1541. int i;
  1542. dprintk(1, "%s\n", __func__);
  1543. dprintk(1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1544. core->boardnr,
  1545. core->name,
  1546. core->pci_bus,
  1547. core->pci_slot);
  1548. err = -ENODEV;
  1549. if (!(core->board.mpeg & CX88_MPEG_DVB))
  1550. goto fail_core;
  1551. /* If vp3054 isn't enabled, a stub will just return 0 */
  1552. err = vp3054_i2c_probe(dev);
  1553. if (err != 0)
  1554. goto fail_core;
  1555. /* dvb stuff */
  1556. pr_info("cx2388x based DVB/ATSC card\n");
  1557. dev->ts_gen_cntrl = 0x0c;
  1558. err = cx8802_alloc_frontends(dev);
  1559. if (err)
  1560. goto fail_core;
  1561. for (i = 1; i <= core->board.num_frontends; i++) {
  1562. struct vb2_queue *q;
  1563. fe = vb2_dvb_get_frontend(&core->dvbdev->frontends, i);
  1564. if (!fe) {
  1565. pr_err("%s() failed to get frontend(%d)\n",
  1566. __func__, i);
  1567. err = -ENODEV;
  1568. goto fail_probe;
  1569. }
  1570. q = &fe->dvb.dvbq;
  1571. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1572. q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
  1573. q->gfp_flags = GFP_DMA32;
  1574. q->min_buffers_needed = 2;
  1575. q->drv_priv = dev;
  1576. q->buf_struct_size = sizeof(struct cx88_buffer);
  1577. q->ops = &dvb_qops;
  1578. q->mem_ops = &vb2_dma_sg_memops;
  1579. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1580. q->lock = &core->lock;
  1581. q->dev = &dev->pci->dev;
  1582. err = vb2_queue_init(q);
  1583. if (err < 0)
  1584. goto fail_probe;
  1585. /* init struct vb2_dvb */
  1586. fe->dvb.name = dev->core->name;
  1587. }
  1588. err = dvb_register(dev);
  1589. if (err)
  1590. /* frontends/adapter de-allocated in dvb_register */
  1591. pr_err("dvb_register failed (err = %d)\n", err);
  1592. return err;
  1593. fail_probe:
  1594. vb2_dvb_dealloc_frontends(&core->dvbdev->frontends);
  1595. fail_core:
  1596. return err;
  1597. }
  1598. static int cx8802_dvb_remove(struct cx8802_driver *drv)
  1599. {
  1600. struct cx88_core *core = drv->core;
  1601. struct cx8802_dev *dev = drv->core->dvbdev;
  1602. dprintk(1, "%s\n", __func__);
  1603. vb2_dvb_unregister_bus(&dev->frontends);
  1604. vp3054_i2c_remove(dev);
  1605. core->gate_ctrl = NULL;
  1606. return 0;
  1607. }
  1608. static struct cx8802_driver cx8802_dvb_driver = {
  1609. .type_id = CX88_MPEG_DVB,
  1610. .hw_access = CX8802_DRVCTL_SHARED,
  1611. .probe = cx8802_dvb_probe,
  1612. .remove = cx8802_dvb_remove,
  1613. .advise_acquire = cx8802_dvb_advise_acquire,
  1614. .advise_release = cx8802_dvb_advise_release,
  1615. };
  1616. static int __init dvb_init(void)
  1617. {
  1618. pr_info("cx2388x dvb driver version %s loaded\n", CX88_VERSION);
  1619. return cx8802_register_driver(&cx8802_dvb_driver);
  1620. }
  1621. static void __exit dvb_fini(void)
  1622. {
  1623. cx8802_unregister_driver(&cx8802_dvb_driver);
  1624. }
  1625. module_init(dvb_init);
  1626. module_exit(dvb_fini);