cx25821-medusa-reg.h 15 KB

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  1. /*
  2. * Driver for the Conexant CX25821 PCIe bridge
  3. *
  4. * Copyright (C) 2009 Conexant Systems Inc.
  5. * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. *
  16. * GNU General Public License for more details.
  17. */
  18. #ifndef __MEDUSA_REGISTERS__
  19. #define __MEDUSA_REGISTERS__
  20. /* Serial Slave Registers */
  21. #define HOST_REGISTER1 0x0000
  22. #define HOST_REGISTER2 0x0001
  23. /* Chip Configuration Registers */
  24. #define CHIP_CTRL 0x0100
  25. #define AFE_AB_CTRL 0x0104
  26. #define AFE_CD_CTRL 0x0108
  27. #define AFE_EF_CTRL 0x010C
  28. #define AFE_GH_CTRL 0x0110
  29. #define DENC_AB_CTRL 0x0114
  30. #define BYP_AB_CTRL 0x0118
  31. #define MON_A_CTRL 0x011C
  32. #define DISP_SEQ_A 0x0120
  33. #define DISP_SEQ_B 0x0124
  34. #define DISP_AB_CNT 0x0128
  35. #define DISP_CD_CNT 0x012C
  36. #define DISP_EF_CNT 0x0130
  37. #define DISP_GH_CNT 0x0134
  38. #define DISP_IJ_CNT 0x0138
  39. #define PIN_OE_CTRL 0x013C
  40. #define PIN_SPD_CTRL 0x0140
  41. #define PIN_SPD_CTRL2 0x0144
  42. #define IRQ_STAT_CTRL 0x0148
  43. #define POWER_CTRL_AB 0x014C
  44. #define POWER_CTRL_CD 0x0150
  45. #define POWER_CTRL_EF 0x0154
  46. #define POWER_CTRL_GH 0x0158
  47. #define TUNE_CTRL 0x015C
  48. #define BIAS_CTRL 0x0160
  49. #define AFE_AB_DIAG_CTRL 0x0164
  50. #define AFE_CD_DIAG_CTRL 0x0168
  51. #define AFE_EF_DIAG_CTRL 0x016C
  52. #define AFE_GH_DIAG_CTRL 0x0170
  53. #define PLL_AB_DIAG_CTRL 0x0174
  54. #define PLL_CD_DIAG_CTRL 0x0178
  55. #define PLL_EF_DIAG_CTRL 0x017C
  56. #define PLL_GH_DIAG_CTRL 0x0180
  57. #define TEST_CTRL 0x0184
  58. #define BIST_STAT 0x0188
  59. #define BIST_STAT2 0x018C
  60. #define BIST_VID_PLL_AB_STAT 0x0190
  61. #define BIST_VID_PLL_CD_STAT 0x0194
  62. #define BIST_VID_PLL_EF_STAT 0x0198
  63. #define BIST_VID_PLL_GH_STAT 0x019C
  64. #define DLL_DIAG_CTRL 0x01A0
  65. #define DEV_CH_ID_CTRL 0x01A4
  66. #define ABIST_CTRL_STATUS 0x01A8
  67. #define ABIST_FREQ 0x01AC
  68. #define ABIST_GOERT_SHIFT 0x01B0
  69. #define ABIST_COEF12 0x01B4
  70. #define ABIST_COEF34 0x01B8
  71. #define ABIST_COEF56 0x01BC
  72. #define ABIST_COEF7_SNR 0x01C0
  73. #define ABIST_ADC_CAL 0x01C4
  74. #define ABIST_BIN1_VGA0 0x01C8
  75. #define ABIST_BIN2_VGA1 0x01CC
  76. #define ABIST_BIN3_VGA2 0x01D0
  77. #define ABIST_BIN4_VGA3 0x01D4
  78. #define ABIST_BIN5_VGA4 0x01D8
  79. #define ABIST_BIN6_VGA5 0x01DC
  80. #define ABIST_BIN7_VGA6 0x01E0
  81. #define ABIST_CLAMP_A 0x01E4
  82. #define ABIST_CLAMP_B 0x01E8
  83. #define ABIST_CLAMP_C 0x01EC
  84. #define ABIST_CLAMP_D 0x01F0
  85. #define ABIST_CLAMP_E 0x01F4
  86. #define ABIST_CLAMP_F 0x01F8
  87. /* Digital Video Encoder A Registers */
  88. #define DENC_A_REG_1 0x0200
  89. #define DENC_A_REG_2 0x0204
  90. #define DENC_A_REG_3 0x0208
  91. #define DENC_A_REG_4 0x020C
  92. #define DENC_A_REG_5 0x0210
  93. #define DENC_A_REG_6 0x0214
  94. #define DENC_A_REG_7 0x0218
  95. #define DENC_A_REG_8 0x021C
  96. /* Digital Video Encoder B Registers */
  97. #define DENC_B_REG_1 0x0300
  98. #define DENC_B_REG_2 0x0304
  99. #define DENC_B_REG_3 0x0308
  100. #define DENC_B_REG_4 0x030C
  101. #define DENC_B_REG_5 0x0310
  102. #define DENC_B_REG_6 0x0314
  103. #define DENC_B_REG_7 0x0318
  104. #define DENC_B_REG_8 0x031C
  105. /* Video Decoder A Registers */
  106. #define MODE_CTRL 0x1000
  107. #define OUT_CTRL1 0x1004
  108. #define OUT_CTRL_NS 0x1008
  109. #define GEN_STAT 0x100C
  110. #define INT_STAT_MASK 0x1010
  111. #define LUMA_CTRL 0x1014
  112. #define CHROMA_CTRL 0x1018
  113. #define CRUSH_CTRL 0x101C
  114. #define HORIZ_TIM_CTRL 0x1020
  115. #define VERT_TIM_CTRL 0x1024
  116. #define MISC_TIM_CTRL 0x1028
  117. #define FIELD_COUNT 0x102C
  118. #define HSCALE_CTRL 0x1030
  119. #define VSCALE_CTRL 0x1034
  120. #define MAN_VGA_CTRL 0x1038
  121. #define MAN_AGC_CTRL 0x103C
  122. #define DFE_CTRL1 0x1040
  123. #define DFE_CTRL2 0x1044
  124. #define DFE_CTRL3 0x1048
  125. #define PLL_CTRL 0x104C
  126. #define PLL_CTRL_FAST 0x1050
  127. #define HTL_CTRL 0x1054
  128. #define SRC_CFG 0x1058
  129. #define SC_STEP_SIZE 0x105C
  130. #define SC_CONVERGE_CTRL 0x1060
  131. #define SC_LOOP_CTRL 0x1064
  132. #define COMB_2D_HFS_CFG 0x1068
  133. #define COMB_2D_HFD_CFG 0x106C
  134. #define COMB_2D_LF_CFG 0x1070
  135. #define COMB_2D_BLEND 0x1074
  136. #define COMB_MISC_CTRL 0x1078
  137. #define COMB_FLAT_THRESH_CTRL 0x107C
  138. #define COMB_TEST 0x1080
  139. #define BP_MISC_CTRL 0x1084
  140. #define VCR_DET_CTRL 0x1088
  141. #define NOISE_DET_CTRL 0x108C
  142. #define COMB_FLAT_NOISE_CTRL 0x1090
  143. #define VERSION 0x11F8
  144. #define SOFT_RST_CTRL 0x11FC
  145. /* Video Decoder B Registers */
  146. #define VDEC_B_MODE_CTRL 0x1200
  147. #define VDEC_B_OUT_CTRL1 0x1204
  148. #define VDEC_B_OUT_CTRL_NS 0x1208
  149. #define VDEC_B_GEN_STAT 0x120C
  150. #define VDEC_B_INT_STAT_MASK 0x1210
  151. #define VDEC_B_LUMA_CTRL 0x1214
  152. #define VDEC_B_CHROMA_CTRL 0x1218
  153. #define VDEC_B_CRUSH_CTRL 0x121C
  154. #define VDEC_B_HORIZ_TIM_CTRL 0x1220
  155. #define VDEC_B_VERT_TIM_CTRL 0x1224
  156. #define VDEC_B_MISC_TIM_CTRL 0x1228
  157. #define VDEC_B_FIELD_COUNT 0x122C
  158. #define VDEC_B_HSCALE_CTRL 0x1230
  159. #define VDEC_B_VSCALE_CTRL 0x1234
  160. #define VDEC_B_MAN_VGA_CTRL 0x1238
  161. #define VDEC_B_MAN_AGC_CTRL 0x123C
  162. #define VDEC_B_DFE_CTRL1 0x1240
  163. #define VDEC_B_DFE_CTRL2 0x1244
  164. #define VDEC_B_DFE_CTRL3 0x1248
  165. #define VDEC_B_PLL_CTRL 0x124C
  166. #define VDEC_B_PLL_CTRL_FAST 0x1250
  167. #define VDEC_B_HTL_CTRL 0x1254
  168. #define VDEC_B_SRC_CFG 0x1258
  169. #define VDEC_B_SC_STEP_SIZE 0x125C
  170. #define VDEC_B_SC_CONVERGE_CTRL 0x1260
  171. #define VDEC_B_SC_LOOP_CTRL 0x1264
  172. #define VDEC_B_COMB_2D_HFS_CFG 0x1268
  173. #define VDEC_B_COMB_2D_HFD_CFG 0x126C
  174. #define VDEC_B_COMB_2D_LF_CFG 0x1270
  175. #define VDEC_B_COMB_2D_BLEND 0x1274
  176. #define VDEC_B_COMB_MISC_CTRL 0x1278
  177. #define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C
  178. #define VDEC_B_COMB_TEST 0x1280
  179. #define VDEC_B_BP_MISC_CTRL 0x1284
  180. #define VDEC_B_VCR_DET_CTRL 0x1288
  181. #define VDEC_B_NOISE_DET_CTRL 0x128C
  182. #define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290
  183. #define VDEC_B_VERSION 0x13F8
  184. #define VDEC_B_SOFT_RST_CTRL 0x13FC
  185. /* Video Decoder C Registers */
  186. #define VDEC_C_MODE_CTRL 0x1400
  187. #define VDEC_C_OUT_CTRL1 0x1404
  188. #define VDEC_C_OUT_CTRL_NS 0x1408
  189. #define VDEC_C_GEN_STAT 0x140C
  190. #define VDEC_C_INT_STAT_MASK 0x1410
  191. #define VDEC_C_LUMA_CTRL 0x1414
  192. #define VDEC_C_CHROMA_CTRL 0x1418
  193. #define VDEC_C_CRUSH_CTRL 0x141C
  194. #define VDEC_C_HORIZ_TIM_CTRL 0x1420
  195. #define VDEC_C_VERT_TIM_CTRL 0x1424
  196. #define VDEC_C_MISC_TIM_CTRL 0x1428
  197. #define VDEC_C_FIELD_COUNT 0x142C
  198. #define VDEC_C_HSCALE_CTRL 0x1430
  199. #define VDEC_C_VSCALE_CTRL 0x1434
  200. #define VDEC_C_MAN_VGA_CTRL 0x1438
  201. #define VDEC_C_MAN_AGC_CTRL 0x143C
  202. #define VDEC_C_DFE_CTRL1 0x1440
  203. #define VDEC_C_DFE_CTRL2 0x1444
  204. #define VDEC_C_DFE_CTRL3 0x1448
  205. #define VDEC_C_PLL_CTRL 0x144C
  206. #define VDEC_C_PLL_CTRL_FAST 0x1450
  207. #define VDEC_C_HTL_CTRL 0x1454
  208. #define VDEC_C_SRC_CFG 0x1458
  209. #define VDEC_C_SC_STEP_SIZE 0x145C
  210. #define VDEC_C_SC_CONVERGE_CTRL 0x1460
  211. #define VDEC_C_SC_LOOP_CTRL 0x1464
  212. #define VDEC_C_COMB_2D_HFS_CFG 0x1468
  213. #define VDEC_C_COMB_2D_HFD_CFG 0x146C
  214. #define VDEC_C_COMB_2D_LF_CFG 0x1470
  215. #define VDEC_C_COMB_2D_BLEND 0x1474
  216. #define VDEC_C_COMB_MISC_CTRL 0x1478
  217. #define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C
  218. #define VDEC_C_COMB_TEST 0x1480
  219. #define VDEC_C_BP_MISC_CTRL 0x1484
  220. #define VDEC_C_VCR_DET_CTRL 0x1488
  221. #define VDEC_C_NOISE_DET_CTRL 0x148C
  222. #define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490
  223. #define VDEC_C_VERSION 0x15F8
  224. #define VDEC_C_SOFT_RST_CTRL 0x15FC
  225. /* Video Decoder D Registers */
  226. #define VDEC_D_MODE_CTRL 0x1600
  227. #define VDEC_D_OUT_CTRL1 0x1604
  228. #define VDEC_D_OUT_CTRL_NS 0x1608
  229. #define VDEC_D_GEN_STAT 0x160C
  230. #define VDEC_D_INT_STAT_MASK 0x1610
  231. #define VDEC_D_LUMA_CTRL 0x1614
  232. #define VDEC_D_CHROMA_CTRL 0x1618
  233. #define VDEC_D_CRUSH_CTRL 0x161C
  234. #define VDEC_D_HORIZ_TIM_CTRL 0x1620
  235. #define VDEC_D_VERT_TIM_CTRL 0x1624
  236. #define VDEC_D_MISC_TIM_CTRL 0x1628
  237. #define VDEC_D_FIELD_COUNT 0x162C
  238. #define VDEC_D_HSCALE_CTRL 0x1630
  239. #define VDEC_D_VSCALE_CTRL 0x1634
  240. #define VDEC_D_MAN_VGA_CTRL 0x1638
  241. #define VDEC_D_MAN_AGC_CTRL 0x163C
  242. #define VDEC_D_DFE_CTRL1 0x1640
  243. #define VDEC_D_DFE_CTRL2 0x1644
  244. #define VDEC_D_DFE_CTRL3 0x1648
  245. #define VDEC_D_PLL_CTRL 0x164C
  246. #define VDEC_D_PLL_CTRL_FAST 0x1650
  247. #define VDEC_D_HTL_CTRL 0x1654
  248. #define VDEC_D_SRC_CFG 0x1658
  249. #define VDEC_D_SC_STEP_SIZE 0x165C
  250. #define VDEC_D_SC_CONVERGE_CTRL 0x1660
  251. #define VDEC_D_SC_LOOP_CTRL 0x1664
  252. #define VDEC_D_COMB_2D_HFS_CFG 0x1668
  253. #define VDEC_D_COMB_2D_HFD_CFG 0x166C
  254. #define VDEC_D_COMB_2D_LF_CFG 0x1670
  255. #define VDEC_D_COMB_2D_BLEND 0x1674
  256. #define VDEC_D_COMB_MISC_CTRL 0x1678
  257. #define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C
  258. #define VDEC_D_COMB_TEST 0x1680
  259. #define VDEC_D_BP_MISC_CTRL 0x1684
  260. #define VDEC_D_VCR_DET_CTRL 0x1688
  261. #define VDEC_D_NOISE_DET_CTRL 0x168C
  262. #define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690
  263. #define VDEC_D_VERSION 0x17F8
  264. #define VDEC_D_SOFT_RST_CTRL 0x17FC
  265. /* Video Decoder E Registers */
  266. #define VDEC_E_MODE_CTRL 0x1800
  267. #define VDEC_E_OUT_CTRL1 0x1804
  268. #define VDEC_E_OUT_CTRL_NS 0x1808
  269. #define VDEC_E_GEN_STAT 0x180C
  270. #define VDEC_E_INT_STAT_MASK 0x1810
  271. #define VDEC_E_LUMA_CTRL 0x1814
  272. #define VDEC_E_CHROMA_CTRL 0x1818
  273. #define VDEC_E_CRUSH_CTRL 0x181C
  274. #define VDEC_E_HORIZ_TIM_CTRL 0x1820
  275. #define VDEC_E_VERT_TIM_CTRL 0x1824
  276. #define VDEC_E_MISC_TIM_CTRL 0x1828
  277. #define VDEC_E_FIELD_COUNT 0x182C
  278. #define VDEC_E_HSCALE_CTRL 0x1830
  279. #define VDEC_E_VSCALE_CTRL 0x1834
  280. #define VDEC_E_MAN_VGA_CTRL 0x1838
  281. #define VDEC_E_MAN_AGC_CTRL 0x183C
  282. #define VDEC_E_DFE_CTRL1 0x1840
  283. #define VDEC_E_DFE_CTRL2 0x1844
  284. #define VDEC_E_DFE_CTRL3 0x1848
  285. #define VDEC_E_PLL_CTRL 0x184C
  286. #define VDEC_E_PLL_CTRL_FAST 0x1850
  287. #define VDEC_E_HTL_CTRL 0x1854
  288. #define VDEC_E_SRC_CFG 0x1858
  289. #define VDEC_E_SC_STEP_SIZE 0x185C
  290. #define VDEC_E_SC_CONVERGE_CTRL 0x1860
  291. #define VDEC_E_SC_LOOP_CTRL 0x1864
  292. #define VDEC_E_COMB_2D_HFS_CFG 0x1868
  293. #define VDEC_E_COMB_2D_HFD_CFG 0x186C
  294. #define VDEC_E_COMB_2D_LF_CFG 0x1870
  295. #define VDEC_E_COMB_2D_BLEND 0x1874
  296. #define VDEC_E_COMB_MISC_CTRL 0x1878
  297. #define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C
  298. #define VDEC_E_COMB_TEST 0x1880
  299. #define VDEC_E_BP_MISC_CTRL 0x1884
  300. #define VDEC_E_VCR_DET_CTRL 0x1888
  301. #define VDEC_E_NOISE_DET_CTRL 0x188C
  302. #define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890
  303. #define VDEC_E_VERSION 0x19F8
  304. #define VDEC_E_SOFT_RST_CTRL 0x19FC
  305. /* Video Decoder F Registers */
  306. #define VDEC_F_MODE_CTRL 0x1A00
  307. #define VDEC_F_OUT_CTRL1 0x1A04
  308. #define VDEC_F_OUT_CTRL_NS 0x1A08
  309. #define VDEC_F_GEN_STAT 0x1A0C
  310. #define VDEC_F_INT_STAT_MASK 0x1A10
  311. #define VDEC_F_LUMA_CTRL 0x1A14
  312. #define VDEC_F_CHROMA_CTRL 0x1A18
  313. #define VDEC_F_CRUSH_CTRL 0x1A1C
  314. #define VDEC_F_HORIZ_TIM_CTRL 0x1A20
  315. #define VDEC_F_VERT_TIM_CTRL 0x1A24
  316. #define VDEC_F_MISC_TIM_CTRL 0x1A28
  317. #define VDEC_F_FIELD_COUNT 0x1A2C
  318. #define VDEC_F_HSCALE_CTRL 0x1A30
  319. #define VDEC_F_VSCALE_CTRL 0x1A34
  320. #define VDEC_F_MAN_VGA_CTRL 0x1A38
  321. #define VDEC_F_MAN_AGC_CTRL 0x1A3C
  322. #define VDEC_F_DFE_CTRL1 0x1A40
  323. #define VDEC_F_DFE_CTRL2 0x1A44
  324. #define VDEC_F_DFE_CTRL3 0x1A48
  325. #define VDEC_F_PLL_CTRL 0x1A4C
  326. #define VDEC_F_PLL_CTRL_FAST 0x1A50
  327. #define VDEC_F_HTL_CTRL 0x1A54
  328. #define VDEC_F_SRC_CFG 0x1A58
  329. #define VDEC_F_SC_STEP_SIZE 0x1A5C
  330. #define VDEC_F_SC_CONVERGE_CTRL 0x1A60
  331. #define VDEC_F_SC_LOOP_CTRL 0x1A64
  332. #define VDEC_F_COMB_2D_HFS_CFG 0x1A68
  333. #define VDEC_F_COMB_2D_HFD_CFG 0x1A6C
  334. #define VDEC_F_COMB_2D_LF_CFG 0x1A70
  335. #define VDEC_F_COMB_2D_BLEND 0x1A74
  336. #define VDEC_F_COMB_MISC_CTRL 0x1A78
  337. #define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C
  338. #define VDEC_F_COMB_TEST 0x1A80
  339. #define VDEC_F_BP_MISC_CTRL 0x1A84
  340. #define VDEC_F_VCR_DET_CTRL 0x1A88
  341. #define VDEC_F_NOISE_DET_CTRL 0x1A8C
  342. #define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90
  343. #define VDEC_F_VERSION 0x1BF8
  344. #define VDEC_F_SOFT_RST_CTRL 0x1BFC
  345. /* Video Decoder G Registers */
  346. #define VDEC_G_MODE_CTRL 0x1C00
  347. #define VDEC_G_OUT_CTRL1 0x1C04
  348. #define VDEC_G_OUT_CTRL_NS 0x1C08
  349. #define VDEC_G_GEN_STAT 0x1C0C
  350. #define VDEC_G_INT_STAT_MASK 0x1C10
  351. #define VDEC_G_LUMA_CTRL 0x1C14
  352. #define VDEC_G_CHROMA_CTRL 0x1C18
  353. #define VDEC_G_CRUSH_CTRL 0x1C1C
  354. #define VDEC_G_HORIZ_TIM_CTRL 0x1C20
  355. #define VDEC_G_VERT_TIM_CTRL 0x1C24
  356. #define VDEC_G_MISC_TIM_CTRL 0x1C28
  357. #define VDEC_G_FIELD_COUNT 0x1C2C
  358. #define VDEC_G_HSCALE_CTRL 0x1C30
  359. #define VDEC_G_VSCALE_CTRL 0x1C34
  360. #define VDEC_G_MAN_VGA_CTRL 0x1C38
  361. #define VDEC_G_MAN_AGC_CTRL 0x1C3C
  362. #define VDEC_G_DFE_CTRL1 0x1C40
  363. #define VDEC_G_DFE_CTRL2 0x1C44
  364. #define VDEC_G_DFE_CTRL3 0x1C48
  365. #define VDEC_G_PLL_CTRL 0x1C4C
  366. #define VDEC_G_PLL_CTRL_FAST 0x1C50
  367. #define VDEC_G_HTL_CTRL 0x1C54
  368. #define VDEC_G_SRC_CFG 0x1C58
  369. #define VDEC_G_SC_STEP_SIZE 0x1C5C
  370. #define VDEC_G_SC_CONVERGE_CTRL 0x1C60
  371. #define VDEC_G_SC_LOOP_CTRL 0x1C64
  372. #define VDEC_G_COMB_2D_HFS_CFG 0x1C68
  373. #define VDEC_G_COMB_2D_HFD_CFG 0x1C6C
  374. #define VDEC_G_COMB_2D_LF_CFG 0x1C70
  375. #define VDEC_G_COMB_2D_BLEND 0x1C74
  376. #define VDEC_G_COMB_MISC_CTRL 0x1C78
  377. #define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C
  378. #define VDEC_G_COMB_TEST 0x1C80
  379. #define VDEC_G_BP_MISC_CTRL 0x1C84
  380. #define VDEC_G_VCR_DET_CTRL 0x1C88
  381. #define VDEC_G_NOISE_DET_CTRL 0x1C8C
  382. #define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90
  383. #define VDEC_G_VERSION 0x1DF8
  384. #define VDEC_G_SOFT_RST_CTRL 0x1DFC
  385. /* Video Decoder H Registers */
  386. #define VDEC_H_MODE_CTRL 0x1E00
  387. #define VDEC_H_OUT_CTRL1 0x1E04
  388. #define VDEC_H_OUT_CTRL_NS 0x1E08
  389. #define VDEC_H_GEN_STAT 0x1E0C
  390. #define VDEC_H_INT_STAT_MASK 0x1E1E
  391. #define VDEC_H_LUMA_CTRL 0x1E14
  392. #define VDEC_H_CHROMA_CTRL 0x1E18
  393. #define VDEC_H_CRUSH_CTRL 0x1E1C
  394. #define VDEC_H_HORIZ_TIM_CTRL 0x1E20
  395. #define VDEC_H_VERT_TIM_CTRL 0x1E24
  396. #define VDEC_H_MISC_TIM_CTRL 0x1E28
  397. #define VDEC_H_FIELD_COUNT 0x1E2C
  398. #define VDEC_H_HSCALE_CTRL 0x1E30
  399. #define VDEC_H_VSCALE_CTRL 0x1E34
  400. #define VDEC_H_MAN_VGA_CTRL 0x1E38
  401. #define VDEC_H_MAN_AGC_CTRL 0x1E3C
  402. #define VDEC_H_DFE_CTRL1 0x1E40
  403. #define VDEC_H_DFE_CTRL2 0x1E44
  404. #define VDEC_H_DFE_CTRL3 0x1E48
  405. #define VDEC_H_PLL_CTRL 0x1E4C
  406. #define VDEC_H_PLL_CTRL_FAST 0x1E50
  407. #define VDEC_H_HTL_CTRL 0x1E54
  408. #define VDEC_H_SRC_CFG 0x1E58
  409. #define VDEC_H_SC_STEP_SIZE 0x1E5C
  410. #define VDEC_H_SC_CONVERGE_CTRL 0x1E60
  411. #define VDEC_H_SC_LOOP_CTRL 0x1E64
  412. #define VDEC_H_COMB_2D_HFS_CFG 0x1E68
  413. #define VDEC_H_COMB_2D_HFD_CFG 0x1E6C
  414. #define VDEC_H_COMB_2D_LF_CFG 0x1E70
  415. #define VDEC_H_COMB_2D_BLEND 0x1E74
  416. #define VDEC_H_COMB_MISC_CTRL 0x1E78
  417. #define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C
  418. #define VDEC_H_COMB_TEST 0x1E80
  419. #define VDEC_H_BP_MISC_CTRL 0x1E84
  420. #define VDEC_H_VCR_DET_CTRL 0x1E88
  421. #define VDEC_H_NOISE_DET_CTRL 0x1E8C
  422. #define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90
  423. #define VDEC_H_VERSION 0x1FF8
  424. #define VDEC_H_SOFT_RST_CTRL 0x1FFC
  425. /*****************************************************************************/
  426. /* LUMA_CTRL register fields */
  427. #define VDEC_A_BRITE_CTRL 0x1014
  428. #define VDEC_A_CNTRST_CTRL 0x1015
  429. #define VDEC_A_PEAK_SEL 0x1016
  430. /*****************************************************************************/
  431. /* CHROMA_CTRL register fields */
  432. #define VDEC_A_USAT_CTRL 0x1018
  433. #define VDEC_A_VSAT_CTRL 0x1019
  434. #define VDEC_A_HUE_CTRL 0x101A
  435. #endif