cimax2.c 13 KB

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  1. /*
  2. * cimax2.c
  3. *
  4. * CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card
  5. *
  6. * Copyright (C) 2009 NetUP Inc.
  7. * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
  8. * Copyright (C) 2009 Abylay Ospan <aospan@netup.ru>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. *
  19. * GNU General Public License for more details.
  20. */
  21. #include "cx23885.h"
  22. #include "cimax2.h"
  23. #include <media/dvb_ca_en50221.h>
  24. /* Max transfer size done by I2C transfer functions */
  25. #define MAX_XFER_SIZE 64
  26. /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
  27. bits 31-16
  28. +-----------+
  29. | Reserved |
  30. +-----------+
  31. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
  32. +-------+-------+-------+-------+-------+-------+-------+-------+
  33. | WR# | RD# | | ACK# | ADHI | ADLO | CS1# | CS0# |
  34. +-------+-------+-------+-------+-------+-------+-------+-------+
  35. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
  36. +-------+-------+-------+-------+-------+-------+-------+-------+
  37. | DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
  38. +-------+-------+-------+-------+-------+-------+-------+-------+
  39. ***/
  40. /* MC417 */
  41. #define NETUP_DATA 0x000000ff
  42. #define NETUP_WR 0x00008000
  43. #define NETUP_RD 0x00004000
  44. #define NETUP_ACK 0x00001000
  45. #define NETUP_ADHI 0x00000800
  46. #define NETUP_ADLO 0x00000400
  47. #define NETUP_CS1 0x00000200
  48. #define NETUP_CS0 0x00000100
  49. #define NETUP_EN_ALL 0x00001000
  50. #define NETUP_CTRL_OFF (NETUP_CS1 | NETUP_CS0 | NETUP_WR | NETUP_RD)
  51. #define NETUP_CI_CTL 0x04
  52. #define NETUP_CI_RD 1
  53. #define NETUP_IRQ_DETAM 0x1
  54. #define NETUP_IRQ_IRQAM 0x4
  55. static unsigned int ci_dbg;
  56. module_param(ci_dbg, int, 0644);
  57. MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
  58. static unsigned int ci_irq_enable;
  59. module_param(ci_irq_enable, int, 0644);
  60. MODULE_PARM_DESC(ci_irq_enable, "Enable IRQ from CAM");
  61. #define ci_dbg_print(fmt, args...) \
  62. do { \
  63. if (ci_dbg) \
  64. printk(KERN_DEBUG pr_fmt("%s: " fmt), \
  65. __func__, ##args); \
  66. } while (0)
  67. #define ci_irq_flags() (ci_irq_enable ? NETUP_IRQ_IRQAM : 0)
  68. /* stores all private variables for communication with CI */
  69. struct netup_ci_state {
  70. struct dvb_ca_en50221 ca;
  71. struct mutex ca_mutex;
  72. struct i2c_adapter *i2c_adap;
  73. u8 ci_i2c_addr;
  74. int status;
  75. struct work_struct work;
  76. void *priv;
  77. u8 current_irq_mode;
  78. int current_ci_flag;
  79. unsigned long next_status_checked_time;
  80. };
  81. static int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
  82. u8 *buf, int len)
  83. {
  84. int ret;
  85. struct i2c_msg msg[] = {
  86. {
  87. .addr = addr,
  88. .flags = 0,
  89. .buf = &reg,
  90. .len = 1
  91. }, {
  92. .addr = addr,
  93. .flags = I2C_M_RD,
  94. .buf = buf,
  95. .len = len
  96. }
  97. };
  98. ret = i2c_transfer(i2c_adap, msg, 2);
  99. if (ret != 2) {
  100. ci_dbg_print("%s: i2c read error, Reg = 0x%02x, Status = %d\n",
  101. __func__, reg, ret);
  102. return -1;
  103. }
  104. ci_dbg_print("%s: i2c read Addr=0x%04x, Reg = 0x%02x, data = %02x\n",
  105. __func__, addr, reg, buf[0]);
  106. return 0;
  107. }
  108. static int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
  109. u8 *buf, int len)
  110. {
  111. int ret;
  112. u8 buffer[MAX_XFER_SIZE];
  113. struct i2c_msg msg = {
  114. .addr = addr,
  115. .flags = 0,
  116. .buf = &buffer[0],
  117. .len = len + 1
  118. };
  119. if (1 + len > sizeof(buffer)) {
  120. pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n",
  121. KBUILD_MODNAME, reg, len);
  122. return -EINVAL;
  123. }
  124. buffer[0] = reg;
  125. memcpy(&buffer[1], buf, len);
  126. ret = i2c_transfer(i2c_adap, &msg, 1);
  127. if (ret != 1) {
  128. ci_dbg_print("%s: i2c write error, Reg=[0x%02x], Status=%d\n",
  129. __func__, reg, ret);
  130. return -1;
  131. }
  132. return 0;
  133. }
  134. static int netup_ci_get_mem(struct cx23885_dev *dev)
  135. {
  136. int mem;
  137. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  138. for (;;) {
  139. mem = cx_read(MC417_RWD);
  140. if ((mem & NETUP_ACK) == 0)
  141. break;
  142. if (time_after(jiffies, timeout))
  143. break;
  144. udelay(1);
  145. }
  146. cx_set(MC417_RWD, NETUP_CTRL_OFF);
  147. return mem & 0xff;
  148. }
  149. static int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
  150. u8 flag, u8 read, int addr, u8 data)
  151. {
  152. struct netup_ci_state *state = en50221->data;
  153. struct cx23885_tsport *port = state->priv;
  154. struct cx23885_dev *dev = port->dev;
  155. u8 store;
  156. int mem;
  157. int ret;
  158. if (0 != slot)
  159. return -EINVAL;
  160. if (state->current_ci_flag != flag) {
  161. ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
  162. 0, &store, 1);
  163. if (ret != 0)
  164. return ret;
  165. store &= ~0x0c;
  166. store |= flag;
  167. ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
  168. 0, &store, 1);
  169. if (ret != 0)
  170. return ret;
  171. }
  172. state->current_ci_flag = flag;
  173. mutex_lock(&dev->gpio_lock);
  174. /* write addr */
  175. cx_write(MC417_OEN, NETUP_EN_ALL);
  176. cx_write(MC417_RWD, NETUP_CTRL_OFF |
  177. NETUP_ADLO | (0xff & addr));
  178. cx_clear(MC417_RWD, NETUP_ADLO);
  179. cx_write(MC417_RWD, NETUP_CTRL_OFF |
  180. NETUP_ADHI | (0xff & (addr >> 8)));
  181. cx_clear(MC417_RWD, NETUP_ADHI);
  182. if (read) { /* data in */
  183. cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA);
  184. } else /* data out */
  185. cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
  186. /* choose chip */
  187. cx_clear(MC417_RWD,
  188. (state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1);
  189. /* read/write */
  190. cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR);
  191. mem = netup_ci_get_mem(dev);
  192. mutex_unlock(&dev->gpio_lock);
  193. if (!read)
  194. if (mem < 0)
  195. return -EREMOTEIO;
  196. ci_dbg_print("%s: %s: chipaddr=[0x%x] addr=[0x%02x], %s=%x\n", __func__,
  197. (read) ? "read" : "write", state->ci_i2c_addr, addr,
  198. (flag == NETUP_CI_CTL) ? "ctl" : "mem",
  199. (read) ? mem : data);
  200. if (read)
  201. return mem;
  202. return 0;
  203. }
  204. int netup_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
  205. int slot, int addr)
  206. {
  207. return netup_ci_op_cam(en50221, slot, 0, NETUP_CI_RD, addr, 0);
  208. }
  209. int netup_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
  210. int slot, int addr, u8 data)
  211. {
  212. return netup_ci_op_cam(en50221, slot, 0, 0, addr, data);
  213. }
  214. int netup_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
  215. u8 addr)
  216. {
  217. return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL,
  218. NETUP_CI_RD, addr, 0);
  219. }
  220. int netup_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
  221. u8 addr, u8 data)
  222. {
  223. return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, 0, addr, data);
  224. }
  225. int netup_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
  226. {
  227. struct netup_ci_state *state = en50221->data;
  228. u8 buf = 0x80;
  229. int ret;
  230. if (0 != slot)
  231. return -EINVAL;
  232. udelay(500);
  233. ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
  234. 0, &buf, 1);
  235. if (ret != 0)
  236. return ret;
  237. udelay(500);
  238. buf = 0x00;
  239. ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
  240. 0, &buf, 1);
  241. msleep(1000);
  242. dvb_ca_en50221_camready_irq(&state->ca, 0);
  243. return 0;
  244. }
  245. int netup_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
  246. {
  247. /* not implemented */
  248. return 0;
  249. }
  250. static int netup_ci_set_irq(struct dvb_ca_en50221 *en50221, u8 irq_mode)
  251. {
  252. struct netup_ci_state *state = en50221->data;
  253. int ret;
  254. if (irq_mode == state->current_irq_mode)
  255. return 0;
  256. ci_dbg_print("%s: chipaddr=[0x%x] setting ci IRQ to [0x%x] \n",
  257. __func__, state->ci_i2c_addr, irq_mode);
  258. ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
  259. 0x1b, &irq_mode, 1);
  260. if (ret != 0)
  261. return ret;
  262. state->current_irq_mode = irq_mode;
  263. return 0;
  264. }
  265. int netup_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
  266. {
  267. struct netup_ci_state *state = en50221->data;
  268. u8 buf;
  269. if (0 != slot)
  270. return -EINVAL;
  271. netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
  272. 0, &buf, 1);
  273. buf |= 0x60;
  274. return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
  275. 0, &buf, 1);
  276. }
  277. /* work handler */
  278. static void netup_read_ci_status(struct work_struct *work)
  279. {
  280. struct netup_ci_state *state =
  281. container_of(work, struct netup_ci_state, work);
  282. u8 buf[33];
  283. int ret;
  284. /* CAM module IRQ processing. fast operation */
  285. dvb_ca_en50221_frda_irq(&state->ca, 0);
  286. /* CAM module INSERT/REMOVE processing. slow operation because of i2c
  287. * transfers */
  288. if (time_after(jiffies, state->next_status_checked_time)
  289. || !state->status) {
  290. ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
  291. 0, &buf[0], 33);
  292. state->next_status_checked_time = jiffies
  293. + msecs_to_jiffies(1000);
  294. if (ret != 0)
  295. return;
  296. ci_dbg_print("%s: Slot Status Addr=[0x%04x], Reg=[0x%02x], data=%02x, TS config = %02x\n",
  297. __func__, state->ci_i2c_addr, 0, buf[0], buf[0]);
  298. if (buf[0] & 1)
  299. state->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
  300. DVB_CA_EN50221_POLL_CAM_READY;
  301. else
  302. state->status = 0;
  303. }
  304. }
  305. /* CI irq handler */
  306. int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status)
  307. {
  308. struct cx23885_tsport *port = NULL;
  309. struct netup_ci_state *state = NULL;
  310. ci_dbg_print("%s:\n", __func__);
  311. if (0 == (pci_status & (PCI_MSK_GPIO0 | PCI_MSK_GPIO1)))
  312. return 0;
  313. if (pci_status & PCI_MSK_GPIO0) {
  314. port = &dev->ts1;
  315. state = port->port_priv;
  316. schedule_work(&state->work);
  317. ci_dbg_print("%s: Wakeup CI0\n", __func__);
  318. }
  319. if (pci_status & PCI_MSK_GPIO1) {
  320. port = &dev->ts2;
  321. state = port->port_priv;
  322. schedule_work(&state->work);
  323. ci_dbg_print("%s: Wakeup CI1\n", __func__);
  324. }
  325. return 1;
  326. }
  327. int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
  328. int slot, int open)
  329. {
  330. struct netup_ci_state *state = en50221->data;
  331. if (0 != slot)
  332. return -EINVAL;
  333. netup_ci_set_irq(en50221, open ? (NETUP_IRQ_DETAM | ci_irq_flags())
  334. : NETUP_IRQ_DETAM);
  335. return state->status;
  336. }
  337. int netup_ci_init(struct cx23885_tsport *port)
  338. {
  339. struct netup_ci_state *state;
  340. u8 cimax_init[34] = {
  341. 0x00, /* module A control*/
  342. 0x00, /* auto select mask high A */
  343. 0x00, /* auto select mask low A */
  344. 0x00, /* auto select pattern high A */
  345. 0x00, /* auto select pattern low A */
  346. 0x44, /* memory access time A */
  347. 0x00, /* invert input A */
  348. 0x00, /* RFU */
  349. 0x00, /* RFU */
  350. 0x00, /* module B control*/
  351. 0x00, /* auto select mask high B */
  352. 0x00, /* auto select mask low B */
  353. 0x00, /* auto select pattern high B */
  354. 0x00, /* auto select pattern low B */
  355. 0x44, /* memory access time B */
  356. 0x00, /* invert input B */
  357. 0x00, /* RFU */
  358. 0x00, /* RFU */
  359. 0x00, /* auto select mask high Ext */
  360. 0x00, /* auto select mask low Ext */
  361. 0x00, /* auto select pattern high Ext */
  362. 0x00, /* auto select pattern low Ext */
  363. 0x00, /* RFU */
  364. 0x02, /* destination - module A */
  365. 0x01, /* power on (use it like store place) */
  366. 0x00, /* RFU */
  367. 0x00, /* int status read only */
  368. ci_irq_flags() | NETUP_IRQ_DETAM, /* DETAM, IRQAM unmasked */
  369. 0x05, /* EXTINT=active-high, INT=push-pull */
  370. 0x00, /* USCG1 */
  371. 0x04, /* ack active low */
  372. 0x00, /* LOCK = 0 */
  373. 0x33, /* serial mode, rising in, rising out, MSB first*/
  374. 0x31, /* synchronization */
  375. };
  376. int ret;
  377. ci_dbg_print("%s\n", __func__);
  378. state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL);
  379. if (!state) {
  380. ci_dbg_print("%s: Unable create CI structure!\n", __func__);
  381. ret = -ENOMEM;
  382. goto err;
  383. }
  384. port->port_priv = state;
  385. switch (port->nr) {
  386. case 1:
  387. state->ci_i2c_addr = 0x40;
  388. break;
  389. case 2:
  390. state->ci_i2c_addr = 0x41;
  391. break;
  392. }
  393. state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap;
  394. state->ca.owner = THIS_MODULE;
  395. state->ca.read_attribute_mem = netup_ci_read_attribute_mem;
  396. state->ca.write_attribute_mem = netup_ci_write_attribute_mem;
  397. state->ca.read_cam_control = netup_ci_read_cam_ctl;
  398. state->ca.write_cam_control = netup_ci_write_cam_ctl;
  399. state->ca.slot_reset = netup_ci_slot_reset;
  400. state->ca.slot_shutdown = netup_ci_slot_shutdown;
  401. state->ca.slot_ts_enable = netup_ci_slot_ts_ctl;
  402. state->ca.poll_slot_status = netup_poll_ci_slot_status;
  403. state->ca.data = state;
  404. state->priv = port;
  405. state->current_irq_mode = ci_irq_flags() | NETUP_IRQ_DETAM;
  406. ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
  407. 0, &cimax_init[0], 34);
  408. /* lock registers */
  409. ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
  410. 0x1f, &cimax_init[0x18], 1);
  411. /* power on slots */
  412. ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
  413. 0x18, &cimax_init[0x18], 1);
  414. if (0 != ret)
  415. goto err;
  416. ret = dvb_ca_en50221_init(&port->frontends.adapter,
  417. &state->ca,
  418. /* flags */ 0,
  419. /* n_slots */ 1);
  420. if (0 != ret)
  421. goto err;
  422. INIT_WORK(&state->work, netup_read_ci_status);
  423. schedule_work(&state->work);
  424. ci_dbg_print("%s: CI initialized!\n", __func__);
  425. return 0;
  426. err:
  427. ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
  428. kfree(state);
  429. return ret;
  430. }
  431. void netup_ci_exit(struct cx23885_tsport *port)
  432. {
  433. struct netup_ci_state *state;
  434. if (NULL == port)
  435. return;
  436. state = (struct netup_ci_state *)port->port_priv;
  437. if (NULL == state)
  438. return;
  439. if (NULL == state->ca.data)
  440. return;
  441. dvb_ca_en50221_release(&state->ca);
  442. kfree(state);
  443. }