mt9t001.c 27 KB

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  1. /*
  2. * Driver for MT9T001 CMOS Image Sensor from Aptina (Micron)
  3. *
  4. * Copyright (C) 2010-2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  5. *
  6. * Based on the MT9M001 driver,
  7. *
  8. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/i2c.h>
  16. #include <linux/log2.h>
  17. #include <linux/module.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/slab.h>
  20. #include <linux/videodev2.h>
  21. #include <linux/v4l2-mediabus.h>
  22. #include <media/i2c/mt9t001.h>
  23. #include <media/v4l2-ctrls.h>
  24. #include <media/v4l2-device.h>
  25. #include <media/v4l2-subdev.h>
  26. #define MT9T001_PIXEL_ARRAY_HEIGHT 1568
  27. #define MT9T001_PIXEL_ARRAY_WIDTH 2112
  28. #define MT9T001_CHIP_VERSION 0x00
  29. #define MT9T001_CHIP_ID 0x1621
  30. #define MT9T001_ROW_START 0x01
  31. #define MT9T001_ROW_START_MIN 0
  32. #define MT9T001_ROW_START_DEF 20
  33. #define MT9T001_ROW_START_MAX 1534
  34. #define MT9T001_COLUMN_START 0x02
  35. #define MT9T001_COLUMN_START_MIN 0
  36. #define MT9T001_COLUMN_START_DEF 32
  37. #define MT9T001_COLUMN_START_MAX 2046
  38. #define MT9T001_WINDOW_HEIGHT 0x03
  39. #define MT9T001_WINDOW_HEIGHT_MIN 1
  40. #define MT9T001_WINDOW_HEIGHT_DEF 1535
  41. #define MT9T001_WINDOW_HEIGHT_MAX 1567
  42. #define MT9T001_WINDOW_WIDTH 0x04
  43. #define MT9T001_WINDOW_WIDTH_MIN 1
  44. #define MT9T001_WINDOW_WIDTH_DEF 2047
  45. #define MT9T001_WINDOW_WIDTH_MAX 2111
  46. #define MT9T001_HORIZONTAL_BLANKING 0x05
  47. #define MT9T001_HORIZONTAL_BLANKING_MIN 21
  48. #define MT9T001_HORIZONTAL_BLANKING_MAX 1023
  49. #define MT9T001_VERTICAL_BLANKING 0x06
  50. #define MT9T001_VERTICAL_BLANKING_MIN 3
  51. #define MT9T001_VERTICAL_BLANKING_MAX 1023
  52. #define MT9T001_OUTPUT_CONTROL 0x07
  53. #define MT9T001_OUTPUT_CONTROL_SYNC (1 << 0)
  54. #define MT9T001_OUTPUT_CONTROL_CHIP_ENABLE (1 << 1)
  55. #define MT9T001_OUTPUT_CONTROL_TEST_DATA (1 << 6)
  56. #define MT9T001_OUTPUT_CONTROL_DEF 0x0002
  57. #define MT9T001_SHUTTER_WIDTH_HIGH 0x08
  58. #define MT9T001_SHUTTER_WIDTH_LOW 0x09
  59. #define MT9T001_SHUTTER_WIDTH_MIN 1
  60. #define MT9T001_SHUTTER_WIDTH_DEF 1561
  61. #define MT9T001_SHUTTER_WIDTH_MAX (1024 * 1024)
  62. #define MT9T001_PIXEL_CLOCK 0x0a
  63. #define MT9T001_PIXEL_CLOCK_INVERT (1 << 15)
  64. #define MT9T001_PIXEL_CLOCK_SHIFT_MASK (7 << 8)
  65. #define MT9T001_PIXEL_CLOCK_SHIFT_SHIFT 8
  66. #define MT9T001_PIXEL_CLOCK_DIVIDE_MASK (0x7f << 0)
  67. #define MT9T001_FRAME_RESTART 0x0b
  68. #define MT9T001_SHUTTER_DELAY 0x0c
  69. #define MT9T001_SHUTTER_DELAY_MAX 2047
  70. #define MT9T001_RESET 0x0d
  71. #define MT9T001_READ_MODE1 0x1e
  72. #define MT9T001_READ_MODE_SNAPSHOT (1 << 8)
  73. #define MT9T001_READ_MODE_STROBE_ENABLE (1 << 9)
  74. #define MT9T001_READ_MODE_STROBE_WIDTH (1 << 10)
  75. #define MT9T001_READ_MODE_STROBE_OVERRIDE (1 << 11)
  76. #define MT9T001_READ_MODE2 0x20
  77. #define MT9T001_READ_MODE_BAD_FRAMES (1 << 0)
  78. #define MT9T001_READ_MODE_LINE_VALID_CONTINUOUS (1 << 9)
  79. #define MT9T001_READ_MODE_LINE_VALID_FRAME (1 << 10)
  80. #define MT9T001_READ_MODE3 0x21
  81. #define MT9T001_READ_MODE_GLOBAL_RESET (1 << 0)
  82. #define MT9T001_READ_MODE_GHST_CTL (1 << 1)
  83. #define MT9T001_ROW_ADDRESS_MODE 0x22
  84. #define MT9T001_ROW_SKIP_MASK (7 << 0)
  85. #define MT9T001_ROW_BIN_MASK (3 << 3)
  86. #define MT9T001_ROW_BIN_SHIFT 3
  87. #define MT9T001_COLUMN_ADDRESS_MODE 0x23
  88. #define MT9T001_COLUMN_SKIP_MASK (7 << 0)
  89. #define MT9T001_COLUMN_BIN_MASK (3 << 3)
  90. #define MT9T001_COLUMN_BIN_SHIFT 3
  91. #define MT9T001_GREEN1_GAIN 0x2b
  92. #define MT9T001_BLUE_GAIN 0x2c
  93. #define MT9T001_RED_GAIN 0x2d
  94. #define MT9T001_GREEN2_GAIN 0x2e
  95. #define MT9T001_TEST_DATA 0x32
  96. #define MT9T001_GLOBAL_GAIN 0x35
  97. #define MT9T001_GLOBAL_GAIN_MIN 8
  98. #define MT9T001_GLOBAL_GAIN_MAX 1024
  99. #define MT9T001_BLACK_LEVEL 0x49
  100. #define MT9T001_ROW_BLACK_DEFAULT_OFFSET 0x4b
  101. #define MT9T001_BLC_DELTA_THRESHOLDS 0x5d
  102. #define MT9T001_CAL_THRESHOLDS 0x5f
  103. #define MT9T001_GREEN1_OFFSET 0x60
  104. #define MT9T001_GREEN2_OFFSET 0x61
  105. #define MT9T001_BLACK_LEVEL_CALIBRATION 0x62
  106. #define MT9T001_BLACK_LEVEL_OVERRIDE (1 << 0)
  107. #define MT9T001_BLACK_LEVEL_DISABLE_OFFSET (1 << 1)
  108. #define MT9T001_BLACK_LEVEL_RECALCULATE (1 << 12)
  109. #define MT9T001_BLACK_LEVEL_LOCK_RED_BLUE (1 << 13)
  110. #define MT9T001_BLACK_LEVEL_LOCK_GREEN (1 << 14)
  111. #define MT9T001_RED_OFFSET 0x63
  112. #define MT9T001_BLUE_OFFSET 0x64
  113. struct mt9t001 {
  114. struct v4l2_subdev subdev;
  115. struct media_pad pad;
  116. struct clk *clk;
  117. struct regulator_bulk_data regulators[2];
  118. struct mutex power_lock; /* lock to protect power_count */
  119. int power_count;
  120. struct v4l2_mbus_framefmt format;
  121. struct v4l2_rect crop;
  122. struct v4l2_ctrl_handler ctrls;
  123. struct v4l2_ctrl *gains[4];
  124. u16 output_control;
  125. u16 black_level;
  126. };
  127. static inline struct mt9t001 *to_mt9t001(struct v4l2_subdev *sd)
  128. {
  129. return container_of(sd, struct mt9t001, subdev);
  130. }
  131. static int mt9t001_read(struct i2c_client *client, u8 reg)
  132. {
  133. return i2c_smbus_read_word_swapped(client, reg);
  134. }
  135. static int mt9t001_write(struct i2c_client *client, u8 reg, u16 data)
  136. {
  137. return i2c_smbus_write_word_swapped(client, reg, data);
  138. }
  139. static int mt9t001_set_output_control(struct mt9t001 *mt9t001, u16 clear,
  140. u16 set)
  141. {
  142. struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
  143. u16 value = (mt9t001->output_control & ~clear) | set;
  144. int ret;
  145. if (value == mt9t001->output_control)
  146. return 0;
  147. ret = mt9t001_write(client, MT9T001_OUTPUT_CONTROL, value);
  148. if (ret < 0)
  149. return ret;
  150. mt9t001->output_control = value;
  151. return 0;
  152. }
  153. static int mt9t001_reset(struct mt9t001 *mt9t001)
  154. {
  155. struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
  156. int ret;
  157. /* Reset the chip and stop data read out */
  158. ret = mt9t001_write(client, MT9T001_RESET, 1);
  159. if (ret < 0)
  160. return ret;
  161. ret = mt9t001_write(client, MT9T001_RESET, 0);
  162. if (ret < 0)
  163. return ret;
  164. mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF;
  165. return mt9t001_set_output_control(mt9t001,
  166. MT9T001_OUTPUT_CONTROL_CHIP_ENABLE,
  167. 0);
  168. }
  169. static int mt9t001_power_on(struct mt9t001 *mt9t001)
  170. {
  171. int ret;
  172. /* Bring up the supplies */
  173. ret = regulator_bulk_enable(ARRAY_SIZE(mt9t001->regulators),
  174. mt9t001->regulators);
  175. if (ret < 0)
  176. return ret;
  177. /* Enable clock */
  178. ret = clk_prepare_enable(mt9t001->clk);
  179. if (ret < 0)
  180. regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators),
  181. mt9t001->regulators);
  182. return ret;
  183. }
  184. static void mt9t001_power_off(struct mt9t001 *mt9t001)
  185. {
  186. regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators),
  187. mt9t001->regulators);
  188. clk_disable_unprepare(mt9t001->clk);
  189. }
  190. static int __mt9t001_set_power(struct mt9t001 *mt9t001, bool on)
  191. {
  192. struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
  193. int ret;
  194. if (!on) {
  195. mt9t001_power_off(mt9t001);
  196. return 0;
  197. }
  198. ret = mt9t001_power_on(mt9t001);
  199. if (ret < 0)
  200. return ret;
  201. ret = mt9t001_reset(mt9t001);
  202. if (ret < 0) {
  203. dev_err(&client->dev, "Failed to reset the camera\n");
  204. goto e_power;
  205. }
  206. ret = v4l2_ctrl_handler_setup(&mt9t001->ctrls);
  207. if (ret < 0) {
  208. dev_err(&client->dev, "Failed to set up control handlers\n");
  209. goto e_power;
  210. }
  211. return 0;
  212. e_power:
  213. mt9t001_power_off(mt9t001);
  214. return ret;
  215. }
  216. /* -----------------------------------------------------------------------------
  217. * V4L2 subdev video operations
  218. */
  219. static struct v4l2_mbus_framefmt *
  220. __mt9t001_get_pad_format(struct mt9t001 *mt9t001, struct v4l2_subdev_pad_config *cfg,
  221. unsigned int pad, enum v4l2_subdev_format_whence which)
  222. {
  223. switch (which) {
  224. case V4L2_SUBDEV_FORMAT_TRY:
  225. return v4l2_subdev_get_try_format(&mt9t001->subdev, cfg, pad);
  226. case V4L2_SUBDEV_FORMAT_ACTIVE:
  227. return &mt9t001->format;
  228. default:
  229. return NULL;
  230. }
  231. }
  232. static struct v4l2_rect *
  233. __mt9t001_get_pad_crop(struct mt9t001 *mt9t001, struct v4l2_subdev_pad_config *cfg,
  234. unsigned int pad, enum v4l2_subdev_format_whence which)
  235. {
  236. switch (which) {
  237. case V4L2_SUBDEV_FORMAT_TRY:
  238. return v4l2_subdev_get_try_crop(&mt9t001->subdev, cfg, pad);
  239. case V4L2_SUBDEV_FORMAT_ACTIVE:
  240. return &mt9t001->crop;
  241. default:
  242. return NULL;
  243. }
  244. }
  245. static int mt9t001_s_stream(struct v4l2_subdev *subdev, int enable)
  246. {
  247. const u16 mode = MT9T001_OUTPUT_CONTROL_CHIP_ENABLE;
  248. struct i2c_client *client = v4l2_get_subdevdata(subdev);
  249. struct mt9t001_platform_data *pdata = client->dev.platform_data;
  250. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  251. struct v4l2_mbus_framefmt *format = &mt9t001->format;
  252. struct v4l2_rect *crop = &mt9t001->crop;
  253. unsigned int hratio;
  254. unsigned int vratio;
  255. int ret;
  256. if (!enable)
  257. return mt9t001_set_output_control(mt9t001, mode, 0);
  258. /* Configure the pixel clock polarity */
  259. if (pdata->clk_pol) {
  260. ret = mt9t001_write(client, MT9T001_PIXEL_CLOCK,
  261. MT9T001_PIXEL_CLOCK_INVERT);
  262. if (ret < 0)
  263. return ret;
  264. }
  265. /* Configure the window size and row/column bin */
  266. hratio = DIV_ROUND_CLOSEST(crop->width, format->width);
  267. vratio = DIV_ROUND_CLOSEST(crop->height, format->height);
  268. ret = mt9t001_write(client, MT9T001_ROW_ADDRESS_MODE, hratio - 1);
  269. if (ret < 0)
  270. return ret;
  271. ret = mt9t001_write(client, MT9T001_COLUMN_ADDRESS_MODE, vratio - 1);
  272. if (ret < 0)
  273. return ret;
  274. ret = mt9t001_write(client, MT9T001_COLUMN_START, crop->left);
  275. if (ret < 0)
  276. return ret;
  277. ret = mt9t001_write(client, MT9T001_ROW_START, crop->top);
  278. if (ret < 0)
  279. return ret;
  280. ret = mt9t001_write(client, MT9T001_WINDOW_WIDTH, crop->width - 1);
  281. if (ret < 0)
  282. return ret;
  283. ret = mt9t001_write(client, MT9T001_WINDOW_HEIGHT, crop->height - 1);
  284. if (ret < 0)
  285. return ret;
  286. /* Switch to master "normal" mode */
  287. return mt9t001_set_output_control(mt9t001, 0, mode);
  288. }
  289. static int mt9t001_enum_mbus_code(struct v4l2_subdev *subdev,
  290. struct v4l2_subdev_pad_config *cfg,
  291. struct v4l2_subdev_mbus_code_enum *code)
  292. {
  293. if (code->index > 0)
  294. return -EINVAL;
  295. code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
  296. return 0;
  297. }
  298. static int mt9t001_enum_frame_size(struct v4l2_subdev *subdev,
  299. struct v4l2_subdev_pad_config *cfg,
  300. struct v4l2_subdev_frame_size_enum *fse)
  301. {
  302. if (fse->index >= 8 || fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
  303. return -EINVAL;
  304. fse->min_width = (MT9T001_WINDOW_WIDTH_DEF + 1) / fse->index;
  305. fse->max_width = fse->min_width;
  306. fse->min_height = (MT9T001_WINDOW_HEIGHT_DEF + 1) / fse->index;
  307. fse->max_height = fse->min_height;
  308. return 0;
  309. }
  310. static int mt9t001_get_format(struct v4l2_subdev *subdev,
  311. struct v4l2_subdev_pad_config *cfg,
  312. struct v4l2_subdev_format *format)
  313. {
  314. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  315. format->format = *__mt9t001_get_pad_format(mt9t001, cfg, format->pad,
  316. format->which);
  317. return 0;
  318. }
  319. static int mt9t001_set_format(struct v4l2_subdev *subdev,
  320. struct v4l2_subdev_pad_config *cfg,
  321. struct v4l2_subdev_format *format)
  322. {
  323. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  324. struct v4l2_mbus_framefmt *__format;
  325. struct v4l2_rect *__crop;
  326. unsigned int width;
  327. unsigned int height;
  328. unsigned int hratio;
  329. unsigned int vratio;
  330. __crop = __mt9t001_get_pad_crop(mt9t001, cfg, format->pad,
  331. format->which);
  332. /* Clamp the width and height to avoid dividing by zero. */
  333. width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
  334. max_t(unsigned int, __crop->width / 8,
  335. MT9T001_WINDOW_HEIGHT_MIN + 1),
  336. __crop->width);
  337. height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
  338. max_t(unsigned int, __crop->height / 8,
  339. MT9T001_WINDOW_HEIGHT_MIN + 1),
  340. __crop->height);
  341. hratio = DIV_ROUND_CLOSEST(__crop->width, width);
  342. vratio = DIV_ROUND_CLOSEST(__crop->height, height);
  343. __format = __mt9t001_get_pad_format(mt9t001, cfg, format->pad,
  344. format->which);
  345. __format->width = __crop->width / hratio;
  346. __format->height = __crop->height / vratio;
  347. format->format = *__format;
  348. return 0;
  349. }
  350. static int mt9t001_get_selection(struct v4l2_subdev *subdev,
  351. struct v4l2_subdev_pad_config *cfg,
  352. struct v4l2_subdev_selection *sel)
  353. {
  354. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  355. if (sel->target != V4L2_SEL_TGT_CROP)
  356. return -EINVAL;
  357. sel->r = *__mt9t001_get_pad_crop(mt9t001, cfg, sel->pad, sel->which);
  358. return 0;
  359. }
  360. static int mt9t001_set_selection(struct v4l2_subdev *subdev,
  361. struct v4l2_subdev_pad_config *cfg,
  362. struct v4l2_subdev_selection *sel)
  363. {
  364. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  365. struct v4l2_mbus_framefmt *__format;
  366. struct v4l2_rect *__crop;
  367. struct v4l2_rect rect;
  368. if (sel->target != V4L2_SEL_TGT_CROP)
  369. return -EINVAL;
  370. /* Clamp the crop rectangle boundaries and align them to a multiple of 2
  371. * pixels.
  372. */
  373. rect.left = clamp(ALIGN(sel->r.left, 2),
  374. MT9T001_COLUMN_START_MIN,
  375. MT9T001_COLUMN_START_MAX);
  376. rect.top = clamp(ALIGN(sel->r.top, 2),
  377. MT9T001_ROW_START_MIN,
  378. MT9T001_ROW_START_MAX);
  379. rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
  380. MT9T001_WINDOW_WIDTH_MIN + 1,
  381. MT9T001_WINDOW_WIDTH_MAX + 1);
  382. rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
  383. MT9T001_WINDOW_HEIGHT_MIN + 1,
  384. MT9T001_WINDOW_HEIGHT_MAX + 1);
  385. rect.width = min_t(unsigned int, rect.width,
  386. MT9T001_PIXEL_ARRAY_WIDTH - rect.left);
  387. rect.height = min_t(unsigned int, rect.height,
  388. MT9T001_PIXEL_ARRAY_HEIGHT - rect.top);
  389. __crop = __mt9t001_get_pad_crop(mt9t001, cfg, sel->pad, sel->which);
  390. if (rect.width != __crop->width || rect.height != __crop->height) {
  391. /* Reset the output image size if the crop rectangle size has
  392. * been modified.
  393. */
  394. __format = __mt9t001_get_pad_format(mt9t001, cfg, sel->pad,
  395. sel->which);
  396. __format->width = rect.width;
  397. __format->height = rect.height;
  398. }
  399. *__crop = rect;
  400. sel->r = rect;
  401. return 0;
  402. }
  403. /* -----------------------------------------------------------------------------
  404. * V4L2 subdev control operations
  405. */
  406. #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
  407. #define V4L2_CID_BLACK_LEVEL_AUTO (V4L2_CID_USER_BASE | 0x1002)
  408. #define V4L2_CID_BLACK_LEVEL_OFFSET (V4L2_CID_USER_BASE | 0x1003)
  409. #define V4L2_CID_BLACK_LEVEL_CALIBRATE (V4L2_CID_USER_BASE | 0x1004)
  410. #define V4L2_CID_GAIN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1001)
  411. #define V4L2_CID_GAIN_GREEN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1002)
  412. #define V4L2_CID_GAIN_GREEN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1003)
  413. #define V4L2_CID_GAIN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1004)
  414. static u16 mt9t001_gain_value(s32 *gain)
  415. {
  416. /* Gain is controlled by 2 analog stages and a digital stage. Valid
  417. * values for the 3 stages are
  418. *
  419. * Stage Min Max Step
  420. * ------------------------------------------
  421. * First analog stage x1 x2 1
  422. * Second analog stage x1 x4 0.125
  423. * Digital stage x1 x16 0.125
  424. *
  425. * To minimize noise, the gain stages should be used in the second
  426. * analog stage, first analog stage, digital stage order. Gain from a
  427. * previous stage should be pushed to its maximum value before the next
  428. * stage is used.
  429. */
  430. if (*gain <= 32)
  431. return *gain;
  432. if (*gain <= 64) {
  433. *gain &= ~1;
  434. return (1 << 6) | (*gain >> 1);
  435. }
  436. *gain &= ~7;
  437. return ((*gain - 64) << 5) | (1 << 6) | 32;
  438. }
  439. static int mt9t001_ctrl_freeze(struct mt9t001 *mt9t001, bool freeze)
  440. {
  441. return mt9t001_set_output_control(mt9t001,
  442. freeze ? 0 : MT9T001_OUTPUT_CONTROL_SYNC,
  443. freeze ? MT9T001_OUTPUT_CONTROL_SYNC : 0);
  444. }
  445. static int mt9t001_s_ctrl(struct v4l2_ctrl *ctrl)
  446. {
  447. static const u8 gains[4] = {
  448. MT9T001_RED_GAIN, MT9T001_GREEN1_GAIN,
  449. MT9T001_GREEN2_GAIN, MT9T001_BLUE_GAIN
  450. };
  451. struct mt9t001 *mt9t001 =
  452. container_of(ctrl->handler, struct mt9t001, ctrls);
  453. struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
  454. unsigned int count;
  455. unsigned int i;
  456. u16 value;
  457. int ret;
  458. switch (ctrl->id) {
  459. case V4L2_CID_GAIN_RED:
  460. case V4L2_CID_GAIN_GREEN_RED:
  461. case V4L2_CID_GAIN_GREEN_BLUE:
  462. case V4L2_CID_GAIN_BLUE:
  463. /* Disable control updates if more than one control has changed
  464. * in the cluster.
  465. */
  466. for (i = 0, count = 0; i < 4; ++i) {
  467. struct v4l2_ctrl *gain = mt9t001->gains[i];
  468. if (gain->val != gain->cur.val)
  469. count++;
  470. }
  471. if (count > 1) {
  472. ret = mt9t001_ctrl_freeze(mt9t001, true);
  473. if (ret < 0)
  474. return ret;
  475. }
  476. /* Update the gain controls. */
  477. for (i = 0; i < 4; ++i) {
  478. struct v4l2_ctrl *gain = mt9t001->gains[i];
  479. if (gain->val == gain->cur.val)
  480. continue;
  481. value = mt9t001_gain_value(&gain->val);
  482. ret = mt9t001_write(client, gains[i], value);
  483. if (ret < 0) {
  484. mt9t001_ctrl_freeze(mt9t001, false);
  485. return ret;
  486. }
  487. }
  488. /* Enable control updates. */
  489. if (count > 1) {
  490. ret = mt9t001_ctrl_freeze(mt9t001, false);
  491. if (ret < 0)
  492. return ret;
  493. }
  494. break;
  495. case V4L2_CID_EXPOSURE:
  496. ret = mt9t001_write(client, MT9T001_SHUTTER_WIDTH_LOW,
  497. ctrl->val & 0xffff);
  498. if (ret < 0)
  499. return ret;
  500. return mt9t001_write(client, MT9T001_SHUTTER_WIDTH_HIGH,
  501. ctrl->val >> 16);
  502. case V4L2_CID_TEST_PATTERN:
  503. return mt9t001_set_output_control(mt9t001,
  504. ctrl->val ? 0 : MT9T001_OUTPUT_CONTROL_TEST_DATA,
  505. ctrl->val ? MT9T001_OUTPUT_CONTROL_TEST_DATA : 0);
  506. case V4L2_CID_TEST_PATTERN_COLOR:
  507. return mt9t001_write(client, MT9T001_TEST_DATA, ctrl->val << 2);
  508. case V4L2_CID_BLACK_LEVEL_AUTO:
  509. value = ctrl->val ? 0 : MT9T001_BLACK_LEVEL_OVERRIDE;
  510. ret = mt9t001_write(client, MT9T001_BLACK_LEVEL_CALIBRATION,
  511. value);
  512. if (ret < 0)
  513. return ret;
  514. mt9t001->black_level = value;
  515. break;
  516. case V4L2_CID_BLACK_LEVEL_OFFSET:
  517. ret = mt9t001_write(client, MT9T001_GREEN1_OFFSET, ctrl->val);
  518. if (ret < 0)
  519. return ret;
  520. ret = mt9t001_write(client, MT9T001_GREEN2_OFFSET, ctrl->val);
  521. if (ret < 0)
  522. return ret;
  523. ret = mt9t001_write(client, MT9T001_RED_OFFSET, ctrl->val);
  524. if (ret < 0)
  525. return ret;
  526. return mt9t001_write(client, MT9T001_BLUE_OFFSET, ctrl->val);
  527. case V4L2_CID_BLACK_LEVEL_CALIBRATE:
  528. return mt9t001_write(client, MT9T001_BLACK_LEVEL_CALIBRATION,
  529. MT9T001_BLACK_LEVEL_RECALCULATE |
  530. mt9t001->black_level);
  531. }
  532. return 0;
  533. }
  534. static const struct v4l2_ctrl_ops mt9t001_ctrl_ops = {
  535. .s_ctrl = mt9t001_s_ctrl,
  536. };
  537. static const char * const mt9t001_test_pattern_menu[] = {
  538. "Disabled",
  539. "Enabled",
  540. };
  541. static const struct v4l2_ctrl_config mt9t001_ctrls[] = {
  542. {
  543. .ops = &mt9t001_ctrl_ops,
  544. .id = V4L2_CID_TEST_PATTERN_COLOR,
  545. .type = V4L2_CTRL_TYPE_INTEGER,
  546. .name = "Test Pattern Color",
  547. .min = 0,
  548. .max = 1023,
  549. .step = 1,
  550. .def = 0,
  551. .flags = 0,
  552. }, {
  553. .ops = &mt9t001_ctrl_ops,
  554. .id = V4L2_CID_BLACK_LEVEL_AUTO,
  555. .type = V4L2_CTRL_TYPE_BOOLEAN,
  556. .name = "Black Level, Auto",
  557. .min = 0,
  558. .max = 1,
  559. .step = 1,
  560. .def = 1,
  561. .flags = 0,
  562. }, {
  563. .ops = &mt9t001_ctrl_ops,
  564. .id = V4L2_CID_BLACK_LEVEL_OFFSET,
  565. .type = V4L2_CTRL_TYPE_INTEGER,
  566. .name = "Black Level, Offset",
  567. .min = -256,
  568. .max = 255,
  569. .step = 1,
  570. .def = 32,
  571. .flags = 0,
  572. }, {
  573. .ops = &mt9t001_ctrl_ops,
  574. .id = V4L2_CID_BLACK_LEVEL_CALIBRATE,
  575. .type = V4L2_CTRL_TYPE_BUTTON,
  576. .name = "Black Level, Calibrate",
  577. .min = 0,
  578. .max = 0,
  579. .step = 0,
  580. .def = 0,
  581. .flags = V4L2_CTRL_FLAG_WRITE_ONLY,
  582. },
  583. };
  584. static const struct v4l2_ctrl_config mt9t001_gains[] = {
  585. {
  586. .ops = &mt9t001_ctrl_ops,
  587. .id = V4L2_CID_GAIN_RED,
  588. .type = V4L2_CTRL_TYPE_INTEGER,
  589. .name = "Gain, Red",
  590. .min = MT9T001_GLOBAL_GAIN_MIN,
  591. .max = MT9T001_GLOBAL_GAIN_MAX,
  592. .step = 1,
  593. .def = MT9T001_GLOBAL_GAIN_MIN,
  594. .flags = 0,
  595. }, {
  596. .ops = &mt9t001_ctrl_ops,
  597. .id = V4L2_CID_GAIN_GREEN_RED,
  598. .type = V4L2_CTRL_TYPE_INTEGER,
  599. .name = "Gain, Green (R)",
  600. .min = MT9T001_GLOBAL_GAIN_MIN,
  601. .max = MT9T001_GLOBAL_GAIN_MAX,
  602. .step = 1,
  603. .def = MT9T001_GLOBAL_GAIN_MIN,
  604. .flags = 0,
  605. }, {
  606. .ops = &mt9t001_ctrl_ops,
  607. .id = V4L2_CID_GAIN_GREEN_BLUE,
  608. .type = V4L2_CTRL_TYPE_INTEGER,
  609. .name = "Gain, Green (B)",
  610. .min = MT9T001_GLOBAL_GAIN_MIN,
  611. .max = MT9T001_GLOBAL_GAIN_MAX,
  612. .step = 1,
  613. .def = MT9T001_GLOBAL_GAIN_MIN,
  614. .flags = 0,
  615. }, {
  616. .ops = &mt9t001_ctrl_ops,
  617. .id = V4L2_CID_GAIN_BLUE,
  618. .type = V4L2_CTRL_TYPE_INTEGER,
  619. .name = "Gain, Blue",
  620. .min = MT9T001_GLOBAL_GAIN_MIN,
  621. .max = MT9T001_GLOBAL_GAIN_MAX,
  622. .step = 1,
  623. .def = MT9T001_GLOBAL_GAIN_MIN,
  624. .flags = 0,
  625. },
  626. };
  627. /* -----------------------------------------------------------------------------
  628. * V4L2 subdev core operations
  629. */
  630. static int mt9t001_set_power(struct v4l2_subdev *subdev, int on)
  631. {
  632. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  633. int ret = 0;
  634. mutex_lock(&mt9t001->power_lock);
  635. /* If the power count is modified from 0 to != 0 or from != 0 to 0,
  636. * update the power state.
  637. */
  638. if (mt9t001->power_count == !on) {
  639. ret = __mt9t001_set_power(mt9t001, !!on);
  640. if (ret < 0)
  641. goto out;
  642. }
  643. /* Update the power count. */
  644. mt9t001->power_count += on ? 1 : -1;
  645. WARN_ON(mt9t001->power_count < 0);
  646. out:
  647. mutex_unlock(&mt9t001->power_lock);
  648. return ret;
  649. }
  650. /* -----------------------------------------------------------------------------
  651. * V4L2 subdev internal operations
  652. */
  653. static int mt9t001_registered(struct v4l2_subdev *subdev)
  654. {
  655. struct i2c_client *client = v4l2_get_subdevdata(subdev);
  656. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  657. s32 data;
  658. int ret;
  659. ret = mt9t001_power_on(mt9t001);
  660. if (ret < 0) {
  661. dev_err(&client->dev, "MT9T001 power up failed\n");
  662. return ret;
  663. }
  664. /* Read out the chip version register */
  665. data = mt9t001_read(client, MT9T001_CHIP_VERSION);
  666. mt9t001_power_off(mt9t001);
  667. if (data != MT9T001_CHIP_ID) {
  668. dev_err(&client->dev,
  669. "MT9T001 not detected, wrong version 0x%04x\n", data);
  670. return -ENODEV;
  671. }
  672. dev_info(&client->dev, "MT9T001 detected at address 0x%02x\n",
  673. client->addr);
  674. return 0;
  675. }
  676. static int mt9t001_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
  677. {
  678. struct v4l2_mbus_framefmt *format;
  679. struct v4l2_rect *crop;
  680. crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
  681. crop->left = MT9T001_COLUMN_START_DEF;
  682. crop->top = MT9T001_ROW_START_DEF;
  683. crop->width = MT9T001_WINDOW_WIDTH_DEF + 1;
  684. crop->height = MT9T001_WINDOW_HEIGHT_DEF + 1;
  685. format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
  686. format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
  687. format->width = MT9T001_WINDOW_WIDTH_DEF + 1;
  688. format->height = MT9T001_WINDOW_HEIGHT_DEF + 1;
  689. format->field = V4L2_FIELD_NONE;
  690. format->colorspace = V4L2_COLORSPACE_SRGB;
  691. return mt9t001_set_power(subdev, 1);
  692. }
  693. static int mt9t001_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
  694. {
  695. return mt9t001_set_power(subdev, 0);
  696. }
  697. static const struct v4l2_subdev_core_ops mt9t001_subdev_core_ops = {
  698. .s_power = mt9t001_set_power,
  699. };
  700. static const struct v4l2_subdev_video_ops mt9t001_subdev_video_ops = {
  701. .s_stream = mt9t001_s_stream,
  702. };
  703. static const struct v4l2_subdev_pad_ops mt9t001_subdev_pad_ops = {
  704. .enum_mbus_code = mt9t001_enum_mbus_code,
  705. .enum_frame_size = mt9t001_enum_frame_size,
  706. .get_fmt = mt9t001_get_format,
  707. .set_fmt = mt9t001_set_format,
  708. .get_selection = mt9t001_get_selection,
  709. .set_selection = mt9t001_set_selection,
  710. };
  711. static const struct v4l2_subdev_ops mt9t001_subdev_ops = {
  712. .core = &mt9t001_subdev_core_ops,
  713. .video = &mt9t001_subdev_video_ops,
  714. .pad = &mt9t001_subdev_pad_ops,
  715. };
  716. static const struct v4l2_subdev_internal_ops mt9t001_subdev_internal_ops = {
  717. .registered = mt9t001_registered,
  718. .open = mt9t001_open,
  719. .close = mt9t001_close,
  720. };
  721. static int mt9t001_probe(struct i2c_client *client,
  722. const struct i2c_device_id *did)
  723. {
  724. struct mt9t001_platform_data *pdata = client->dev.platform_data;
  725. struct mt9t001 *mt9t001;
  726. unsigned int i;
  727. int ret;
  728. if (pdata == NULL) {
  729. dev_err(&client->dev, "No platform data\n");
  730. return -EINVAL;
  731. }
  732. if (!i2c_check_functionality(client->adapter,
  733. I2C_FUNC_SMBUS_WORD_DATA)) {
  734. dev_warn(&client->adapter->dev,
  735. "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
  736. return -EIO;
  737. }
  738. mt9t001 = devm_kzalloc(&client->dev, sizeof(*mt9t001), GFP_KERNEL);
  739. if (!mt9t001)
  740. return -ENOMEM;
  741. mutex_init(&mt9t001->power_lock);
  742. mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF;
  743. mt9t001->regulators[0].supply = "vdd";
  744. mt9t001->regulators[1].supply = "vaa";
  745. ret = devm_regulator_bulk_get(&client->dev, 2, mt9t001->regulators);
  746. if (ret < 0) {
  747. dev_err(&client->dev, "Unable to get regulators\n");
  748. return ret;
  749. }
  750. mt9t001->clk = devm_clk_get(&client->dev, NULL);
  751. if (IS_ERR(mt9t001->clk)) {
  752. dev_err(&client->dev, "Unable to get clock\n");
  753. return PTR_ERR(mt9t001->clk);
  754. }
  755. v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) +
  756. ARRAY_SIZE(mt9t001_gains) + 4);
  757. v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
  758. V4L2_CID_EXPOSURE, MT9T001_SHUTTER_WIDTH_MIN,
  759. MT9T001_SHUTTER_WIDTH_MAX, 1,
  760. MT9T001_SHUTTER_WIDTH_DEF);
  761. v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
  762. V4L2_CID_BLACK_LEVEL, 1, 1, 1, 1);
  763. v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
  764. V4L2_CID_PIXEL_RATE, pdata->ext_clk, pdata->ext_clk,
  765. 1, pdata->ext_clk);
  766. v4l2_ctrl_new_std_menu_items(&mt9t001->ctrls, &mt9t001_ctrl_ops,
  767. V4L2_CID_TEST_PATTERN,
  768. ARRAY_SIZE(mt9t001_test_pattern_menu) - 1, 0,
  769. 0, mt9t001_test_pattern_menu);
  770. for (i = 0; i < ARRAY_SIZE(mt9t001_ctrls); ++i)
  771. v4l2_ctrl_new_custom(&mt9t001->ctrls, &mt9t001_ctrls[i], NULL);
  772. for (i = 0; i < ARRAY_SIZE(mt9t001_gains); ++i)
  773. mt9t001->gains[i] = v4l2_ctrl_new_custom(&mt9t001->ctrls,
  774. &mt9t001_gains[i], NULL);
  775. v4l2_ctrl_cluster(ARRAY_SIZE(mt9t001_gains), mt9t001->gains);
  776. mt9t001->subdev.ctrl_handler = &mt9t001->ctrls;
  777. if (mt9t001->ctrls.error) {
  778. printk(KERN_INFO "%s: control initialization error %d\n",
  779. __func__, mt9t001->ctrls.error);
  780. ret = -EINVAL;
  781. goto done;
  782. }
  783. mt9t001->crop.left = MT9T001_COLUMN_START_DEF;
  784. mt9t001->crop.top = MT9T001_ROW_START_DEF;
  785. mt9t001->crop.width = MT9T001_WINDOW_WIDTH_DEF + 1;
  786. mt9t001->crop.height = MT9T001_WINDOW_HEIGHT_DEF + 1;
  787. mt9t001->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
  788. mt9t001->format.width = MT9T001_WINDOW_WIDTH_DEF + 1;
  789. mt9t001->format.height = MT9T001_WINDOW_HEIGHT_DEF + 1;
  790. mt9t001->format.field = V4L2_FIELD_NONE;
  791. mt9t001->format.colorspace = V4L2_COLORSPACE_SRGB;
  792. v4l2_i2c_subdev_init(&mt9t001->subdev, client, &mt9t001_subdev_ops);
  793. mt9t001->subdev.internal_ops = &mt9t001_subdev_internal_ops;
  794. mt9t001->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  795. mt9t001->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  796. mt9t001->pad.flags = MEDIA_PAD_FL_SOURCE;
  797. ret = media_entity_pads_init(&mt9t001->subdev.entity, 1, &mt9t001->pad);
  798. done:
  799. if (ret < 0) {
  800. v4l2_ctrl_handler_free(&mt9t001->ctrls);
  801. media_entity_cleanup(&mt9t001->subdev.entity);
  802. }
  803. return ret;
  804. }
  805. static int mt9t001_remove(struct i2c_client *client)
  806. {
  807. struct v4l2_subdev *subdev = i2c_get_clientdata(client);
  808. struct mt9t001 *mt9t001 = to_mt9t001(subdev);
  809. v4l2_ctrl_handler_free(&mt9t001->ctrls);
  810. v4l2_device_unregister_subdev(subdev);
  811. media_entity_cleanup(&subdev->entity);
  812. return 0;
  813. }
  814. static const struct i2c_device_id mt9t001_id[] = {
  815. { "mt9t001", 0 },
  816. { }
  817. };
  818. MODULE_DEVICE_TABLE(i2c, mt9t001_id);
  819. static struct i2c_driver mt9t001_driver = {
  820. .driver = {
  821. .name = "mt9t001",
  822. },
  823. .probe = mt9t001_probe,
  824. .remove = mt9t001_remove,
  825. .id_table = mt9t001_id,
  826. };
  827. module_i2c_driver(mt9t001_driver);
  828. MODULE_DESCRIPTION("Aptina (Micron) MT9T001 Camera driver");
  829. MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
  830. MODULE_LICENSE("GPL");