omap-mailbox.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * OMAP mailbox driver
  4. *
  5. * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
  6. * Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com
  7. *
  8. * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  9. * Suman Anna <s-anna@ti.com>
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/mutex.h>
  14. #include <linux/slab.h>
  15. #include <linux/kfifo.h>
  16. #include <linux/err.h>
  17. #include <linux/module.h>
  18. #include <linux/of_device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/omap-mailbox.h>
  22. #include <linux/mailbox_controller.h>
  23. #include <linux/mailbox_client.h>
  24. #include "mailbox.h"
  25. #define MAILBOX_REVISION 0x000
  26. #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
  27. #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
  28. #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
  29. #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
  30. #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
  31. #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
  32. #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
  33. #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
  34. #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
  35. OMAP2_MAILBOX_IRQSTATUS(u))
  36. #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
  37. OMAP2_MAILBOX_IRQENABLE(u))
  38. #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
  39. : OMAP2_MAILBOX_IRQENABLE(u))
  40. #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
  41. #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
  42. /* Interrupt register configuration types */
  43. #define MBOX_INTR_CFG_TYPE1 0
  44. #define MBOX_INTR_CFG_TYPE2 1
  45. struct omap_mbox_fifo {
  46. unsigned long msg;
  47. unsigned long fifo_stat;
  48. unsigned long msg_stat;
  49. unsigned long irqenable;
  50. unsigned long irqstatus;
  51. unsigned long irqdisable;
  52. u32 intr_bit;
  53. };
  54. struct omap_mbox_queue {
  55. spinlock_t lock;
  56. struct kfifo fifo;
  57. struct work_struct work;
  58. struct omap_mbox *mbox;
  59. bool full;
  60. };
  61. struct omap_mbox_match_data {
  62. u32 intr_type;
  63. };
  64. struct omap_mbox_device {
  65. struct device *dev;
  66. struct mutex cfg_lock;
  67. void __iomem *mbox_base;
  68. u32 *irq_ctx;
  69. u32 num_users;
  70. u32 num_fifos;
  71. u32 intr_type;
  72. struct omap_mbox **mboxes;
  73. struct mbox_controller controller;
  74. struct list_head elem;
  75. };
  76. struct omap_mbox_fifo_info {
  77. int tx_id;
  78. int tx_usr;
  79. int tx_irq;
  80. int rx_id;
  81. int rx_usr;
  82. int rx_irq;
  83. const char *name;
  84. bool send_no_irq;
  85. };
  86. struct omap_mbox {
  87. const char *name;
  88. int irq;
  89. struct omap_mbox_queue *rxq;
  90. struct device *dev;
  91. struct omap_mbox_device *parent;
  92. struct omap_mbox_fifo tx_fifo;
  93. struct omap_mbox_fifo rx_fifo;
  94. u32 intr_type;
  95. struct mbox_chan *chan;
  96. bool send_no_irq;
  97. };
  98. /* global variables for the mailbox devices */
  99. static DEFINE_MUTEX(omap_mbox_devices_lock);
  100. static LIST_HEAD(omap_mbox_devices);
  101. static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
  102. module_param(mbox_kfifo_size, uint, S_IRUGO);
  103. MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
  104. static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan)
  105. {
  106. if (!chan || !chan->con_priv)
  107. return NULL;
  108. return (struct omap_mbox *)chan->con_priv;
  109. }
  110. static inline
  111. unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
  112. {
  113. return __raw_readl(mdev->mbox_base + ofs);
  114. }
  115. static inline
  116. void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
  117. {
  118. __raw_writel(val, mdev->mbox_base + ofs);
  119. }
  120. /* Mailbox FIFO handle functions */
  121. static mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
  122. {
  123. struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
  124. return (mbox_msg_t)mbox_read_reg(mbox->parent, fifo->msg);
  125. }
  126. static void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
  127. {
  128. struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
  129. mbox_write_reg(mbox->parent, msg, fifo->msg);
  130. }
  131. static int mbox_fifo_empty(struct omap_mbox *mbox)
  132. {
  133. struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
  134. return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
  135. }
  136. static int mbox_fifo_full(struct omap_mbox *mbox)
  137. {
  138. struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
  139. return mbox_read_reg(mbox->parent, fifo->fifo_stat);
  140. }
  141. /* Mailbox IRQ handle functions */
  142. static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  143. {
  144. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  145. &mbox->tx_fifo : &mbox->rx_fifo;
  146. u32 bit = fifo->intr_bit;
  147. u32 irqstatus = fifo->irqstatus;
  148. mbox_write_reg(mbox->parent, bit, irqstatus);
  149. /* Flush posted write for irq status to avoid spurious interrupts */
  150. mbox_read_reg(mbox->parent, irqstatus);
  151. }
  152. static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  153. {
  154. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  155. &mbox->tx_fifo : &mbox->rx_fifo;
  156. u32 bit = fifo->intr_bit;
  157. u32 irqenable = fifo->irqenable;
  158. u32 irqstatus = fifo->irqstatus;
  159. u32 enable = mbox_read_reg(mbox->parent, irqenable);
  160. u32 status = mbox_read_reg(mbox->parent, irqstatus);
  161. return (int)(enable & status & bit);
  162. }
  163. static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  164. {
  165. u32 l;
  166. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  167. &mbox->tx_fifo : &mbox->rx_fifo;
  168. u32 bit = fifo->intr_bit;
  169. u32 irqenable = fifo->irqenable;
  170. l = mbox_read_reg(mbox->parent, irqenable);
  171. l |= bit;
  172. mbox_write_reg(mbox->parent, l, irqenable);
  173. }
  174. static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
  175. {
  176. struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
  177. &mbox->tx_fifo : &mbox->rx_fifo;
  178. u32 bit = fifo->intr_bit;
  179. u32 irqdisable = fifo->irqdisable;
  180. /*
  181. * Read and update the interrupt configuration register for pre-OMAP4.
  182. * OMAP4 and later SoCs have a dedicated interrupt disabling register.
  183. */
  184. if (!mbox->intr_type)
  185. bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
  186. mbox_write_reg(mbox->parent, bit, irqdisable);
  187. }
  188. void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
  189. {
  190. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  191. if (WARN_ON(!mbox))
  192. return;
  193. _omap_mbox_enable_irq(mbox, irq);
  194. }
  195. EXPORT_SYMBOL(omap_mbox_enable_irq);
  196. void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
  197. {
  198. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  199. if (WARN_ON(!mbox))
  200. return;
  201. _omap_mbox_disable_irq(mbox, irq);
  202. }
  203. EXPORT_SYMBOL(omap_mbox_disable_irq);
  204. /*
  205. * Message receiver(workqueue)
  206. */
  207. static void mbox_rx_work(struct work_struct *work)
  208. {
  209. struct omap_mbox_queue *mq =
  210. container_of(work, struct omap_mbox_queue, work);
  211. mbox_msg_t msg;
  212. int len;
  213. while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
  214. len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
  215. WARN_ON(len != sizeof(msg));
  216. mbox_chan_received_data(mq->mbox->chan, (void *)msg);
  217. spin_lock_irq(&mq->lock);
  218. if (mq->full) {
  219. mq->full = false;
  220. _omap_mbox_enable_irq(mq->mbox, IRQ_RX);
  221. }
  222. spin_unlock_irq(&mq->lock);
  223. }
  224. }
  225. /*
  226. * Mailbox interrupt handler
  227. */
  228. static void __mbox_tx_interrupt(struct omap_mbox *mbox)
  229. {
  230. _omap_mbox_disable_irq(mbox, IRQ_TX);
  231. ack_mbox_irq(mbox, IRQ_TX);
  232. mbox_chan_txdone(mbox->chan, 0);
  233. }
  234. static void __mbox_rx_interrupt(struct omap_mbox *mbox)
  235. {
  236. struct omap_mbox_queue *mq = mbox->rxq;
  237. mbox_msg_t msg;
  238. int len;
  239. while (!mbox_fifo_empty(mbox)) {
  240. if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
  241. _omap_mbox_disable_irq(mbox, IRQ_RX);
  242. mq->full = true;
  243. goto nomem;
  244. }
  245. msg = mbox_fifo_read(mbox);
  246. len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
  247. WARN_ON(len != sizeof(msg));
  248. }
  249. /* no more messages in the fifo. clear IRQ source. */
  250. ack_mbox_irq(mbox, IRQ_RX);
  251. nomem:
  252. schedule_work(&mbox->rxq->work);
  253. }
  254. static irqreturn_t mbox_interrupt(int irq, void *p)
  255. {
  256. struct omap_mbox *mbox = p;
  257. if (is_mbox_irq(mbox, IRQ_TX))
  258. __mbox_tx_interrupt(mbox);
  259. if (is_mbox_irq(mbox, IRQ_RX))
  260. __mbox_rx_interrupt(mbox);
  261. return IRQ_HANDLED;
  262. }
  263. static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
  264. void (*work)(struct work_struct *))
  265. {
  266. struct omap_mbox_queue *mq;
  267. if (!work)
  268. return NULL;
  269. mq = kzalloc(sizeof(*mq), GFP_KERNEL);
  270. if (!mq)
  271. return NULL;
  272. spin_lock_init(&mq->lock);
  273. if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
  274. goto error;
  275. INIT_WORK(&mq->work, work);
  276. return mq;
  277. error:
  278. kfree(mq);
  279. return NULL;
  280. }
  281. static void mbox_queue_free(struct omap_mbox_queue *q)
  282. {
  283. kfifo_free(&q->fifo);
  284. kfree(q);
  285. }
  286. static int omap_mbox_startup(struct omap_mbox *mbox)
  287. {
  288. int ret = 0;
  289. struct omap_mbox_queue *mq;
  290. mq = mbox_queue_alloc(mbox, mbox_rx_work);
  291. if (!mq)
  292. return -ENOMEM;
  293. mbox->rxq = mq;
  294. mq->mbox = mbox;
  295. ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
  296. mbox->name, mbox);
  297. if (unlikely(ret)) {
  298. pr_err("failed to register mailbox interrupt:%d\n", ret);
  299. goto fail_request_irq;
  300. }
  301. if (mbox->send_no_irq)
  302. mbox->chan->txdone_method = TXDONE_BY_ACK;
  303. _omap_mbox_enable_irq(mbox, IRQ_RX);
  304. return 0;
  305. fail_request_irq:
  306. mbox_queue_free(mbox->rxq);
  307. return ret;
  308. }
  309. static void omap_mbox_fini(struct omap_mbox *mbox)
  310. {
  311. _omap_mbox_disable_irq(mbox, IRQ_RX);
  312. free_irq(mbox->irq, mbox);
  313. flush_work(&mbox->rxq->work);
  314. mbox_queue_free(mbox->rxq);
  315. }
  316. static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
  317. const char *mbox_name)
  318. {
  319. struct omap_mbox *_mbox, *mbox = NULL;
  320. struct omap_mbox **mboxes = mdev->mboxes;
  321. int i;
  322. if (!mboxes)
  323. return NULL;
  324. for (i = 0; (_mbox = mboxes[i]); i++) {
  325. if (!strcmp(_mbox->name, mbox_name)) {
  326. mbox = _mbox;
  327. break;
  328. }
  329. }
  330. return mbox;
  331. }
  332. struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
  333. const char *chan_name)
  334. {
  335. struct device *dev = cl->dev;
  336. struct omap_mbox *mbox = NULL;
  337. struct omap_mbox_device *mdev;
  338. struct mbox_chan *chan;
  339. unsigned long flags;
  340. int ret;
  341. if (!dev)
  342. return ERR_PTR(-ENODEV);
  343. if (dev->of_node) {
  344. pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n",
  345. __func__);
  346. return ERR_PTR(-ENODEV);
  347. }
  348. mutex_lock(&omap_mbox_devices_lock);
  349. list_for_each_entry(mdev, &omap_mbox_devices, elem) {
  350. mbox = omap_mbox_device_find(mdev, chan_name);
  351. if (mbox)
  352. break;
  353. }
  354. mutex_unlock(&omap_mbox_devices_lock);
  355. if (!mbox || !mbox->chan)
  356. return ERR_PTR(-ENOENT);
  357. chan = mbox->chan;
  358. spin_lock_irqsave(&chan->lock, flags);
  359. chan->msg_free = 0;
  360. chan->msg_count = 0;
  361. chan->active_req = NULL;
  362. chan->cl = cl;
  363. init_completion(&chan->tx_complete);
  364. spin_unlock_irqrestore(&chan->lock, flags);
  365. ret = chan->mbox->ops->startup(chan);
  366. if (ret) {
  367. pr_err("Unable to startup the chan (%d)\n", ret);
  368. mbox_free_channel(chan);
  369. chan = ERR_PTR(ret);
  370. }
  371. return chan;
  372. }
  373. EXPORT_SYMBOL(omap_mbox_request_channel);
  374. static struct class omap_mbox_class = { .name = "mbox", };
  375. static int omap_mbox_register(struct omap_mbox_device *mdev)
  376. {
  377. int ret;
  378. int i;
  379. struct omap_mbox **mboxes;
  380. if (!mdev || !mdev->mboxes)
  381. return -EINVAL;
  382. mboxes = mdev->mboxes;
  383. for (i = 0; mboxes[i]; i++) {
  384. struct omap_mbox *mbox = mboxes[i];
  385. mbox->dev = device_create(&omap_mbox_class, mdev->dev,
  386. 0, mbox, "%s", mbox->name);
  387. if (IS_ERR(mbox->dev)) {
  388. ret = PTR_ERR(mbox->dev);
  389. goto err_out;
  390. }
  391. }
  392. mutex_lock(&omap_mbox_devices_lock);
  393. list_add(&mdev->elem, &omap_mbox_devices);
  394. mutex_unlock(&omap_mbox_devices_lock);
  395. ret = mbox_controller_register(&mdev->controller);
  396. err_out:
  397. if (ret) {
  398. while (i--)
  399. device_unregister(mboxes[i]->dev);
  400. }
  401. return ret;
  402. }
  403. static int omap_mbox_unregister(struct omap_mbox_device *mdev)
  404. {
  405. int i;
  406. struct omap_mbox **mboxes;
  407. if (!mdev || !mdev->mboxes)
  408. return -EINVAL;
  409. mutex_lock(&omap_mbox_devices_lock);
  410. list_del(&mdev->elem);
  411. mutex_unlock(&omap_mbox_devices_lock);
  412. mbox_controller_unregister(&mdev->controller);
  413. mboxes = mdev->mboxes;
  414. for (i = 0; mboxes[i]; i++)
  415. device_unregister(mboxes[i]->dev);
  416. return 0;
  417. }
  418. static int omap_mbox_chan_startup(struct mbox_chan *chan)
  419. {
  420. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  421. struct omap_mbox_device *mdev = mbox->parent;
  422. int ret = 0;
  423. mutex_lock(&mdev->cfg_lock);
  424. pm_runtime_get_sync(mdev->dev);
  425. ret = omap_mbox_startup(mbox);
  426. if (ret)
  427. pm_runtime_put_sync(mdev->dev);
  428. mutex_unlock(&mdev->cfg_lock);
  429. return ret;
  430. }
  431. static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
  432. {
  433. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  434. struct omap_mbox_device *mdev = mbox->parent;
  435. mutex_lock(&mdev->cfg_lock);
  436. omap_mbox_fini(mbox);
  437. pm_runtime_put_sync(mdev->dev);
  438. mutex_unlock(&mdev->cfg_lock);
  439. }
  440. static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, void *data)
  441. {
  442. int ret = -EBUSY;
  443. if (!mbox_fifo_full(mbox)) {
  444. _omap_mbox_enable_irq(mbox, IRQ_RX);
  445. mbox_fifo_write(mbox, (mbox_msg_t)data);
  446. ret = 0;
  447. _omap_mbox_disable_irq(mbox, IRQ_RX);
  448. /* we must read and ack the interrupt directly from here */
  449. mbox_fifo_read(mbox);
  450. ack_mbox_irq(mbox, IRQ_RX);
  451. }
  452. return ret;
  453. }
  454. static int omap_mbox_chan_send(struct omap_mbox *mbox, void *data)
  455. {
  456. int ret = -EBUSY;
  457. if (!mbox_fifo_full(mbox)) {
  458. mbox_fifo_write(mbox, (mbox_msg_t)data);
  459. ret = 0;
  460. }
  461. /* always enable the interrupt */
  462. _omap_mbox_enable_irq(mbox, IRQ_TX);
  463. return ret;
  464. }
  465. static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
  466. {
  467. struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
  468. int ret;
  469. if (!mbox)
  470. return -EINVAL;
  471. if (mbox->send_no_irq)
  472. ret = omap_mbox_chan_send_noirq(mbox, data);
  473. else
  474. ret = omap_mbox_chan_send(mbox, data);
  475. return ret;
  476. }
  477. static const struct mbox_chan_ops omap_mbox_chan_ops = {
  478. .startup = omap_mbox_chan_startup,
  479. .send_data = omap_mbox_chan_send_data,
  480. .shutdown = omap_mbox_chan_shutdown,
  481. };
  482. #ifdef CONFIG_PM_SLEEP
  483. static int omap_mbox_suspend(struct device *dev)
  484. {
  485. struct omap_mbox_device *mdev = dev_get_drvdata(dev);
  486. u32 usr, fifo, reg;
  487. if (pm_runtime_status_suspended(dev))
  488. return 0;
  489. for (fifo = 0; fifo < mdev->num_fifos; fifo++) {
  490. if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) {
  491. dev_err(mdev->dev, "fifo %d has unexpected unread messages\n",
  492. fifo);
  493. return -EBUSY;
  494. }
  495. }
  496. for (usr = 0; usr < mdev->num_users; usr++) {
  497. reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
  498. mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg);
  499. }
  500. return 0;
  501. }
  502. static int omap_mbox_resume(struct device *dev)
  503. {
  504. struct omap_mbox_device *mdev = dev_get_drvdata(dev);
  505. u32 usr, reg;
  506. if (pm_runtime_status_suspended(dev))
  507. return 0;
  508. for (usr = 0; usr < mdev->num_users; usr++) {
  509. reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
  510. mbox_write_reg(mdev, mdev->irq_ctx[usr], reg);
  511. }
  512. return 0;
  513. }
  514. #endif
  515. static const struct dev_pm_ops omap_mbox_pm_ops = {
  516. SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume)
  517. };
  518. static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 };
  519. static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 };
  520. static const struct of_device_id omap_mailbox_of_match[] = {
  521. {
  522. .compatible = "ti,omap2-mailbox",
  523. .data = &omap2_data,
  524. },
  525. {
  526. .compatible = "ti,omap3-mailbox",
  527. .data = &omap2_data,
  528. },
  529. {
  530. .compatible = "ti,omap4-mailbox",
  531. .data = &omap4_data,
  532. },
  533. {
  534. /* end */
  535. },
  536. };
  537. MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
  538. static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
  539. const struct of_phandle_args *sp)
  540. {
  541. phandle phandle = sp->args[0];
  542. struct device_node *node;
  543. struct omap_mbox_device *mdev;
  544. struct omap_mbox *mbox;
  545. mdev = container_of(controller, struct omap_mbox_device, controller);
  546. if (WARN_ON(!mdev))
  547. return ERR_PTR(-EINVAL);
  548. node = of_find_node_by_phandle(phandle);
  549. if (!node) {
  550. pr_err("%s: could not find node phandle 0x%x\n",
  551. __func__, phandle);
  552. return ERR_PTR(-ENODEV);
  553. }
  554. mbox = omap_mbox_device_find(mdev, node->name);
  555. of_node_put(node);
  556. return mbox ? mbox->chan : ERR_PTR(-ENOENT);
  557. }
  558. static int omap_mbox_probe(struct platform_device *pdev)
  559. {
  560. struct resource *mem;
  561. int ret;
  562. struct mbox_chan *chnls;
  563. struct omap_mbox **list, *mbox, *mboxblk;
  564. struct omap_mbox_fifo_info *finfo, *finfoblk;
  565. struct omap_mbox_device *mdev;
  566. struct omap_mbox_fifo *fifo;
  567. struct device_node *node = pdev->dev.of_node;
  568. struct device_node *child;
  569. const struct omap_mbox_match_data *match_data;
  570. u32 intr_type, info_count;
  571. u32 num_users, num_fifos;
  572. u32 tmp[3];
  573. u32 l;
  574. int i;
  575. if (!node) {
  576. pr_err("%s: only DT-based devices are supported\n", __func__);
  577. return -ENODEV;
  578. }
  579. match_data = of_device_get_match_data(&pdev->dev);
  580. if (!match_data)
  581. return -ENODEV;
  582. intr_type = match_data->intr_type;
  583. if (of_property_read_u32(node, "ti,mbox-num-users", &num_users))
  584. return -ENODEV;
  585. if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos))
  586. return -ENODEV;
  587. info_count = of_get_available_child_count(node);
  588. if (!info_count) {
  589. dev_err(&pdev->dev, "no available mbox devices found\n");
  590. return -ENODEV;
  591. }
  592. finfoblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*finfoblk),
  593. GFP_KERNEL);
  594. if (!finfoblk)
  595. return -ENOMEM;
  596. finfo = finfoblk;
  597. child = NULL;
  598. for (i = 0; i < info_count; i++, finfo++) {
  599. child = of_get_next_available_child(node, child);
  600. ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp,
  601. ARRAY_SIZE(tmp));
  602. if (ret)
  603. return ret;
  604. finfo->tx_id = tmp[0];
  605. finfo->tx_irq = tmp[1];
  606. finfo->tx_usr = tmp[2];
  607. ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp,
  608. ARRAY_SIZE(tmp));
  609. if (ret)
  610. return ret;
  611. finfo->rx_id = tmp[0];
  612. finfo->rx_irq = tmp[1];
  613. finfo->rx_usr = tmp[2];
  614. finfo->name = child->name;
  615. if (of_find_property(child, "ti,mbox-send-noirq", NULL))
  616. finfo->send_no_irq = true;
  617. if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
  618. finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)
  619. return -EINVAL;
  620. }
  621. mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
  622. if (!mdev)
  623. return -ENOMEM;
  624. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  625. mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem);
  626. if (IS_ERR(mdev->mbox_base))
  627. return PTR_ERR(mdev->mbox_base);
  628. mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32),
  629. GFP_KERNEL);
  630. if (!mdev->irq_ctx)
  631. return -ENOMEM;
  632. /* allocate one extra for marking end of list */
  633. list = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*list),
  634. GFP_KERNEL);
  635. if (!list)
  636. return -ENOMEM;
  637. chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls),
  638. GFP_KERNEL);
  639. if (!chnls)
  640. return -ENOMEM;
  641. mboxblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*mbox),
  642. GFP_KERNEL);
  643. if (!mboxblk)
  644. return -ENOMEM;
  645. mbox = mboxblk;
  646. finfo = finfoblk;
  647. for (i = 0; i < info_count; i++, finfo++) {
  648. fifo = &mbox->tx_fifo;
  649. fifo->msg = MAILBOX_MESSAGE(finfo->tx_id);
  650. fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id);
  651. fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id);
  652. fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr);
  653. fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr);
  654. fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr);
  655. fifo = &mbox->rx_fifo;
  656. fifo->msg = MAILBOX_MESSAGE(finfo->rx_id);
  657. fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id);
  658. fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id);
  659. fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr);
  660. fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr);
  661. fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr);
  662. mbox->send_no_irq = finfo->send_no_irq;
  663. mbox->intr_type = intr_type;
  664. mbox->parent = mdev;
  665. mbox->name = finfo->name;
  666. mbox->irq = platform_get_irq(pdev, finfo->tx_irq);
  667. if (mbox->irq < 0)
  668. return mbox->irq;
  669. mbox->chan = &chnls[i];
  670. chnls[i].con_priv = mbox;
  671. list[i] = mbox++;
  672. }
  673. mutex_init(&mdev->cfg_lock);
  674. mdev->dev = &pdev->dev;
  675. mdev->num_users = num_users;
  676. mdev->num_fifos = num_fifos;
  677. mdev->intr_type = intr_type;
  678. mdev->mboxes = list;
  679. /* OMAP does not have a Tx-Done IRQ, but rather a Tx-Ready IRQ */
  680. mdev->controller.txdone_irq = true;
  681. mdev->controller.dev = mdev->dev;
  682. mdev->controller.ops = &omap_mbox_chan_ops;
  683. mdev->controller.chans = chnls;
  684. mdev->controller.num_chans = info_count;
  685. mdev->controller.of_xlate = omap_mbox_of_xlate;
  686. ret = omap_mbox_register(mdev);
  687. if (ret)
  688. return ret;
  689. platform_set_drvdata(pdev, mdev);
  690. pm_runtime_enable(mdev->dev);
  691. ret = pm_runtime_get_sync(mdev->dev);
  692. if (ret < 0) {
  693. pm_runtime_put_noidle(mdev->dev);
  694. goto unregister;
  695. }
  696. /*
  697. * just print the raw revision register, the format is not
  698. * uniform across all SoCs
  699. */
  700. l = mbox_read_reg(mdev, MAILBOX_REVISION);
  701. dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
  702. ret = pm_runtime_put_sync(mdev->dev);
  703. if (ret < 0)
  704. goto unregister;
  705. devm_kfree(&pdev->dev, finfoblk);
  706. return 0;
  707. unregister:
  708. pm_runtime_disable(mdev->dev);
  709. omap_mbox_unregister(mdev);
  710. return ret;
  711. }
  712. static int omap_mbox_remove(struct platform_device *pdev)
  713. {
  714. struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
  715. pm_runtime_disable(mdev->dev);
  716. omap_mbox_unregister(mdev);
  717. return 0;
  718. }
  719. static struct platform_driver omap_mbox_driver = {
  720. .probe = omap_mbox_probe,
  721. .remove = omap_mbox_remove,
  722. .driver = {
  723. .name = "omap-mailbox",
  724. .pm = &omap_mbox_pm_ops,
  725. .of_match_table = of_match_ptr(omap_mailbox_of_match),
  726. },
  727. };
  728. static int __init omap_mbox_init(void)
  729. {
  730. int err;
  731. err = class_register(&omap_mbox_class);
  732. if (err)
  733. return err;
  734. /* kfifo size sanity check: alignment and minimal size */
  735. mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
  736. mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
  737. sizeof(mbox_msg_t));
  738. err = platform_driver_register(&omap_mbox_driver);
  739. if (err)
  740. class_unregister(&omap_mbox_class);
  741. return err;
  742. }
  743. subsys_initcall(omap_mbox_init);
  744. static void __exit omap_mbox_exit(void)
  745. {
  746. platform_driver_unregister(&omap_mbox_driver);
  747. class_unregister(&omap_mbox_class);
  748. }
  749. module_exit(omap_mbox_exit);
  750. MODULE_LICENSE("GPL v2");
  751. MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
  752. MODULE_AUTHOR("Toshihiro Kobayashi");
  753. MODULE_AUTHOR("Hiroshi DOYU");