coresight-etm4x.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _CORESIGHT_CORESIGHT_ETM_H
  6. #define _CORESIGHT_CORESIGHT_ETM_H
  7. #include <asm/local.h>
  8. #include <linux/spinlock.h>
  9. #include "coresight-priv.h"
  10. /*
  11. * Device registers:
  12. * 0x000 - 0x2FC: Trace registers
  13. * 0x300 - 0x314: Management registers
  14. * 0x318 - 0xEFC: Trace registers
  15. * 0xF00: Management registers
  16. * 0xFA0 - 0xFA4: Trace registers
  17. * 0xFA8 - 0xFFC: Management registers
  18. */
  19. /* Trace registers (0x000-0x2FC) */
  20. /* Main control and configuration registers */
  21. #define TRCPRGCTLR 0x004
  22. #define TRCPROCSELR 0x008
  23. #define TRCSTATR 0x00C
  24. #define TRCCONFIGR 0x010
  25. #define TRCAUXCTLR 0x018
  26. #define TRCEVENTCTL0R 0x020
  27. #define TRCEVENTCTL1R 0x024
  28. #define TRCSTALLCTLR 0x02C
  29. #define TRCTSCTLR 0x030
  30. #define TRCSYNCPR 0x034
  31. #define TRCCCCTLR 0x038
  32. #define TRCBBCTLR 0x03C
  33. #define TRCTRACEIDR 0x040
  34. #define TRCQCTLR 0x044
  35. /* Filtering control registers */
  36. #define TRCVICTLR 0x080
  37. #define TRCVIIECTLR 0x084
  38. #define TRCVISSCTLR 0x088
  39. #define TRCVIPCSSCTLR 0x08C
  40. #define TRCVDCTLR 0x0A0
  41. #define TRCVDSACCTLR 0x0A4
  42. #define TRCVDARCCTLR 0x0A8
  43. /* Derived resources registers */
  44. #define TRCSEQEVRn(n) (0x100 + (n * 4))
  45. #define TRCSEQRSTEVR 0x118
  46. #define TRCSEQSTR 0x11C
  47. #define TRCEXTINSELR 0x120
  48. #define TRCCNTRLDVRn(n) (0x140 + (n * 4))
  49. #define TRCCNTCTLRn(n) (0x150 + (n * 4))
  50. #define TRCCNTVRn(n) (0x160 + (n * 4))
  51. /* ID registers */
  52. #define TRCIDR8 0x180
  53. #define TRCIDR9 0x184
  54. #define TRCIDR10 0x188
  55. #define TRCIDR11 0x18C
  56. #define TRCIDR12 0x190
  57. #define TRCIDR13 0x194
  58. #define TRCIMSPEC0 0x1C0
  59. #define TRCIMSPECn(n) (0x1C0 + (n * 4))
  60. #define TRCIDR0 0x1E0
  61. #define TRCIDR1 0x1E4
  62. #define TRCIDR2 0x1E8
  63. #define TRCIDR3 0x1EC
  64. #define TRCIDR4 0x1F0
  65. #define TRCIDR5 0x1F4
  66. #define TRCIDR6 0x1F8
  67. #define TRCIDR7 0x1FC
  68. /* Resource selection registers */
  69. #define TRCRSCTLRn(n) (0x200 + (n * 4))
  70. /* Single-shot comparator registers */
  71. #define TRCSSCCRn(n) (0x280 + (n * 4))
  72. #define TRCSSCSRn(n) (0x2A0 + (n * 4))
  73. #define TRCSSPCICRn(n) (0x2C0 + (n * 4))
  74. /* Management registers (0x300-0x314) */
  75. #define TRCOSLAR 0x300
  76. #define TRCOSLSR 0x304
  77. #define TRCPDCR 0x310
  78. #define TRCPDSR 0x314
  79. /* Trace registers (0x318-0xEFC) */
  80. /* Comparator registers */
  81. #define TRCACVRn(n) (0x400 + (n * 8))
  82. #define TRCACATRn(n) (0x480 + (n * 8))
  83. #define TRCDVCVRn(n) (0x500 + (n * 16))
  84. #define TRCDVCMRn(n) (0x580 + (n * 16))
  85. #define TRCCIDCVRn(n) (0x600 + (n * 8))
  86. #define TRCVMIDCVRn(n) (0x640 + (n * 8))
  87. #define TRCCIDCCTLR0 0x680
  88. #define TRCCIDCCTLR1 0x684
  89. #define TRCVMIDCCTLR0 0x688
  90. #define TRCVMIDCCTLR1 0x68C
  91. /* Management register (0xF00) */
  92. /* Integration control registers */
  93. #define TRCITCTRL 0xF00
  94. /* Trace registers (0xFA0-0xFA4) */
  95. /* Claim tag registers */
  96. #define TRCCLAIMSET 0xFA0
  97. #define TRCCLAIMCLR 0xFA4
  98. /* Management registers (0xFA8-0xFFC) */
  99. #define TRCDEVAFF0 0xFA8
  100. #define TRCDEVAFF1 0xFAC
  101. #define TRCLAR 0xFB0
  102. #define TRCLSR 0xFB4
  103. #define TRCAUTHSTATUS 0xFB8
  104. #define TRCDEVARCH 0xFBC
  105. #define TRCDEVID 0xFC8
  106. #define TRCDEVTYPE 0xFCC
  107. #define TRCPIDR4 0xFD0
  108. #define TRCPIDR5 0xFD4
  109. #define TRCPIDR6 0xFD8
  110. #define TRCPIDR7 0xFDC
  111. #define TRCPIDR0 0xFE0
  112. #define TRCPIDR1 0xFE4
  113. #define TRCPIDR2 0xFE8
  114. #define TRCPIDR3 0xFEC
  115. #define TRCCIDR0 0xFF0
  116. #define TRCCIDR1 0xFF4
  117. #define TRCCIDR2 0xFF8
  118. #define TRCCIDR3 0xFFC
  119. /* ETMv4 resources */
  120. #define ETM_MAX_NR_PE 8
  121. #define ETMv4_MAX_CNTR 4
  122. #define ETM_MAX_SEQ_STATES 4
  123. #define ETM_MAX_EXT_INP_SEL 4
  124. #define ETM_MAX_EXT_INP 256
  125. #define ETM_MAX_EXT_OUT 4
  126. #define ETM_MAX_SINGLE_ADDR_CMP 16
  127. #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
  128. #define ETM_MAX_DATA_VAL_CMP 8
  129. #define ETMv4_MAX_CTXID_CMP 8
  130. #define ETM_MAX_VMID_CMP 8
  131. #define ETM_MAX_PE_CMP 8
  132. #define ETM_MAX_RES_SEL 16
  133. #define ETM_MAX_SS_CMP 8
  134. #define ETM_ARCH_V4 0x40
  135. #define ETMv4_SYNC_MASK 0x1F
  136. #define ETM_CYC_THRESHOLD_MASK 0xFFF
  137. #define ETM_CYC_THRESHOLD_DEFAULT 0x100
  138. #define ETMv4_EVENT_MASK 0xFF
  139. #define ETM_CNTR_MAX_VAL 0xFFFF
  140. #define ETM_TRACEID_MASK 0x3f
  141. /* ETMv4 programming modes */
  142. #define ETM_MODE_EXCLUDE BIT(0)
  143. #define ETM_MODE_LOAD BIT(1)
  144. #define ETM_MODE_STORE BIT(2)
  145. #define ETM_MODE_LOAD_STORE BIT(3)
  146. #define ETM_MODE_BB BIT(4)
  147. #define ETMv4_MODE_CYCACC BIT(5)
  148. #define ETMv4_MODE_CTXID BIT(6)
  149. #define ETM_MODE_VMID BIT(7)
  150. #define ETM_MODE_COND(val) BMVAL(val, 8, 10)
  151. #define ETMv4_MODE_TIMESTAMP BIT(11)
  152. #define ETM_MODE_RETURNSTACK BIT(12)
  153. #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
  154. #define ETM_MODE_DATA_TRACE_ADDR BIT(15)
  155. #define ETM_MODE_DATA_TRACE_VAL BIT(16)
  156. #define ETM_MODE_ISTALL BIT(17)
  157. #define ETM_MODE_DSTALL BIT(18)
  158. #define ETM_MODE_ATB_TRIGGER BIT(19)
  159. #define ETM_MODE_LPOVERRIDE BIT(20)
  160. #define ETM_MODE_ISTALL_EN BIT(21)
  161. #define ETM_MODE_DSTALL_EN BIT(22)
  162. #define ETM_MODE_INSTPRIO BIT(23)
  163. #define ETM_MODE_NOOVERFLOW BIT(24)
  164. #define ETM_MODE_TRACE_RESET BIT(25)
  165. #define ETM_MODE_TRACE_ERR BIT(26)
  166. #define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
  167. #define ETMv4_MODE_ALL (GENMASK(27, 0) | \
  168. ETM_MODE_EXCL_KERN | \
  169. ETM_MODE_EXCL_USER)
  170. #define TRCSTATR_IDLE_BIT 0
  171. #define ETM_DEFAULT_ADDR_COMP 0
  172. /* PowerDown Control Register bits */
  173. #define TRCPDCR_PU BIT(3)
  174. /* secure state access levels */
  175. #define ETM_EXLEVEL_S_APP BIT(8)
  176. #define ETM_EXLEVEL_S_OS BIT(9)
  177. #define ETM_EXLEVEL_S_NA BIT(10)
  178. #define ETM_EXLEVEL_S_HYP BIT(11)
  179. /* non-secure state access levels */
  180. #define ETM_EXLEVEL_NS_APP BIT(12)
  181. #define ETM_EXLEVEL_NS_OS BIT(13)
  182. #define ETM_EXLEVEL_NS_HYP BIT(14)
  183. #define ETM_EXLEVEL_NS_NA BIT(15)
  184. /**
  185. * struct etmv4_config - configuration information related to an ETMv4
  186. * @mode: Controls various modes supported by this ETM.
  187. * @pe_sel: Controls which PE to trace.
  188. * @cfg: Controls the tracing options.
  189. * @eventctrl0: Controls the tracing of arbitrary events.
  190. * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
  191. * @stallctl: If functionality that prevents trace unit buffer overflows
  192. * is available.
  193. * @ts_ctrl: Controls the insertion of global timestamps in the
  194. * trace streams.
  195. * @syncfreq: Controls how often trace synchronization requests occur.
  196. * the TRCCCCTLR register.
  197. * @ccctlr: Sets the threshold value for cycle counting.
  198. * @vinst_ctrl: Controls instruction trace filtering.
  199. * @viiectlr: Set or read, the address range comparators.
  200. * @vissctlr: Set, or read, the single address comparators that control the
  201. * ViewInst start-stop logic.
  202. * @vipcssctlr: Set, or read, which PE comparator inputs can control the
  203. * ViewInst start-stop logic.
  204. * @seq_idx: Sequencor index selector.
  205. * @seq_ctrl: Control for the sequencer state transition control register.
  206. * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
  207. * @seq_state: Set, or read the sequencer state.
  208. * @cntr_idx: Counter index seletor.
  209. * @cntrldvr: Sets or returns the reload count value for a counter.
  210. * @cntr_ctrl: Controls the operation of a counter.
  211. * @cntr_val: Sets or returns the value for a counter.
  212. * @res_idx: Resource index selector.
  213. * @res_ctrl: Controls the selection of the resources in the trace unit.
  214. * @ss_ctrl: Controls the corresponding single-shot comparator resource.
  215. * @ss_status: The status of the corresponding single-shot comparator.
  216. * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
  217. * @addr_idx: Address comparator index selector.
  218. * @addr_val: Value for address comparator.
  219. * @addr_acc: Address comparator access type.
  220. * @addr_type: Current status of the comparator register.
  221. * @ctxid_idx: Context ID index selector.
  222. * @ctxid_pid: Value of the context ID comparator.
  223. * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
  224. * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
  225. * @vmid_idx: VM ID index selector.
  226. * @vmid_val: Value of the VM ID comparator.
  227. * @vmid_mask0: VM ID comparator mask for comparator 0-3.
  228. * @vmid_mask1: VM ID comparator mask for comparator 4-7.
  229. * @ext_inp: External input selection.
  230. */
  231. struct etmv4_config {
  232. u32 mode;
  233. u32 pe_sel;
  234. u32 cfg;
  235. u32 eventctrl0;
  236. u32 eventctrl1;
  237. u32 stall_ctrl;
  238. u32 ts_ctrl;
  239. u32 syncfreq;
  240. u32 ccctlr;
  241. u32 bb_ctrl;
  242. u32 vinst_ctrl;
  243. u32 viiectlr;
  244. u32 vissctlr;
  245. u32 vipcssctlr;
  246. u8 seq_idx;
  247. u32 seq_ctrl[ETM_MAX_SEQ_STATES];
  248. u32 seq_rst;
  249. u32 seq_state;
  250. u8 cntr_idx;
  251. u32 cntrldvr[ETMv4_MAX_CNTR];
  252. u32 cntr_ctrl[ETMv4_MAX_CNTR];
  253. u32 cntr_val[ETMv4_MAX_CNTR];
  254. u8 res_idx;
  255. u32 res_ctrl[ETM_MAX_RES_SEL];
  256. u32 ss_ctrl[ETM_MAX_SS_CMP];
  257. u32 ss_status[ETM_MAX_SS_CMP];
  258. u32 ss_pe_cmp[ETM_MAX_SS_CMP];
  259. u8 addr_idx;
  260. u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
  261. u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
  262. u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
  263. u8 ctxid_idx;
  264. u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
  265. u32 ctxid_mask0;
  266. u32 ctxid_mask1;
  267. u8 vmid_idx;
  268. u64 vmid_val[ETM_MAX_VMID_CMP];
  269. u32 vmid_mask0;
  270. u32 vmid_mask1;
  271. u32 ext_inp;
  272. };
  273. /**
  274. * struct etm4_drvdata - specifics associated to an ETM component
  275. * @base: Memory mapped base address for this component.
  276. * @dev: The device entity associated to this component.
  277. * @csdev: Component vitals needed by the framework.
  278. * @spinlock: Only one at a time pls.
  279. * @mode: This tracer's mode, i.e sysFS, Perf or disabled.
  280. * @cpu: The cpu this component is affined to.
  281. * @arch: ETM version number.
  282. * @nr_pe: The number of processing entity available for tracing.
  283. * @nr_pe_cmp: The number of processing entity comparator inputs that are
  284. * available for tracing.
  285. * @nr_addr_cmp:Number of pairs of address comparators available
  286. * as found in ETMIDR4 0-3.
  287. * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
  288. * @nr_ext_inp: Number of external input.
  289. * @numcidc: Number of contextID comparators.
  290. * @numvmidc: Number of VMID comparators.
  291. * @nrseqstate: The number of sequencer states that are implemented.
  292. * @nr_event: Indicates how many events the trace unit support.
  293. * @nr_resource:The number of resource selection pairs available for tracing.
  294. * @nr_ss_cmp: Number of single-shot comparator controls that are available.
  295. * @trcid: value of the current ID for this component.
  296. * @trcid_size: Indicates the trace ID width.
  297. * @ts_size: Global timestamp size field.
  298. * @ctxid_size: Size of the context ID field to consider.
  299. * @vmid_size: Size of the VM ID comparator to consider.
  300. * @ccsize: Indicates the size of the cycle counter in bits.
  301. * @ccitmin: minimum value that can be programmed in
  302. * @s_ex_level: In secure state, indicates whether instruction tracing is
  303. * supported for the corresponding Exception level.
  304. * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
  305. * supported for the corresponding Exception level.
  306. * @sticky_enable: true if ETM base configuration has been done.
  307. * @boot_enable:True if we should start tracing at boot time.
  308. * @os_unlock: True if access to management registers is allowed.
  309. * @instrp0: Tracing of load and store instructions
  310. * as P0 elements is supported.
  311. * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
  312. * @trccond: If the trace unit supports conditional
  313. * instruction tracing.
  314. * @retstack: Indicates if the implementation supports a return stack.
  315. * @trccci: Indicates if the trace unit supports cycle counting
  316. * for instruction.
  317. * @q_support: Q element support characteristics.
  318. * @trc_error: Whether a trace unit can trace a system
  319. * error exception.
  320. * @syncpr: Indicates if an implementation has a fixed
  321. * synchronization period.
  322. * @stall_ctrl: Enables trace unit functionality that prevents trace
  323. * unit buffer overflows.
  324. * @sysstall: Does the system support stall control of the PE?
  325. * @nooverflow: Indicate if overflow prevention is supported.
  326. * @atbtrig: If the implementation can support ATB triggers
  327. * @lpoverride: If the implementation can support low-power state over.
  328. * @config: structure holding configuration parameters.
  329. */
  330. struct etmv4_drvdata {
  331. void __iomem *base;
  332. struct device *dev;
  333. struct coresight_device *csdev;
  334. spinlock_t spinlock;
  335. local_t mode;
  336. int cpu;
  337. u8 arch;
  338. u8 nr_pe;
  339. u8 nr_pe_cmp;
  340. u8 nr_addr_cmp;
  341. u8 nr_cntr;
  342. u8 nr_ext_inp;
  343. u8 numcidc;
  344. u8 numvmidc;
  345. u8 nrseqstate;
  346. u8 nr_event;
  347. u8 nr_resource;
  348. u8 nr_ss_cmp;
  349. u8 trcid;
  350. u8 trcid_size;
  351. u8 ts_size;
  352. u8 ctxid_size;
  353. u8 vmid_size;
  354. u8 ccsize;
  355. u8 ccitmin;
  356. u8 s_ex_level;
  357. u8 ns_ex_level;
  358. u8 q_support;
  359. bool sticky_enable;
  360. bool boot_enable;
  361. bool os_unlock;
  362. bool instrp0;
  363. bool trcbb;
  364. bool trccond;
  365. bool retstack;
  366. bool trccci;
  367. bool trc_error;
  368. bool syncpr;
  369. bool stallctl;
  370. bool sysstall;
  371. bool nooverflow;
  372. bool atbtrig;
  373. bool lpoverride;
  374. struct etmv4_config config;
  375. };
  376. /* Address comparator access types */
  377. enum etm_addr_acctype {
  378. ETM_INSTR_ADDR,
  379. ETM_DATA_LOAD_ADDR,
  380. ETM_DATA_STORE_ADDR,
  381. ETM_DATA_LOAD_STORE_ADDR,
  382. };
  383. /* Address comparator context types */
  384. enum etm_addr_ctxtype {
  385. ETM_CTX_NONE,
  386. ETM_CTX_CTXID,
  387. ETM_CTX_VMID,
  388. ETM_CTX_CTXID_VMID,
  389. };
  390. extern const struct attribute_group *coresight_etmv4_groups[];
  391. void etm4_config_trace_mode(struct etmv4_config *config);
  392. #endif