sdma_v3_0.c 50 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #include <linux/firmware.h>
  25. #include <drm/drmP.h>
  26. #include "amdgpu.h"
  27. #include "amdgpu_ucode.h"
  28. #include "amdgpu_trace.h"
  29. #include "vi.h"
  30. #include "vid.h"
  31. #include "oss/oss_3_0_d.h"
  32. #include "oss/oss_3_0_sh_mask.h"
  33. #include "gmc/gmc_8_1_d.h"
  34. #include "gmc/gmc_8_1_sh_mask.h"
  35. #include "gca/gfx_8_0_d.h"
  36. #include "gca/gfx_8_0_enum.h"
  37. #include "gca/gfx_8_0_sh_mask.h"
  38. #include "bif/bif_5_0_d.h"
  39. #include "bif/bif_5_0_sh_mask.h"
  40. #include "tonga_sdma_pkt_open.h"
  41. #include "ivsrcid/ivsrcid_vislands30.h"
  42. static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  43. static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  44. static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  45. static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  46. MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  47. MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  48. MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  49. MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  50. MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  51. MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  52. MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  53. MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  54. MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  55. MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  56. MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  57. MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
  58. MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
  59. MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
  60. MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
  61. static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  62. {
  63. SDMA0_REGISTER_OFFSET,
  64. SDMA1_REGISTER_OFFSET
  65. };
  66. static const u32 golden_settings_tonga_a11[] =
  67. {
  68. mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  69. mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  70. mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  71. mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  72. mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  73. mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  74. mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  75. mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  76. mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  77. mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  78. };
  79. static const u32 tonga_mgcg_cgcg_init[] =
  80. {
  81. mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  82. mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  83. };
  84. static const u32 golden_settings_fiji_a10[] =
  85. {
  86. mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  87. mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  88. mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  89. mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  90. mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  91. mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  92. mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  93. mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  94. };
  95. static const u32 fiji_mgcg_cgcg_init[] =
  96. {
  97. mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  98. mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  99. };
  100. static const u32 golden_settings_polaris11_a11[] =
  101. {
  102. mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  103. mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  104. mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  105. mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  106. mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  107. mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  108. mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  109. mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  110. mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  111. mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  112. };
  113. static const u32 golden_settings_polaris10_a11[] =
  114. {
  115. mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  116. mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  117. mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  118. mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  119. mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  120. mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  121. mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  122. mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  123. mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  124. mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  125. };
  126. static const u32 cz_golden_settings_a11[] =
  127. {
  128. mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  129. mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  130. mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
  131. mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
  132. mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
  133. mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
  134. mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  135. mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  136. mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
  137. mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
  138. mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
  139. mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
  140. };
  141. static const u32 cz_mgcg_cgcg_init[] =
  142. {
  143. mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  144. mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  145. };
  146. static const u32 stoney_golden_settings_a11[] =
  147. {
  148. mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
  149. mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
  150. mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
  151. mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
  152. };
  153. static const u32 stoney_mgcg_cgcg_init[] =
  154. {
  155. mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
  156. };
  157. /*
  158. * sDMA - System DMA
  159. * Starting with CIK, the GPU has new asynchronous
  160. * DMA engines. These engines are used for compute
  161. * and gfx. There are two DMA engines (SDMA0, SDMA1)
  162. * and each one supports 1 ring buffer used for gfx
  163. * and 2 queues used for compute.
  164. *
  165. * The programming model is very similar to the CP
  166. * (ring buffer, IBs, etc.), but sDMA has it's own
  167. * packet format that is different from the PM4 format
  168. * used by the CP. sDMA supports copying data, writing
  169. * embedded data, solid fills, and a number of other
  170. * things. It also has support for tiling/detiling of
  171. * buffers.
  172. */
  173. static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
  174. {
  175. switch (adev->asic_type) {
  176. case CHIP_FIJI:
  177. amdgpu_device_program_register_sequence(adev,
  178. fiji_mgcg_cgcg_init,
  179. ARRAY_SIZE(fiji_mgcg_cgcg_init));
  180. amdgpu_device_program_register_sequence(adev,
  181. golden_settings_fiji_a10,
  182. ARRAY_SIZE(golden_settings_fiji_a10));
  183. break;
  184. case CHIP_TONGA:
  185. amdgpu_device_program_register_sequence(adev,
  186. tonga_mgcg_cgcg_init,
  187. ARRAY_SIZE(tonga_mgcg_cgcg_init));
  188. amdgpu_device_program_register_sequence(adev,
  189. golden_settings_tonga_a11,
  190. ARRAY_SIZE(golden_settings_tonga_a11));
  191. break;
  192. case CHIP_POLARIS11:
  193. case CHIP_POLARIS12:
  194. case CHIP_VEGAM:
  195. amdgpu_device_program_register_sequence(adev,
  196. golden_settings_polaris11_a11,
  197. ARRAY_SIZE(golden_settings_polaris11_a11));
  198. break;
  199. case CHIP_POLARIS10:
  200. amdgpu_device_program_register_sequence(adev,
  201. golden_settings_polaris10_a11,
  202. ARRAY_SIZE(golden_settings_polaris10_a11));
  203. break;
  204. case CHIP_CARRIZO:
  205. amdgpu_device_program_register_sequence(adev,
  206. cz_mgcg_cgcg_init,
  207. ARRAY_SIZE(cz_mgcg_cgcg_init));
  208. amdgpu_device_program_register_sequence(adev,
  209. cz_golden_settings_a11,
  210. ARRAY_SIZE(cz_golden_settings_a11));
  211. break;
  212. case CHIP_STONEY:
  213. amdgpu_device_program_register_sequence(adev,
  214. stoney_mgcg_cgcg_init,
  215. ARRAY_SIZE(stoney_mgcg_cgcg_init));
  216. amdgpu_device_program_register_sequence(adev,
  217. stoney_golden_settings_a11,
  218. ARRAY_SIZE(stoney_golden_settings_a11));
  219. break;
  220. default:
  221. break;
  222. }
  223. }
  224. static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
  225. {
  226. int i;
  227. for (i = 0; i < adev->sdma.num_instances; i++) {
  228. release_firmware(adev->sdma.instance[i].fw);
  229. adev->sdma.instance[i].fw = NULL;
  230. }
  231. }
  232. /**
  233. * sdma_v3_0_init_microcode - load ucode images from disk
  234. *
  235. * @adev: amdgpu_device pointer
  236. *
  237. * Use the firmware interface to load the ucode images into
  238. * the driver (not loaded into hw).
  239. * Returns 0 on success, error on failure.
  240. */
  241. static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
  242. {
  243. const char *chip_name;
  244. char fw_name[30];
  245. int err = 0, i;
  246. struct amdgpu_firmware_info *info = NULL;
  247. const struct common_firmware_header *header = NULL;
  248. const struct sdma_firmware_header_v1_0 *hdr;
  249. DRM_DEBUG("\n");
  250. switch (adev->asic_type) {
  251. case CHIP_TONGA:
  252. chip_name = "tonga";
  253. break;
  254. case CHIP_FIJI:
  255. chip_name = "fiji";
  256. break;
  257. case CHIP_POLARIS10:
  258. chip_name = "polaris10";
  259. break;
  260. case CHIP_POLARIS11:
  261. chip_name = "polaris11";
  262. break;
  263. case CHIP_POLARIS12:
  264. chip_name = "polaris12";
  265. break;
  266. case CHIP_VEGAM:
  267. chip_name = "vegam";
  268. break;
  269. case CHIP_CARRIZO:
  270. chip_name = "carrizo";
  271. break;
  272. case CHIP_STONEY:
  273. chip_name = "stoney";
  274. break;
  275. default: BUG();
  276. }
  277. for (i = 0; i < adev->sdma.num_instances; i++) {
  278. if (i == 0)
  279. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
  280. else
  281. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
  282. err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
  283. if (err)
  284. goto out;
  285. err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
  286. if (err)
  287. goto out;
  288. hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
  289. adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
  290. adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
  291. if (adev->sdma.instance[i].feature_version >= 20)
  292. adev->sdma.instance[i].burst_nop = true;
  293. if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
  294. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
  295. info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
  296. info->fw = adev->sdma.instance[i].fw;
  297. header = (const struct common_firmware_header *)info->fw->data;
  298. adev->firmware.fw_size +=
  299. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  300. }
  301. }
  302. out:
  303. if (err) {
  304. pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
  305. for (i = 0; i < adev->sdma.num_instances; i++) {
  306. release_firmware(adev->sdma.instance[i].fw);
  307. adev->sdma.instance[i].fw = NULL;
  308. }
  309. }
  310. return err;
  311. }
  312. /**
  313. * sdma_v3_0_ring_get_rptr - get the current read pointer
  314. *
  315. * @ring: amdgpu ring pointer
  316. *
  317. * Get the current rptr from the hardware (VI+).
  318. */
  319. static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
  320. {
  321. /* XXX check if swapping is necessary on BE */
  322. return ring->adev->wb.wb[ring->rptr_offs] >> 2;
  323. }
  324. /**
  325. * sdma_v3_0_ring_get_wptr - get the current write pointer
  326. *
  327. * @ring: amdgpu ring pointer
  328. *
  329. * Get the current wptr from the hardware (VI+).
  330. */
  331. static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
  332. {
  333. struct amdgpu_device *adev = ring->adev;
  334. u32 wptr;
  335. if (ring->use_doorbell || ring->use_pollmem) {
  336. /* XXX check if swapping is necessary on BE */
  337. wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
  338. } else {
  339. wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
  340. }
  341. return wptr;
  342. }
  343. /**
  344. * sdma_v3_0_ring_set_wptr - commit the write pointer
  345. *
  346. * @ring: amdgpu ring pointer
  347. *
  348. * Write the wptr back to the hardware (VI+).
  349. */
  350. static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
  351. {
  352. struct amdgpu_device *adev = ring->adev;
  353. if (ring->use_doorbell) {
  354. u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
  355. /* XXX check if swapping is necessary on BE */
  356. WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
  357. WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
  358. } else if (ring->use_pollmem) {
  359. u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
  360. WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
  361. } else {
  362. WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
  363. }
  364. }
  365. static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  366. {
  367. struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
  368. int i;
  369. for (i = 0; i < count; i++)
  370. if (sdma && sdma->burst_nop && (i == 0))
  371. amdgpu_ring_write(ring, ring->funcs->nop |
  372. SDMA_PKT_NOP_HEADER_COUNT(count - 1));
  373. else
  374. amdgpu_ring_write(ring, ring->funcs->nop);
  375. }
  376. /**
  377. * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
  378. *
  379. * @ring: amdgpu ring pointer
  380. * @ib: IB object to schedule
  381. *
  382. * Schedule an IB in the DMA ring (VI).
  383. */
  384. static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
  385. struct amdgpu_ib *ib,
  386. unsigned vmid, bool ctx_switch)
  387. {
  388. /* IB packet must end on a 8 DW boundary */
  389. sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
  390. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
  391. SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
  392. /* base must be 32 byte aligned */
  393. amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
  394. amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
  395. amdgpu_ring_write(ring, ib->length_dw);
  396. amdgpu_ring_write(ring, 0);
  397. amdgpu_ring_write(ring, 0);
  398. }
  399. /**
  400. * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
  401. *
  402. * @ring: amdgpu ring pointer
  403. *
  404. * Emit an hdp flush packet on the requested DMA ring.
  405. */
  406. static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
  407. {
  408. u32 ref_and_mask = 0;
  409. if (ring->me == 0)
  410. ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
  411. else
  412. ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
  413. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
  414. SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
  415. SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
  416. amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
  417. amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
  418. amdgpu_ring_write(ring, ref_and_mask); /* reference */
  419. amdgpu_ring_write(ring, ref_and_mask); /* mask */
  420. amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
  421. SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
  422. }
  423. /**
  424. * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
  425. *
  426. * @ring: amdgpu ring pointer
  427. * @fence: amdgpu fence object
  428. *
  429. * Add a DMA fence packet to the ring to write
  430. * the fence seq number and DMA trap packet to generate
  431. * an interrupt if needed (VI).
  432. */
  433. static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
  434. unsigned flags)
  435. {
  436. bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
  437. /* write the fence */
  438. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
  439. amdgpu_ring_write(ring, lower_32_bits(addr));
  440. amdgpu_ring_write(ring, upper_32_bits(addr));
  441. amdgpu_ring_write(ring, lower_32_bits(seq));
  442. /* optionally write high bits as well */
  443. if (write64bit) {
  444. addr += 4;
  445. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
  446. amdgpu_ring_write(ring, lower_32_bits(addr));
  447. amdgpu_ring_write(ring, upper_32_bits(addr));
  448. amdgpu_ring_write(ring, upper_32_bits(seq));
  449. }
  450. /* generate an interrupt */
  451. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
  452. amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
  453. }
  454. /**
  455. * sdma_v3_0_gfx_stop - stop the gfx async dma engines
  456. *
  457. * @adev: amdgpu_device pointer
  458. *
  459. * Stop the gfx async dma ring buffers (VI).
  460. */
  461. static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
  462. {
  463. struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
  464. struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
  465. u32 rb_cntl, ib_cntl;
  466. int i;
  467. if ((adev->mman.buffer_funcs_ring == sdma0) ||
  468. (adev->mman.buffer_funcs_ring == sdma1))
  469. amdgpu_ttm_set_buffer_funcs_status(adev, false);
  470. for (i = 0; i < adev->sdma.num_instances; i++) {
  471. rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
  472. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
  473. WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
  474. ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
  475. ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
  476. WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
  477. }
  478. sdma0->ready = false;
  479. sdma1->ready = false;
  480. }
  481. /**
  482. * sdma_v3_0_rlc_stop - stop the compute async dma engines
  483. *
  484. * @adev: amdgpu_device pointer
  485. *
  486. * Stop the compute async dma queues (VI).
  487. */
  488. static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
  489. {
  490. /* XXX todo */
  491. }
  492. /**
  493. * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
  494. *
  495. * @adev: amdgpu_device pointer
  496. * @enable: enable/disable the DMA MEs context switch.
  497. *
  498. * Halt or unhalt the async dma engines context switch (VI).
  499. */
  500. static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
  501. {
  502. u32 f32_cntl, phase_quantum = 0;
  503. int i;
  504. if (amdgpu_sdma_phase_quantum) {
  505. unsigned value = amdgpu_sdma_phase_quantum;
  506. unsigned unit = 0;
  507. while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
  508. SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
  509. value = (value + 1) >> 1;
  510. unit++;
  511. }
  512. if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
  513. SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
  514. value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
  515. SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
  516. unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
  517. SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
  518. WARN_ONCE(1,
  519. "clamping sdma_phase_quantum to %uK clock cycles\n",
  520. value << unit);
  521. }
  522. phase_quantum =
  523. value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
  524. unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
  525. }
  526. for (i = 0; i < adev->sdma.num_instances; i++) {
  527. f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
  528. if (enable) {
  529. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
  530. AUTO_CTXSW_ENABLE, 1);
  531. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
  532. ATC_L1_ENABLE, 1);
  533. if (amdgpu_sdma_phase_quantum) {
  534. WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
  535. phase_quantum);
  536. WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
  537. phase_quantum);
  538. }
  539. } else {
  540. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
  541. AUTO_CTXSW_ENABLE, 0);
  542. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
  543. ATC_L1_ENABLE, 1);
  544. }
  545. WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
  546. }
  547. }
  548. /**
  549. * sdma_v3_0_enable - stop the async dma engines
  550. *
  551. * @adev: amdgpu_device pointer
  552. * @enable: enable/disable the DMA MEs.
  553. *
  554. * Halt or unhalt the async dma engines (VI).
  555. */
  556. static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
  557. {
  558. u32 f32_cntl;
  559. int i;
  560. if (!enable) {
  561. sdma_v3_0_gfx_stop(adev);
  562. sdma_v3_0_rlc_stop(adev);
  563. }
  564. for (i = 0; i < adev->sdma.num_instances; i++) {
  565. f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
  566. if (enable)
  567. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
  568. else
  569. f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
  570. WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
  571. }
  572. }
  573. /**
  574. * sdma_v3_0_gfx_resume - setup and start the async dma engines
  575. *
  576. * @adev: amdgpu_device pointer
  577. *
  578. * Set up the gfx DMA ring buffers and enable them (VI).
  579. * Returns 0 for success, error for failure.
  580. */
  581. static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
  582. {
  583. struct amdgpu_ring *ring;
  584. u32 rb_cntl, ib_cntl, wptr_poll_cntl;
  585. u32 rb_bufsz;
  586. u32 wb_offset;
  587. u32 doorbell;
  588. u64 wptr_gpu_addr;
  589. int i, j, r;
  590. for (i = 0; i < adev->sdma.num_instances; i++) {
  591. ring = &adev->sdma.instance[i].ring;
  592. amdgpu_ring_clear_ring(ring);
  593. wb_offset = (ring->rptr_offs * 4);
  594. mutex_lock(&adev->srbm_mutex);
  595. for (j = 0; j < 16; j++) {
  596. vi_srbm_select(adev, 0, 0, 0, j);
  597. /* SDMA GFX */
  598. WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
  599. WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
  600. }
  601. vi_srbm_select(adev, 0, 0, 0, 0);
  602. mutex_unlock(&adev->srbm_mutex);
  603. WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
  604. adev->gfx.config.gb_addr_config & 0x70);
  605. WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
  606. /* Set ring buffer size in dwords */
  607. rb_bufsz = order_base_2(ring->ring_size / 4);
  608. rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
  609. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
  610. #ifdef __BIG_ENDIAN
  611. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
  612. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
  613. RPTR_WRITEBACK_SWAP_ENABLE, 1);
  614. #endif
  615. WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
  616. /* Initialize the ring buffer's read and write pointers */
  617. ring->wptr = 0;
  618. WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
  619. sdma_v3_0_ring_set_wptr(ring);
  620. WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
  621. WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
  622. /* set the wb address whether it's enabled or not */
  623. WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
  624. upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
  625. WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
  626. lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
  627. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
  628. WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
  629. WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
  630. doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
  631. if (ring->use_doorbell) {
  632. doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
  633. OFFSET, ring->doorbell_index);
  634. doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
  635. } else {
  636. doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
  637. }
  638. WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
  639. /* setup the wptr shadow polling */
  640. wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
  641. WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
  642. lower_32_bits(wptr_gpu_addr));
  643. WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
  644. upper_32_bits(wptr_gpu_addr));
  645. wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
  646. if (ring->use_pollmem) {
  647. /*wptr polling is not enogh fast, directly clean the wptr register */
  648. WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
  649. wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
  650. SDMA0_GFX_RB_WPTR_POLL_CNTL,
  651. ENABLE, 1);
  652. } else {
  653. wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
  654. SDMA0_GFX_RB_WPTR_POLL_CNTL,
  655. ENABLE, 0);
  656. }
  657. WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
  658. /* enable DMA RB */
  659. rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
  660. WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
  661. ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
  662. ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
  663. #ifdef __BIG_ENDIAN
  664. ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
  665. #endif
  666. /* enable DMA IBs */
  667. WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
  668. ring->ready = true;
  669. }
  670. /* unhalt the MEs */
  671. sdma_v3_0_enable(adev, true);
  672. /* enable sdma ring preemption */
  673. sdma_v3_0_ctx_switch_enable(adev, true);
  674. for (i = 0; i < adev->sdma.num_instances; i++) {
  675. ring = &adev->sdma.instance[i].ring;
  676. r = amdgpu_ring_test_ring(ring);
  677. if (r) {
  678. ring->ready = false;
  679. return r;
  680. }
  681. if (adev->mman.buffer_funcs_ring == ring)
  682. amdgpu_ttm_set_buffer_funcs_status(adev, true);
  683. }
  684. return 0;
  685. }
  686. /**
  687. * sdma_v3_0_rlc_resume - setup and start the async dma engines
  688. *
  689. * @adev: amdgpu_device pointer
  690. *
  691. * Set up the compute DMA queues and enable them (VI).
  692. * Returns 0 for success, error for failure.
  693. */
  694. static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
  695. {
  696. /* XXX todo */
  697. return 0;
  698. }
  699. /**
  700. * sdma_v3_0_load_microcode - load the sDMA ME ucode
  701. *
  702. * @adev: amdgpu_device pointer
  703. *
  704. * Loads the sDMA0/1 ucode.
  705. * Returns 0 for success, -EINVAL if the ucode is not available.
  706. */
  707. static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
  708. {
  709. const struct sdma_firmware_header_v1_0 *hdr;
  710. const __le32 *fw_data;
  711. u32 fw_size;
  712. int i, j;
  713. /* halt the MEs */
  714. sdma_v3_0_enable(adev, false);
  715. for (i = 0; i < adev->sdma.num_instances; i++) {
  716. if (!adev->sdma.instance[i].fw)
  717. return -EINVAL;
  718. hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
  719. amdgpu_ucode_print_sdma_hdr(&hdr->header);
  720. fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
  721. fw_data = (const __le32 *)
  722. (adev->sdma.instance[i].fw->data +
  723. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  724. WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
  725. for (j = 0; j < fw_size; j++)
  726. WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
  727. WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
  728. }
  729. return 0;
  730. }
  731. /**
  732. * sdma_v3_0_start - setup and start the async dma engines
  733. *
  734. * @adev: amdgpu_device pointer
  735. *
  736. * Set up the DMA engines and enable them (VI).
  737. * Returns 0 for success, error for failure.
  738. */
  739. static int sdma_v3_0_start(struct amdgpu_device *adev)
  740. {
  741. int r;
  742. if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
  743. r = sdma_v3_0_load_microcode(adev);
  744. if (r)
  745. return r;
  746. }
  747. /* disable sdma engine before programing it */
  748. sdma_v3_0_ctx_switch_enable(adev, false);
  749. sdma_v3_0_enable(adev, false);
  750. /* start the gfx rings and rlc compute queues */
  751. r = sdma_v3_0_gfx_resume(adev);
  752. if (r)
  753. return r;
  754. r = sdma_v3_0_rlc_resume(adev);
  755. if (r)
  756. return r;
  757. return 0;
  758. }
  759. /**
  760. * sdma_v3_0_ring_test_ring - simple async dma engine test
  761. *
  762. * @ring: amdgpu_ring structure holding ring information
  763. *
  764. * Test the DMA engine by writing using it to write an
  765. * value to memory. (VI).
  766. * Returns 0 for success, error for failure.
  767. */
  768. static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
  769. {
  770. struct amdgpu_device *adev = ring->adev;
  771. unsigned i;
  772. unsigned index;
  773. int r;
  774. u32 tmp;
  775. u64 gpu_addr;
  776. r = amdgpu_device_wb_get(adev, &index);
  777. if (r) {
  778. dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
  779. return r;
  780. }
  781. gpu_addr = adev->wb.gpu_addr + (index * 4);
  782. tmp = 0xCAFEDEAD;
  783. adev->wb.wb[index] = cpu_to_le32(tmp);
  784. r = amdgpu_ring_alloc(ring, 5);
  785. if (r) {
  786. DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
  787. amdgpu_device_wb_free(adev, index);
  788. return r;
  789. }
  790. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
  791. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
  792. amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
  793. amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
  794. amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
  795. amdgpu_ring_write(ring, 0xDEADBEEF);
  796. amdgpu_ring_commit(ring);
  797. for (i = 0; i < adev->usec_timeout; i++) {
  798. tmp = le32_to_cpu(adev->wb.wb[index]);
  799. if (tmp == 0xDEADBEEF)
  800. break;
  801. DRM_UDELAY(1);
  802. }
  803. if (i < adev->usec_timeout) {
  804. DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
  805. } else {
  806. DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
  807. ring->idx, tmp);
  808. r = -EINVAL;
  809. }
  810. amdgpu_device_wb_free(adev, index);
  811. return r;
  812. }
  813. /**
  814. * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
  815. *
  816. * @ring: amdgpu_ring structure holding ring information
  817. *
  818. * Test a simple IB in the DMA ring (VI).
  819. * Returns 0 on success, error on failure.
  820. */
  821. static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
  822. {
  823. struct amdgpu_device *adev = ring->adev;
  824. struct amdgpu_ib ib;
  825. struct dma_fence *f = NULL;
  826. unsigned index;
  827. u32 tmp = 0;
  828. u64 gpu_addr;
  829. long r;
  830. r = amdgpu_device_wb_get(adev, &index);
  831. if (r) {
  832. dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
  833. return r;
  834. }
  835. gpu_addr = adev->wb.gpu_addr + (index * 4);
  836. tmp = 0xCAFEDEAD;
  837. adev->wb.wb[index] = cpu_to_le32(tmp);
  838. memset(&ib, 0, sizeof(ib));
  839. r = amdgpu_ib_get(adev, NULL, 256, &ib);
  840. if (r) {
  841. DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
  842. goto err0;
  843. }
  844. ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
  845. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
  846. ib.ptr[1] = lower_32_bits(gpu_addr);
  847. ib.ptr[2] = upper_32_bits(gpu_addr);
  848. ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
  849. ib.ptr[4] = 0xDEADBEEF;
  850. ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
  851. ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
  852. ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
  853. ib.length_dw = 8;
  854. r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
  855. if (r)
  856. goto err1;
  857. r = dma_fence_wait_timeout(f, false, timeout);
  858. if (r == 0) {
  859. DRM_ERROR("amdgpu: IB test timed out\n");
  860. r = -ETIMEDOUT;
  861. goto err1;
  862. } else if (r < 0) {
  863. DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
  864. goto err1;
  865. }
  866. tmp = le32_to_cpu(adev->wb.wb[index]);
  867. if (tmp == 0xDEADBEEF) {
  868. DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
  869. r = 0;
  870. } else {
  871. DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
  872. r = -EINVAL;
  873. }
  874. err1:
  875. amdgpu_ib_free(adev, &ib, NULL);
  876. dma_fence_put(f);
  877. err0:
  878. amdgpu_device_wb_free(adev, index);
  879. return r;
  880. }
  881. /**
  882. * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
  883. *
  884. * @ib: indirect buffer to fill with commands
  885. * @pe: addr of the page entry
  886. * @src: src addr to copy from
  887. * @count: number of page entries to update
  888. *
  889. * Update PTEs by copying them from the GART using sDMA (CIK).
  890. */
  891. static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
  892. uint64_t pe, uint64_t src,
  893. unsigned count)
  894. {
  895. unsigned bytes = count * 8;
  896. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
  897. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
  898. ib->ptr[ib->length_dw++] = bytes;
  899. ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
  900. ib->ptr[ib->length_dw++] = lower_32_bits(src);
  901. ib->ptr[ib->length_dw++] = upper_32_bits(src);
  902. ib->ptr[ib->length_dw++] = lower_32_bits(pe);
  903. ib->ptr[ib->length_dw++] = upper_32_bits(pe);
  904. }
  905. /**
  906. * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
  907. *
  908. * @ib: indirect buffer to fill with commands
  909. * @pe: addr of the page entry
  910. * @value: dst addr to write into pe
  911. * @count: number of page entries to update
  912. * @incr: increase next addr by incr bytes
  913. *
  914. * Update PTEs by writing them manually using sDMA (CIK).
  915. */
  916. static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
  917. uint64_t value, unsigned count,
  918. uint32_t incr)
  919. {
  920. unsigned ndw = count * 2;
  921. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
  922. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
  923. ib->ptr[ib->length_dw++] = lower_32_bits(pe);
  924. ib->ptr[ib->length_dw++] = upper_32_bits(pe);
  925. ib->ptr[ib->length_dw++] = ndw;
  926. for (; ndw > 0; ndw -= 2) {
  927. ib->ptr[ib->length_dw++] = lower_32_bits(value);
  928. ib->ptr[ib->length_dw++] = upper_32_bits(value);
  929. value += incr;
  930. }
  931. }
  932. /**
  933. * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
  934. *
  935. * @ib: indirect buffer to fill with commands
  936. * @pe: addr of the page entry
  937. * @addr: dst addr to write into pe
  938. * @count: number of page entries to update
  939. * @incr: increase next addr by incr bytes
  940. * @flags: access flags
  941. *
  942. * Update the page tables using sDMA (CIK).
  943. */
  944. static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
  945. uint64_t addr, unsigned count,
  946. uint32_t incr, uint64_t flags)
  947. {
  948. /* for physically contiguous pages (vram) */
  949. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
  950. ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
  951. ib->ptr[ib->length_dw++] = upper_32_bits(pe);
  952. ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
  953. ib->ptr[ib->length_dw++] = upper_32_bits(flags);
  954. ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
  955. ib->ptr[ib->length_dw++] = upper_32_bits(addr);
  956. ib->ptr[ib->length_dw++] = incr; /* increment size */
  957. ib->ptr[ib->length_dw++] = 0;
  958. ib->ptr[ib->length_dw++] = count; /* number of entries */
  959. }
  960. /**
  961. * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
  962. *
  963. * @ib: indirect buffer to fill with padding
  964. *
  965. */
  966. static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
  967. {
  968. struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
  969. u32 pad_count;
  970. int i;
  971. pad_count = (8 - (ib->length_dw & 0x7)) % 8;
  972. for (i = 0; i < pad_count; i++)
  973. if (sdma && sdma->burst_nop && (i == 0))
  974. ib->ptr[ib->length_dw++] =
  975. SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
  976. SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
  977. else
  978. ib->ptr[ib->length_dw++] =
  979. SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
  980. }
  981. /**
  982. * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
  983. *
  984. * @ring: amdgpu_ring pointer
  985. *
  986. * Make sure all previous operations are completed (CIK).
  987. */
  988. static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
  989. {
  990. uint32_t seq = ring->fence_drv.sync_seq;
  991. uint64_t addr = ring->fence_drv.gpu_addr;
  992. /* wait for idle */
  993. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
  994. SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
  995. SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
  996. SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
  997. amdgpu_ring_write(ring, addr & 0xfffffffc);
  998. amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
  999. amdgpu_ring_write(ring, seq); /* reference */
  1000. amdgpu_ring_write(ring, 0xffffffff); /* mask */
  1001. amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
  1002. SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
  1003. }
  1004. /**
  1005. * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
  1006. *
  1007. * @ring: amdgpu_ring pointer
  1008. * @vm: amdgpu_vm pointer
  1009. *
  1010. * Update the page table base and flush the VM TLB
  1011. * using sDMA (VI).
  1012. */
  1013. static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
  1014. unsigned vmid, uint64_t pd_addr)
  1015. {
  1016. amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
  1017. /* wait for flush */
  1018. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
  1019. SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
  1020. SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
  1021. amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
  1022. amdgpu_ring_write(ring, 0);
  1023. amdgpu_ring_write(ring, 0); /* reference */
  1024. amdgpu_ring_write(ring, 0); /* mask */
  1025. amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
  1026. SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
  1027. }
  1028. static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
  1029. uint32_t reg, uint32_t val)
  1030. {
  1031. amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
  1032. SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
  1033. amdgpu_ring_write(ring, reg);
  1034. amdgpu_ring_write(ring, val);
  1035. }
  1036. static int sdma_v3_0_early_init(void *handle)
  1037. {
  1038. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1039. switch (adev->asic_type) {
  1040. case CHIP_STONEY:
  1041. adev->sdma.num_instances = 1;
  1042. break;
  1043. default:
  1044. adev->sdma.num_instances = SDMA_MAX_INSTANCE;
  1045. break;
  1046. }
  1047. sdma_v3_0_set_ring_funcs(adev);
  1048. sdma_v3_0_set_buffer_funcs(adev);
  1049. sdma_v3_0_set_vm_pte_funcs(adev);
  1050. sdma_v3_0_set_irq_funcs(adev);
  1051. return 0;
  1052. }
  1053. static int sdma_v3_0_sw_init(void *handle)
  1054. {
  1055. struct amdgpu_ring *ring;
  1056. int r, i;
  1057. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1058. /* SDMA trap event */
  1059. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
  1060. &adev->sdma.trap_irq);
  1061. if (r)
  1062. return r;
  1063. /* SDMA Privileged inst */
  1064. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
  1065. &adev->sdma.illegal_inst_irq);
  1066. if (r)
  1067. return r;
  1068. /* SDMA Privileged inst */
  1069. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
  1070. &adev->sdma.illegal_inst_irq);
  1071. if (r)
  1072. return r;
  1073. r = sdma_v3_0_init_microcode(adev);
  1074. if (r) {
  1075. DRM_ERROR("Failed to load sdma firmware!\n");
  1076. return r;
  1077. }
  1078. for (i = 0; i < adev->sdma.num_instances; i++) {
  1079. ring = &adev->sdma.instance[i].ring;
  1080. ring->ring_obj = NULL;
  1081. if (!amdgpu_sriov_vf(adev)) {
  1082. ring->use_doorbell = true;
  1083. ring->doorbell_index = (i == 0) ?
  1084. AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
  1085. } else {
  1086. ring->use_pollmem = true;
  1087. }
  1088. sprintf(ring->name, "sdma%d", i);
  1089. r = amdgpu_ring_init(adev, ring, 1024,
  1090. &adev->sdma.trap_irq,
  1091. (i == 0) ?
  1092. AMDGPU_SDMA_IRQ_TRAP0 :
  1093. AMDGPU_SDMA_IRQ_TRAP1);
  1094. if (r)
  1095. return r;
  1096. }
  1097. return r;
  1098. }
  1099. static int sdma_v3_0_sw_fini(void *handle)
  1100. {
  1101. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1102. int i;
  1103. for (i = 0; i < adev->sdma.num_instances; i++)
  1104. amdgpu_ring_fini(&adev->sdma.instance[i].ring);
  1105. sdma_v3_0_free_microcode(adev);
  1106. return 0;
  1107. }
  1108. static int sdma_v3_0_hw_init(void *handle)
  1109. {
  1110. int r;
  1111. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1112. sdma_v3_0_init_golden_registers(adev);
  1113. r = sdma_v3_0_start(adev);
  1114. if (r)
  1115. return r;
  1116. return r;
  1117. }
  1118. static int sdma_v3_0_hw_fini(void *handle)
  1119. {
  1120. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1121. sdma_v3_0_ctx_switch_enable(adev, false);
  1122. sdma_v3_0_enable(adev, false);
  1123. return 0;
  1124. }
  1125. static int sdma_v3_0_suspend(void *handle)
  1126. {
  1127. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1128. return sdma_v3_0_hw_fini(adev);
  1129. }
  1130. static int sdma_v3_0_resume(void *handle)
  1131. {
  1132. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1133. return sdma_v3_0_hw_init(adev);
  1134. }
  1135. static bool sdma_v3_0_is_idle(void *handle)
  1136. {
  1137. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1138. u32 tmp = RREG32(mmSRBM_STATUS2);
  1139. if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
  1140. SRBM_STATUS2__SDMA1_BUSY_MASK))
  1141. return false;
  1142. return true;
  1143. }
  1144. static int sdma_v3_0_wait_for_idle(void *handle)
  1145. {
  1146. unsigned i;
  1147. u32 tmp;
  1148. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1149. for (i = 0; i < adev->usec_timeout; i++) {
  1150. tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
  1151. SRBM_STATUS2__SDMA1_BUSY_MASK);
  1152. if (!tmp)
  1153. return 0;
  1154. udelay(1);
  1155. }
  1156. return -ETIMEDOUT;
  1157. }
  1158. static bool sdma_v3_0_check_soft_reset(void *handle)
  1159. {
  1160. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1161. u32 srbm_soft_reset = 0;
  1162. u32 tmp = RREG32(mmSRBM_STATUS2);
  1163. if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
  1164. (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
  1165. srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
  1166. srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
  1167. }
  1168. if (srbm_soft_reset) {
  1169. adev->sdma.srbm_soft_reset = srbm_soft_reset;
  1170. return true;
  1171. } else {
  1172. adev->sdma.srbm_soft_reset = 0;
  1173. return false;
  1174. }
  1175. }
  1176. static int sdma_v3_0_pre_soft_reset(void *handle)
  1177. {
  1178. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1179. u32 srbm_soft_reset = 0;
  1180. if (!adev->sdma.srbm_soft_reset)
  1181. return 0;
  1182. srbm_soft_reset = adev->sdma.srbm_soft_reset;
  1183. if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
  1184. REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
  1185. sdma_v3_0_ctx_switch_enable(adev, false);
  1186. sdma_v3_0_enable(adev, false);
  1187. }
  1188. return 0;
  1189. }
  1190. static int sdma_v3_0_post_soft_reset(void *handle)
  1191. {
  1192. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1193. u32 srbm_soft_reset = 0;
  1194. if (!adev->sdma.srbm_soft_reset)
  1195. return 0;
  1196. srbm_soft_reset = adev->sdma.srbm_soft_reset;
  1197. if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
  1198. REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
  1199. sdma_v3_0_gfx_resume(adev);
  1200. sdma_v3_0_rlc_resume(adev);
  1201. }
  1202. return 0;
  1203. }
  1204. static int sdma_v3_0_soft_reset(void *handle)
  1205. {
  1206. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1207. u32 srbm_soft_reset = 0;
  1208. u32 tmp;
  1209. if (!adev->sdma.srbm_soft_reset)
  1210. return 0;
  1211. srbm_soft_reset = adev->sdma.srbm_soft_reset;
  1212. if (srbm_soft_reset) {
  1213. tmp = RREG32(mmSRBM_SOFT_RESET);
  1214. tmp |= srbm_soft_reset;
  1215. dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
  1216. WREG32(mmSRBM_SOFT_RESET, tmp);
  1217. tmp = RREG32(mmSRBM_SOFT_RESET);
  1218. udelay(50);
  1219. tmp &= ~srbm_soft_reset;
  1220. WREG32(mmSRBM_SOFT_RESET, tmp);
  1221. tmp = RREG32(mmSRBM_SOFT_RESET);
  1222. /* Wait a little for things to settle down */
  1223. udelay(50);
  1224. }
  1225. return 0;
  1226. }
  1227. static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
  1228. struct amdgpu_irq_src *source,
  1229. unsigned type,
  1230. enum amdgpu_interrupt_state state)
  1231. {
  1232. u32 sdma_cntl;
  1233. switch (type) {
  1234. case AMDGPU_SDMA_IRQ_TRAP0:
  1235. switch (state) {
  1236. case AMDGPU_IRQ_STATE_DISABLE:
  1237. sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
  1238. sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
  1239. WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
  1240. break;
  1241. case AMDGPU_IRQ_STATE_ENABLE:
  1242. sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
  1243. sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
  1244. WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
  1245. break;
  1246. default:
  1247. break;
  1248. }
  1249. break;
  1250. case AMDGPU_SDMA_IRQ_TRAP1:
  1251. switch (state) {
  1252. case AMDGPU_IRQ_STATE_DISABLE:
  1253. sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
  1254. sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
  1255. WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
  1256. break;
  1257. case AMDGPU_IRQ_STATE_ENABLE:
  1258. sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
  1259. sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
  1260. WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
  1261. break;
  1262. default:
  1263. break;
  1264. }
  1265. break;
  1266. default:
  1267. break;
  1268. }
  1269. return 0;
  1270. }
  1271. static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
  1272. struct amdgpu_irq_src *source,
  1273. struct amdgpu_iv_entry *entry)
  1274. {
  1275. u8 instance_id, queue_id;
  1276. instance_id = (entry->ring_id & 0x3) >> 0;
  1277. queue_id = (entry->ring_id & 0xc) >> 2;
  1278. DRM_DEBUG("IH: SDMA trap\n");
  1279. switch (instance_id) {
  1280. case 0:
  1281. switch (queue_id) {
  1282. case 0:
  1283. amdgpu_fence_process(&adev->sdma.instance[0].ring);
  1284. break;
  1285. case 1:
  1286. /* XXX compute */
  1287. break;
  1288. case 2:
  1289. /* XXX compute */
  1290. break;
  1291. }
  1292. break;
  1293. case 1:
  1294. switch (queue_id) {
  1295. case 0:
  1296. amdgpu_fence_process(&adev->sdma.instance[1].ring);
  1297. break;
  1298. case 1:
  1299. /* XXX compute */
  1300. break;
  1301. case 2:
  1302. /* XXX compute */
  1303. break;
  1304. }
  1305. break;
  1306. }
  1307. return 0;
  1308. }
  1309. static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
  1310. struct amdgpu_irq_src *source,
  1311. struct amdgpu_iv_entry *entry)
  1312. {
  1313. DRM_ERROR("Illegal instruction in SDMA command stream\n");
  1314. schedule_work(&adev->reset_work);
  1315. return 0;
  1316. }
  1317. static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
  1318. struct amdgpu_device *adev,
  1319. bool enable)
  1320. {
  1321. uint32_t temp, data;
  1322. int i;
  1323. if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
  1324. for (i = 0; i < adev->sdma.num_instances; i++) {
  1325. temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
  1326. data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
  1327. SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
  1328. SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
  1329. SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
  1330. SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
  1331. SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
  1332. SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
  1333. SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
  1334. if (data != temp)
  1335. WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
  1336. }
  1337. } else {
  1338. for (i = 0; i < adev->sdma.num_instances; i++) {
  1339. temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
  1340. data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
  1341. SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
  1342. SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
  1343. SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
  1344. SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
  1345. SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
  1346. SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
  1347. SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
  1348. if (data != temp)
  1349. WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
  1350. }
  1351. }
  1352. }
  1353. static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
  1354. struct amdgpu_device *adev,
  1355. bool enable)
  1356. {
  1357. uint32_t temp, data;
  1358. int i;
  1359. if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
  1360. for (i = 0; i < adev->sdma.num_instances; i++) {
  1361. temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
  1362. data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
  1363. if (temp != data)
  1364. WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
  1365. }
  1366. } else {
  1367. for (i = 0; i < adev->sdma.num_instances; i++) {
  1368. temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
  1369. data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
  1370. if (temp != data)
  1371. WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
  1372. }
  1373. }
  1374. }
  1375. static int sdma_v3_0_set_clockgating_state(void *handle,
  1376. enum amd_clockgating_state state)
  1377. {
  1378. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1379. if (amdgpu_sriov_vf(adev))
  1380. return 0;
  1381. switch (adev->asic_type) {
  1382. case CHIP_FIJI:
  1383. case CHIP_CARRIZO:
  1384. case CHIP_STONEY:
  1385. sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
  1386. state == AMD_CG_STATE_GATE);
  1387. sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
  1388. state == AMD_CG_STATE_GATE);
  1389. break;
  1390. default:
  1391. break;
  1392. }
  1393. return 0;
  1394. }
  1395. static int sdma_v3_0_set_powergating_state(void *handle,
  1396. enum amd_powergating_state state)
  1397. {
  1398. return 0;
  1399. }
  1400. static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
  1401. {
  1402. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1403. int data;
  1404. if (amdgpu_sriov_vf(adev))
  1405. *flags = 0;
  1406. /* AMD_CG_SUPPORT_SDMA_MGCG */
  1407. data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
  1408. if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
  1409. *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
  1410. /* AMD_CG_SUPPORT_SDMA_LS */
  1411. data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
  1412. if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
  1413. *flags |= AMD_CG_SUPPORT_SDMA_LS;
  1414. }
  1415. static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
  1416. .name = "sdma_v3_0",
  1417. .early_init = sdma_v3_0_early_init,
  1418. .late_init = NULL,
  1419. .sw_init = sdma_v3_0_sw_init,
  1420. .sw_fini = sdma_v3_0_sw_fini,
  1421. .hw_init = sdma_v3_0_hw_init,
  1422. .hw_fini = sdma_v3_0_hw_fini,
  1423. .suspend = sdma_v3_0_suspend,
  1424. .resume = sdma_v3_0_resume,
  1425. .is_idle = sdma_v3_0_is_idle,
  1426. .wait_for_idle = sdma_v3_0_wait_for_idle,
  1427. .check_soft_reset = sdma_v3_0_check_soft_reset,
  1428. .pre_soft_reset = sdma_v3_0_pre_soft_reset,
  1429. .post_soft_reset = sdma_v3_0_post_soft_reset,
  1430. .soft_reset = sdma_v3_0_soft_reset,
  1431. .set_clockgating_state = sdma_v3_0_set_clockgating_state,
  1432. .set_powergating_state = sdma_v3_0_set_powergating_state,
  1433. .get_clockgating_state = sdma_v3_0_get_clockgating_state,
  1434. };
  1435. static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
  1436. .type = AMDGPU_RING_TYPE_SDMA,
  1437. .align_mask = 0xf,
  1438. .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
  1439. .support_64bit_ptrs = false,
  1440. .get_rptr = sdma_v3_0_ring_get_rptr,
  1441. .get_wptr = sdma_v3_0_ring_get_wptr,
  1442. .set_wptr = sdma_v3_0_ring_set_wptr,
  1443. .emit_frame_size =
  1444. 6 + /* sdma_v3_0_ring_emit_hdp_flush */
  1445. 3 + /* hdp invalidate */
  1446. 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
  1447. VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
  1448. 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
  1449. .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
  1450. .emit_ib = sdma_v3_0_ring_emit_ib,
  1451. .emit_fence = sdma_v3_0_ring_emit_fence,
  1452. .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
  1453. .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
  1454. .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
  1455. .test_ring = sdma_v3_0_ring_test_ring,
  1456. .test_ib = sdma_v3_0_ring_test_ib,
  1457. .insert_nop = sdma_v3_0_ring_insert_nop,
  1458. .pad_ib = sdma_v3_0_ring_pad_ib,
  1459. .emit_wreg = sdma_v3_0_ring_emit_wreg,
  1460. };
  1461. static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
  1462. {
  1463. int i;
  1464. for (i = 0; i < adev->sdma.num_instances; i++) {
  1465. adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
  1466. adev->sdma.instance[i].ring.me = i;
  1467. }
  1468. }
  1469. static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
  1470. .set = sdma_v3_0_set_trap_irq_state,
  1471. .process = sdma_v3_0_process_trap_irq,
  1472. };
  1473. static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
  1474. .process = sdma_v3_0_process_illegal_inst_irq,
  1475. };
  1476. static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
  1477. {
  1478. adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
  1479. adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
  1480. adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
  1481. }
  1482. /**
  1483. * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
  1484. *
  1485. * @ring: amdgpu_ring structure holding ring information
  1486. * @src_offset: src GPU address
  1487. * @dst_offset: dst GPU address
  1488. * @byte_count: number of bytes to xfer
  1489. *
  1490. * Copy GPU buffers using the DMA engine (VI).
  1491. * Used by the amdgpu ttm implementation to move pages if
  1492. * registered as the asic copy callback.
  1493. */
  1494. static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
  1495. uint64_t src_offset,
  1496. uint64_t dst_offset,
  1497. uint32_t byte_count)
  1498. {
  1499. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
  1500. SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
  1501. ib->ptr[ib->length_dw++] = byte_count;
  1502. ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
  1503. ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
  1504. ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
  1505. ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
  1506. ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
  1507. }
  1508. /**
  1509. * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
  1510. *
  1511. * @ring: amdgpu_ring structure holding ring information
  1512. * @src_data: value to write to buffer
  1513. * @dst_offset: dst GPU address
  1514. * @byte_count: number of bytes to xfer
  1515. *
  1516. * Fill GPU buffers using the DMA engine (VI).
  1517. */
  1518. static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
  1519. uint32_t src_data,
  1520. uint64_t dst_offset,
  1521. uint32_t byte_count)
  1522. {
  1523. ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
  1524. ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
  1525. ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
  1526. ib->ptr[ib->length_dw++] = src_data;
  1527. ib->ptr[ib->length_dw++] = byte_count;
  1528. }
  1529. static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
  1530. .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
  1531. .copy_num_dw = 7,
  1532. .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
  1533. .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
  1534. .fill_num_dw = 5,
  1535. .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
  1536. };
  1537. static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
  1538. {
  1539. if (adev->mman.buffer_funcs == NULL) {
  1540. adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
  1541. adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
  1542. }
  1543. }
  1544. static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
  1545. .copy_pte_num_dw = 7,
  1546. .copy_pte = sdma_v3_0_vm_copy_pte,
  1547. .write_pte = sdma_v3_0_vm_write_pte,
  1548. .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
  1549. };
  1550. static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
  1551. {
  1552. unsigned i;
  1553. if (adev->vm_manager.vm_pte_funcs == NULL) {
  1554. adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
  1555. for (i = 0; i < adev->sdma.num_instances; i++)
  1556. adev->vm_manager.vm_pte_rings[i] =
  1557. &adev->sdma.instance[i].ring;
  1558. adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
  1559. }
  1560. }
  1561. const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
  1562. {
  1563. .type = AMD_IP_BLOCK_TYPE_SDMA,
  1564. .major = 3,
  1565. .minor = 0,
  1566. .rev = 0,
  1567. .funcs = &sdma_v3_0_ip_funcs,
  1568. };
  1569. const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
  1570. {
  1571. .type = AMD_IP_BLOCK_TYPE_SDMA,
  1572. .major = 3,
  1573. .minor = 1,
  1574. .rev = 0,
  1575. .funcs = &sdma_v3_0_ip_funcs,
  1576. };