gpio-vf610.c 8.1 KB

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  1. /*
  2. * Freescale vf610 GPIO support through PORT and GPIO
  3. *
  4. * Copyright (c) 2014 Toradex AG.
  5. *
  6. * Author: Stefan Agner <stefan@agner.ch>.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/bitops.h>
  18. #include <linux/err.h>
  19. #include <linux/gpio.h>
  20. #include <linux/init.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/io.h>
  23. #include <linux/ioport.h>
  24. #include <linux/irq.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/of.h>
  27. #include <linux/of_device.h>
  28. #include <linux/of_irq.h>
  29. #define VF610_GPIO_PER_PORT 32
  30. struct fsl_gpio_soc_data {
  31. /* SoCs has a Port Data Direction Register (PDDR) */
  32. bool have_paddr;
  33. };
  34. struct vf610_gpio_port {
  35. struct gpio_chip gc;
  36. struct irq_chip ic;
  37. void __iomem *base;
  38. void __iomem *gpio_base;
  39. const struct fsl_gpio_soc_data *sdata;
  40. u8 irqc[VF610_GPIO_PER_PORT];
  41. int irq;
  42. };
  43. #define GPIO_PDOR 0x00
  44. #define GPIO_PSOR 0x04
  45. #define GPIO_PCOR 0x08
  46. #define GPIO_PTOR 0x0c
  47. #define GPIO_PDIR 0x10
  48. #define GPIO_PDDR 0x14
  49. #define PORT_PCR(n) ((n) * 0x4)
  50. #define PORT_PCR_IRQC_OFFSET 16
  51. #define PORT_ISFR 0xa0
  52. #define PORT_DFER 0xc0
  53. #define PORT_DFCR 0xc4
  54. #define PORT_DFWR 0xc8
  55. #define PORT_INT_OFF 0x0
  56. #define PORT_INT_LOGIC_ZERO 0x8
  57. #define PORT_INT_RISING_EDGE 0x9
  58. #define PORT_INT_FALLING_EDGE 0xa
  59. #define PORT_INT_EITHER_EDGE 0xb
  60. #define PORT_INT_LOGIC_ONE 0xc
  61. static const struct fsl_gpio_soc_data imx_data = {
  62. .have_paddr = true,
  63. };
  64. static const struct of_device_id vf610_gpio_dt_ids[] = {
  65. { .compatible = "fsl,vf610-gpio", .data = NULL, },
  66. { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
  67. { /* sentinel */ }
  68. };
  69. static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
  70. {
  71. writel_relaxed(val, reg);
  72. }
  73. static inline u32 vf610_gpio_readl(void __iomem *reg)
  74. {
  75. return readl_relaxed(reg);
  76. }
  77. static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  78. {
  79. struct vf610_gpio_port *port = gpiochip_get_data(gc);
  80. unsigned long mask = BIT(gpio);
  81. void __iomem *addr;
  82. if (port->sdata && port->sdata->have_paddr) {
  83. mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
  84. addr = mask ? port->gpio_base + GPIO_PDOR :
  85. port->gpio_base + GPIO_PDIR;
  86. return !!(vf610_gpio_readl(addr) & BIT(gpio));
  87. } else {
  88. return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR)
  89. & BIT(gpio));
  90. }
  91. }
  92. static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  93. {
  94. struct vf610_gpio_port *port = gpiochip_get_data(gc);
  95. unsigned long mask = BIT(gpio);
  96. if (val)
  97. vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR);
  98. else
  99. vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR);
  100. }
  101. static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  102. {
  103. struct vf610_gpio_port *port = gpiochip_get_data(chip);
  104. unsigned long mask = BIT(gpio);
  105. u32 val;
  106. if (port->sdata && port->sdata->have_paddr) {
  107. val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
  108. val &= ~mask;
  109. vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
  110. }
  111. return pinctrl_gpio_direction_input(chip->base + gpio);
  112. }
  113. static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
  114. int value)
  115. {
  116. struct vf610_gpio_port *port = gpiochip_get_data(chip);
  117. unsigned long mask = BIT(gpio);
  118. if (port->sdata && port->sdata->have_paddr)
  119. vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
  120. vf610_gpio_set(chip, gpio, value);
  121. return pinctrl_gpio_direction_output(chip->base + gpio);
  122. }
  123. static void vf610_gpio_irq_handler(struct irq_desc *desc)
  124. {
  125. struct vf610_gpio_port *port =
  126. gpiochip_get_data(irq_desc_get_handler_data(desc));
  127. struct irq_chip *chip = irq_desc_get_chip(desc);
  128. int pin;
  129. unsigned long irq_isfr;
  130. chained_irq_enter(chip, desc);
  131. irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
  132. for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
  133. vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
  134. generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
  135. }
  136. chained_irq_exit(chip, desc);
  137. }
  138. static void vf610_gpio_irq_ack(struct irq_data *d)
  139. {
  140. struct vf610_gpio_port *port =
  141. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  142. int gpio = d->hwirq;
  143. vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
  144. }
  145. static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
  146. {
  147. struct vf610_gpio_port *port =
  148. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  149. u8 irqc;
  150. switch (type) {
  151. case IRQ_TYPE_EDGE_RISING:
  152. irqc = PORT_INT_RISING_EDGE;
  153. break;
  154. case IRQ_TYPE_EDGE_FALLING:
  155. irqc = PORT_INT_FALLING_EDGE;
  156. break;
  157. case IRQ_TYPE_EDGE_BOTH:
  158. irqc = PORT_INT_EITHER_EDGE;
  159. break;
  160. case IRQ_TYPE_LEVEL_LOW:
  161. irqc = PORT_INT_LOGIC_ZERO;
  162. break;
  163. case IRQ_TYPE_LEVEL_HIGH:
  164. irqc = PORT_INT_LOGIC_ONE;
  165. break;
  166. default:
  167. return -EINVAL;
  168. }
  169. port->irqc[d->hwirq] = irqc;
  170. if (type & IRQ_TYPE_LEVEL_MASK)
  171. irq_set_handler_locked(d, handle_level_irq);
  172. else
  173. irq_set_handler_locked(d, handle_edge_irq);
  174. return 0;
  175. }
  176. static void vf610_gpio_irq_mask(struct irq_data *d)
  177. {
  178. struct vf610_gpio_port *port =
  179. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  180. void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
  181. vf610_gpio_writel(0, pcr_base);
  182. }
  183. static void vf610_gpio_irq_unmask(struct irq_data *d)
  184. {
  185. struct vf610_gpio_port *port =
  186. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  187. void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
  188. vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
  189. pcr_base);
  190. }
  191. static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
  192. {
  193. struct vf610_gpio_port *port =
  194. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  195. if (enable)
  196. enable_irq_wake(port->irq);
  197. else
  198. disable_irq_wake(port->irq);
  199. return 0;
  200. }
  201. static int vf610_gpio_probe(struct platform_device *pdev)
  202. {
  203. struct device *dev = &pdev->dev;
  204. struct device_node *np = dev->of_node;
  205. struct vf610_gpio_port *port;
  206. struct resource *iores;
  207. struct gpio_chip *gc;
  208. struct irq_chip *ic;
  209. int i;
  210. int ret;
  211. port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
  212. if (!port)
  213. return -ENOMEM;
  214. port->sdata = of_device_get_match_data(dev);
  215. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  216. port->base = devm_ioremap_resource(dev, iores);
  217. if (IS_ERR(port->base))
  218. return PTR_ERR(port->base);
  219. iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  220. port->gpio_base = devm_ioremap_resource(dev, iores);
  221. if (IS_ERR(port->gpio_base))
  222. return PTR_ERR(port->gpio_base);
  223. port->irq = platform_get_irq(pdev, 0);
  224. if (port->irq < 0)
  225. return port->irq;
  226. gc = &port->gc;
  227. gc->of_node = np;
  228. gc->parent = dev;
  229. gc->label = "vf610-gpio";
  230. gc->ngpio = VF610_GPIO_PER_PORT;
  231. gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
  232. gc->request = gpiochip_generic_request;
  233. gc->free = gpiochip_generic_free;
  234. gc->direction_input = vf610_gpio_direction_input;
  235. gc->get = vf610_gpio_get;
  236. gc->direction_output = vf610_gpio_direction_output;
  237. gc->set = vf610_gpio_set;
  238. ic = &port->ic;
  239. ic->name = "gpio-vf610";
  240. ic->irq_ack = vf610_gpio_irq_ack;
  241. ic->irq_mask = vf610_gpio_irq_mask;
  242. ic->irq_unmask = vf610_gpio_irq_unmask;
  243. ic->irq_set_type = vf610_gpio_irq_set_type;
  244. ic->irq_set_wake = vf610_gpio_irq_set_wake;
  245. ret = gpiochip_add_data(gc, port);
  246. if (ret < 0)
  247. return ret;
  248. /* Mask all GPIO interrupts */
  249. for (i = 0; i < gc->ngpio; i++)
  250. vf610_gpio_writel(0, port->base + PORT_PCR(i));
  251. /* Clear the interrupt status register for all GPIO's */
  252. vf610_gpio_writel(~0, port->base + PORT_ISFR);
  253. ret = gpiochip_irqchip_add(gc, ic, 0, handle_edge_irq, IRQ_TYPE_NONE);
  254. if (ret) {
  255. dev_err(dev, "failed to add irqchip\n");
  256. gpiochip_remove(gc);
  257. return ret;
  258. }
  259. gpiochip_set_chained_irqchip(gc, ic, port->irq,
  260. vf610_gpio_irq_handler);
  261. return 0;
  262. }
  263. static struct platform_driver vf610_gpio_driver = {
  264. .driver = {
  265. .name = "gpio-vf610",
  266. .of_match_table = vf610_gpio_dt_ids,
  267. },
  268. .probe = vf610_gpio_probe,
  269. };
  270. builtin_platform_driver(vf610_gpio_driver);