core.c 28 KB

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  1. /*
  2. * Filename: core.c
  3. *
  4. *
  5. * Authors: Joshua Morris <josh.h.morris@us.ibm.com>
  6. * Philip Kelleher <pjk1939@linux.vnet.ibm.com>
  7. *
  8. * (C) Copyright 2013 IBM Corporation
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of the
  13. * License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software Foundation,
  22. * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/init.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include <linux/reboot.h>
  30. #include <linux/slab.h>
  31. #include <linux/bitops.h>
  32. #include <linux/delay.h>
  33. #include <linux/debugfs.h>
  34. #include <linux/seq_file.h>
  35. #include <linux/genhd.h>
  36. #include <linux/idr.h>
  37. #include "rsxx_priv.h"
  38. #include "rsxx_cfg.h"
  39. #define NO_LEGACY 0
  40. #define SYNC_START_TIMEOUT (10 * 60) /* 10 minutes */
  41. MODULE_DESCRIPTION("IBM Flash Adapter 900GB Full Height Device Driver");
  42. MODULE_AUTHOR("Joshua Morris/Philip Kelleher, IBM");
  43. MODULE_LICENSE("GPL");
  44. MODULE_VERSION(DRIVER_VERSION);
  45. static unsigned int force_legacy = NO_LEGACY;
  46. module_param(force_legacy, uint, 0444);
  47. MODULE_PARM_DESC(force_legacy, "Force the use of legacy type PCI interrupts");
  48. static unsigned int sync_start = 1;
  49. module_param(sync_start, uint, 0444);
  50. MODULE_PARM_DESC(sync_start, "On by Default: Driver load will not complete "
  51. "until the card startup has completed.");
  52. static DEFINE_IDA(rsxx_disk_ida);
  53. /* --------------------Debugfs Setup ------------------- */
  54. static int rsxx_attr_pci_regs_show(struct seq_file *m, void *p)
  55. {
  56. struct rsxx_cardinfo *card = m->private;
  57. seq_printf(m, "HWID 0x%08x\n",
  58. ioread32(card->regmap + HWID));
  59. seq_printf(m, "SCRATCH 0x%08x\n",
  60. ioread32(card->regmap + SCRATCH));
  61. seq_printf(m, "IER 0x%08x\n",
  62. ioread32(card->regmap + IER));
  63. seq_printf(m, "IPR 0x%08x\n",
  64. ioread32(card->regmap + IPR));
  65. seq_printf(m, "CREG_CMD 0x%08x\n",
  66. ioread32(card->regmap + CREG_CMD));
  67. seq_printf(m, "CREG_ADD 0x%08x\n",
  68. ioread32(card->regmap + CREG_ADD));
  69. seq_printf(m, "CREG_CNT 0x%08x\n",
  70. ioread32(card->regmap + CREG_CNT));
  71. seq_printf(m, "CREG_STAT 0x%08x\n",
  72. ioread32(card->regmap + CREG_STAT));
  73. seq_printf(m, "CREG_DATA0 0x%08x\n",
  74. ioread32(card->regmap + CREG_DATA0));
  75. seq_printf(m, "CREG_DATA1 0x%08x\n",
  76. ioread32(card->regmap + CREG_DATA1));
  77. seq_printf(m, "CREG_DATA2 0x%08x\n",
  78. ioread32(card->regmap + CREG_DATA2));
  79. seq_printf(m, "CREG_DATA3 0x%08x\n",
  80. ioread32(card->regmap + CREG_DATA3));
  81. seq_printf(m, "CREG_DATA4 0x%08x\n",
  82. ioread32(card->regmap + CREG_DATA4));
  83. seq_printf(m, "CREG_DATA5 0x%08x\n",
  84. ioread32(card->regmap + CREG_DATA5));
  85. seq_printf(m, "CREG_DATA6 0x%08x\n",
  86. ioread32(card->regmap + CREG_DATA6));
  87. seq_printf(m, "CREG_DATA7 0x%08x\n",
  88. ioread32(card->regmap + CREG_DATA7));
  89. seq_printf(m, "INTR_COAL 0x%08x\n",
  90. ioread32(card->regmap + INTR_COAL));
  91. seq_printf(m, "HW_ERROR 0x%08x\n",
  92. ioread32(card->regmap + HW_ERROR));
  93. seq_printf(m, "DEBUG0 0x%08x\n",
  94. ioread32(card->regmap + PCI_DEBUG0));
  95. seq_printf(m, "DEBUG1 0x%08x\n",
  96. ioread32(card->regmap + PCI_DEBUG1));
  97. seq_printf(m, "DEBUG2 0x%08x\n",
  98. ioread32(card->regmap + PCI_DEBUG2));
  99. seq_printf(m, "DEBUG3 0x%08x\n",
  100. ioread32(card->regmap + PCI_DEBUG3));
  101. seq_printf(m, "DEBUG4 0x%08x\n",
  102. ioread32(card->regmap + PCI_DEBUG4));
  103. seq_printf(m, "DEBUG5 0x%08x\n",
  104. ioread32(card->regmap + PCI_DEBUG5));
  105. seq_printf(m, "DEBUG6 0x%08x\n",
  106. ioread32(card->regmap + PCI_DEBUG6));
  107. seq_printf(m, "DEBUG7 0x%08x\n",
  108. ioread32(card->regmap + PCI_DEBUG7));
  109. seq_printf(m, "RECONFIG 0x%08x\n",
  110. ioread32(card->regmap + PCI_RECONFIG));
  111. return 0;
  112. }
  113. static int rsxx_attr_stats_show(struct seq_file *m, void *p)
  114. {
  115. struct rsxx_cardinfo *card = m->private;
  116. int i;
  117. for (i = 0; i < card->n_targets; i++) {
  118. seq_printf(m, "Ctrl %d CRC Errors = %d\n",
  119. i, card->ctrl[i].stats.crc_errors);
  120. seq_printf(m, "Ctrl %d Hard Errors = %d\n",
  121. i, card->ctrl[i].stats.hard_errors);
  122. seq_printf(m, "Ctrl %d Soft Errors = %d\n",
  123. i, card->ctrl[i].stats.soft_errors);
  124. seq_printf(m, "Ctrl %d Writes Issued = %d\n",
  125. i, card->ctrl[i].stats.writes_issued);
  126. seq_printf(m, "Ctrl %d Writes Failed = %d\n",
  127. i, card->ctrl[i].stats.writes_failed);
  128. seq_printf(m, "Ctrl %d Reads Issued = %d\n",
  129. i, card->ctrl[i].stats.reads_issued);
  130. seq_printf(m, "Ctrl %d Reads Failed = %d\n",
  131. i, card->ctrl[i].stats.reads_failed);
  132. seq_printf(m, "Ctrl %d Reads Retried = %d\n",
  133. i, card->ctrl[i].stats.reads_retried);
  134. seq_printf(m, "Ctrl %d Discards Issued = %d\n",
  135. i, card->ctrl[i].stats.discards_issued);
  136. seq_printf(m, "Ctrl %d Discards Failed = %d\n",
  137. i, card->ctrl[i].stats.discards_failed);
  138. seq_printf(m, "Ctrl %d DMA SW Errors = %d\n",
  139. i, card->ctrl[i].stats.dma_sw_err);
  140. seq_printf(m, "Ctrl %d DMA HW Faults = %d\n",
  141. i, card->ctrl[i].stats.dma_hw_fault);
  142. seq_printf(m, "Ctrl %d DMAs Cancelled = %d\n",
  143. i, card->ctrl[i].stats.dma_cancelled);
  144. seq_printf(m, "Ctrl %d SW Queue Depth = %d\n",
  145. i, card->ctrl[i].stats.sw_q_depth);
  146. seq_printf(m, "Ctrl %d HW Queue Depth = %d\n",
  147. i, atomic_read(&card->ctrl[i].stats.hw_q_depth));
  148. }
  149. return 0;
  150. }
  151. static int rsxx_attr_stats_open(struct inode *inode, struct file *file)
  152. {
  153. return single_open(file, rsxx_attr_stats_show, inode->i_private);
  154. }
  155. static int rsxx_attr_pci_regs_open(struct inode *inode, struct file *file)
  156. {
  157. return single_open(file, rsxx_attr_pci_regs_show, inode->i_private);
  158. }
  159. static ssize_t rsxx_cram_read(struct file *fp, char __user *ubuf,
  160. size_t cnt, loff_t *ppos)
  161. {
  162. struct rsxx_cardinfo *card = file_inode(fp)->i_private;
  163. char *buf;
  164. ssize_t st;
  165. buf = kzalloc(cnt, GFP_KERNEL);
  166. if (!buf)
  167. return -ENOMEM;
  168. st = rsxx_creg_read(card, CREG_ADD_CRAM + (u32)*ppos, cnt, buf, 1);
  169. if (!st)
  170. st = copy_to_user(ubuf, buf, cnt);
  171. kfree(buf);
  172. if (st)
  173. return st;
  174. *ppos += cnt;
  175. return cnt;
  176. }
  177. static ssize_t rsxx_cram_write(struct file *fp, const char __user *ubuf,
  178. size_t cnt, loff_t *ppos)
  179. {
  180. struct rsxx_cardinfo *card = file_inode(fp)->i_private;
  181. char *buf;
  182. ssize_t st;
  183. buf = memdup_user(ubuf, cnt);
  184. if (IS_ERR(buf))
  185. return PTR_ERR(buf);
  186. st = rsxx_creg_write(card, CREG_ADD_CRAM + (u32)*ppos, cnt, buf, 1);
  187. kfree(buf);
  188. if (st)
  189. return st;
  190. *ppos += cnt;
  191. return cnt;
  192. }
  193. static const struct file_operations debugfs_cram_fops = {
  194. .owner = THIS_MODULE,
  195. .read = rsxx_cram_read,
  196. .write = rsxx_cram_write,
  197. };
  198. static const struct file_operations debugfs_stats_fops = {
  199. .owner = THIS_MODULE,
  200. .open = rsxx_attr_stats_open,
  201. .read = seq_read,
  202. .llseek = seq_lseek,
  203. .release = single_release,
  204. };
  205. static const struct file_operations debugfs_pci_regs_fops = {
  206. .owner = THIS_MODULE,
  207. .open = rsxx_attr_pci_regs_open,
  208. .read = seq_read,
  209. .llseek = seq_lseek,
  210. .release = single_release,
  211. };
  212. static void rsxx_debugfs_dev_new(struct rsxx_cardinfo *card)
  213. {
  214. struct dentry *debugfs_stats;
  215. struct dentry *debugfs_pci_regs;
  216. struct dentry *debugfs_cram;
  217. card->debugfs_dir = debugfs_create_dir(card->gendisk->disk_name, NULL);
  218. if (IS_ERR_OR_NULL(card->debugfs_dir))
  219. goto failed_debugfs_dir;
  220. debugfs_stats = debugfs_create_file("stats", 0444,
  221. card->debugfs_dir, card,
  222. &debugfs_stats_fops);
  223. if (IS_ERR_OR_NULL(debugfs_stats))
  224. goto failed_debugfs_stats;
  225. debugfs_pci_regs = debugfs_create_file("pci_regs", 0444,
  226. card->debugfs_dir, card,
  227. &debugfs_pci_regs_fops);
  228. if (IS_ERR_OR_NULL(debugfs_pci_regs))
  229. goto failed_debugfs_pci_regs;
  230. debugfs_cram = debugfs_create_file("cram", 0644,
  231. card->debugfs_dir, card,
  232. &debugfs_cram_fops);
  233. if (IS_ERR_OR_NULL(debugfs_cram))
  234. goto failed_debugfs_cram;
  235. return;
  236. failed_debugfs_cram:
  237. debugfs_remove(debugfs_pci_regs);
  238. failed_debugfs_pci_regs:
  239. debugfs_remove(debugfs_stats);
  240. failed_debugfs_stats:
  241. debugfs_remove(card->debugfs_dir);
  242. failed_debugfs_dir:
  243. card->debugfs_dir = NULL;
  244. }
  245. /*----------------- Interrupt Control & Handling -------------------*/
  246. static void rsxx_mask_interrupts(struct rsxx_cardinfo *card)
  247. {
  248. card->isr_mask = 0;
  249. card->ier_mask = 0;
  250. }
  251. static void __enable_intr(unsigned int *mask, unsigned int intr)
  252. {
  253. *mask |= intr;
  254. }
  255. static void __disable_intr(unsigned int *mask, unsigned int intr)
  256. {
  257. *mask &= ~intr;
  258. }
  259. /*
  260. * NOTE: Disabling the IER will disable the hardware interrupt.
  261. * Disabling the ISR will disable the software handling of the ISR bit.
  262. *
  263. * Enable/Disable interrupt functions assume the card->irq_lock
  264. * is held by the caller.
  265. */
  266. void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr)
  267. {
  268. if (unlikely(card->halt) ||
  269. unlikely(card->eeh_state))
  270. return;
  271. __enable_intr(&card->ier_mask, intr);
  272. iowrite32(card->ier_mask, card->regmap + IER);
  273. }
  274. void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr)
  275. {
  276. if (unlikely(card->eeh_state))
  277. return;
  278. __disable_intr(&card->ier_mask, intr);
  279. iowrite32(card->ier_mask, card->regmap + IER);
  280. }
  281. void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
  282. unsigned int intr)
  283. {
  284. if (unlikely(card->halt) ||
  285. unlikely(card->eeh_state))
  286. return;
  287. __enable_intr(&card->isr_mask, intr);
  288. __enable_intr(&card->ier_mask, intr);
  289. iowrite32(card->ier_mask, card->regmap + IER);
  290. }
  291. void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
  292. unsigned int intr)
  293. {
  294. if (unlikely(card->eeh_state))
  295. return;
  296. __disable_intr(&card->isr_mask, intr);
  297. __disable_intr(&card->ier_mask, intr);
  298. iowrite32(card->ier_mask, card->regmap + IER);
  299. }
  300. static irqreturn_t rsxx_isr(int irq, void *pdata)
  301. {
  302. struct rsxx_cardinfo *card = pdata;
  303. unsigned int isr;
  304. int handled = 0;
  305. int reread_isr;
  306. int i;
  307. spin_lock(&card->irq_lock);
  308. do {
  309. reread_isr = 0;
  310. if (unlikely(card->eeh_state))
  311. break;
  312. isr = ioread32(card->regmap + ISR);
  313. if (isr == 0xffffffff) {
  314. /*
  315. * A few systems seem to have an intermittent issue
  316. * where PCI reads return all Fs, but retrying the read
  317. * a little later will return as expected.
  318. */
  319. dev_info(CARD_TO_DEV(card),
  320. "ISR = 0xFFFFFFFF, retrying later\n");
  321. break;
  322. }
  323. isr &= card->isr_mask;
  324. if (!isr)
  325. break;
  326. for (i = 0; i < card->n_targets; i++) {
  327. if (isr & CR_INTR_DMA(i)) {
  328. if (card->ier_mask & CR_INTR_DMA(i)) {
  329. rsxx_disable_ier(card, CR_INTR_DMA(i));
  330. reread_isr = 1;
  331. }
  332. queue_work(card->ctrl[i].done_wq,
  333. &card->ctrl[i].dma_done_work);
  334. handled++;
  335. }
  336. }
  337. if (isr & CR_INTR_CREG) {
  338. queue_work(card->creg_ctrl.creg_wq,
  339. &card->creg_ctrl.done_work);
  340. handled++;
  341. }
  342. if (isr & CR_INTR_EVENT) {
  343. queue_work(card->event_wq, &card->event_work);
  344. rsxx_disable_ier_and_isr(card, CR_INTR_EVENT);
  345. handled++;
  346. }
  347. } while (reread_isr);
  348. spin_unlock(&card->irq_lock);
  349. return handled ? IRQ_HANDLED : IRQ_NONE;
  350. }
  351. /*----------------- Card Event Handler -------------------*/
  352. static const char * const rsxx_card_state_to_str(unsigned int state)
  353. {
  354. static const char * const state_strings[] = {
  355. "Unknown", "Shutdown", "Starting", "Formatting",
  356. "Uninitialized", "Good", "Shutting Down",
  357. "Fault", "Read Only Fault", "dStroying"
  358. };
  359. return state_strings[ffs(state)];
  360. }
  361. static void card_state_change(struct rsxx_cardinfo *card,
  362. unsigned int new_state)
  363. {
  364. int st;
  365. dev_info(CARD_TO_DEV(card),
  366. "card state change detected.(%s -> %s)\n",
  367. rsxx_card_state_to_str(card->state),
  368. rsxx_card_state_to_str(new_state));
  369. card->state = new_state;
  370. /* Don't attach DMA interfaces if the card has an invalid config */
  371. if (!card->config_valid)
  372. return;
  373. switch (new_state) {
  374. case CARD_STATE_RD_ONLY_FAULT:
  375. dev_crit(CARD_TO_DEV(card),
  376. "Hardware has entered read-only mode!\n");
  377. /*
  378. * Fall through so the DMA devices can be attached and
  379. * the user can attempt to pull off their data.
  380. */
  381. case CARD_STATE_GOOD:
  382. st = rsxx_get_card_size8(card, &card->size8);
  383. if (st)
  384. dev_err(CARD_TO_DEV(card),
  385. "Failed attaching DMA devices\n");
  386. if (card->config_valid)
  387. set_capacity(card->gendisk, card->size8 >> 9);
  388. break;
  389. case CARD_STATE_FAULT:
  390. dev_crit(CARD_TO_DEV(card),
  391. "Hardware Fault reported!\n");
  392. /* Fall through. */
  393. /* Everything else, detach DMA interface if it's attached. */
  394. case CARD_STATE_SHUTDOWN:
  395. case CARD_STATE_STARTING:
  396. case CARD_STATE_FORMATTING:
  397. case CARD_STATE_UNINITIALIZED:
  398. case CARD_STATE_SHUTTING_DOWN:
  399. /*
  400. * dStroy is a term coined by marketing to represent the low level
  401. * secure erase.
  402. */
  403. case CARD_STATE_DSTROYING:
  404. set_capacity(card->gendisk, 0);
  405. break;
  406. }
  407. }
  408. static void card_event_handler(struct work_struct *work)
  409. {
  410. struct rsxx_cardinfo *card;
  411. unsigned int state;
  412. unsigned long flags;
  413. int st;
  414. card = container_of(work, struct rsxx_cardinfo, event_work);
  415. if (unlikely(card->halt))
  416. return;
  417. /*
  418. * Enable the interrupt now to avoid any weird race conditions where a
  419. * state change might occur while rsxx_get_card_state() is
  420. * processing a returned creg cmd.
  421. */
  422. spin_lock_irqsave(&card->irq_lock, flags);
  423. rsxx_enable_ier_and_isr(card, CR_INTR_EVENT);
  424. spin_unlock_irqrestore(&card->irq_lock, flags);
  425. st = rsxx_get_card_state(card, &state);
  426. if (st) {
  427. dev_info(CARD_TO_DEV(card),
  428. "Failed reading state after event.\n");
  429. return;
  430. }
  431. if (card->state != state)
  432. card_state_change(card, state);
  433. if (card->creg_ctrl.creg_stats.stat & CREG_STAT_LOG_PENDING)
  434. rsxx_read_hw_log(card);
  435. }
  436. /*----------------- Card Operations -------------------*/
  437. static int card_shutdown(struct rsxx_cardinfo *card)
  438. {
  439. unsigned int state;
  440. signed long start;
  441. const int timeout = msecs_to_jiffies(120000);
  442. int st;
  443. /* We can't issue a shutdown if the card is in a transition state */
  444. start = jiffies;
  445. do {
  446. st = rsxx_get_card_state(card, &state);
  447. if (st)
  448. return st;
  449. } while (state == CARD_STATE_STARTING &&
  450. (jiffies - start < timeout));
  451. if (state == CARD_STATE_STARTING)
  452. return -ETIMEDOUT;
  453. /* Only issue a shutdown if we need to */
  454. if ((state != CARD_STATE_SHUTTING_DOWN) &&
  455. (state != CARD_STATE_SHUTDOWN)) {
  456. st = rsxx_issue_card_cmd(card, CARD_CMD_SHUTDOWN);
  457. if (st)
  458. return st;
  459. }
  460. start = jiffies;
  461. do {
  462. st = rsxx_get_card_state(card, &state);
  463. if (st)
  464. return st;
  465. } while (state != CARD_STATE_SHUTDOWN &&
  466. (jiffies - start < timeout));
  467. if (state != CARD_STATE_SHUTDOWN)
  468. return -ETIMEDOUT;
  469. return 0;
  470. }
  471. static int rsxx_eeh_frozen(struct pci_dev *dev)
  472. {
  473. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  474. int i;
  475. int st;
  476. dev_warn(&dev->dev, "IBM Flash Adapter PCI: preparing for slot reset.\n");
  477. card->eeh_state = 1;
  478. rsxx_mask_interrupts(card);
  479. /*
  480. * We need to guarantee that the write for eeh_state and masking
  481. * interrupts does not become reordered. This will prevent a possible
  482. * race condition with the EEH code.
  483. */
  484. wmb();
  485. pci_disable_device(dev);
  486. st = rsxx_eeh_save_issued_dmas(card);
  487. if (st)
  488. return st;
  489. rsxx_eeh_save_issued_creg(card);
  490. for (i = 0; i < card->n_targets; i++) {
  491. if (card->ctrl[i].status.buf)
  492. pci_free_consistent(card->dev, STATUS_BUFFER_SIZE8,
  493. card->ctrl[i].status.buf,
  494. card->ctrl[i].status.dma_addr);
  495. if (card->ctrl[i].cmd.buf)
  496. pci_free_consistent(card->dev, COMMAND_BUFFER_SIZE8,
  497. card->ctrl[i].cmd.buf,
  498. card->ctrl[i].cmd.dma_addr);
  499. }
  500. return 0;
  501. }
  502. static void rsxx_eeh_failure(struct pci_dev *dev)
  503. {
  504. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  505. int i;
  506. int cnt = 0;
  507. dev_err(&dev->dev, "IBM Flash Adapter PCI: disabling failed card.\n");
  508. card->eeh_state = 1;
  509. card->halt = 1;
  510. for (i = 0; i < card->n_targets; i++) {
  511. spin_lock_bh(&card->ctrl[i].queue_lock);
  512. cnt = rsxx_cleanup_dma_queue(&card->ctrl[i],
  513. &card->ctrl[i].queue,
  514. COMPLETE_DMA);
  515. spin_unlock_bh(&card->ctrl[i].queue_lock);
  516. cnt += rsxx_dma_cancel(&card->ctrl[i]);
  517. if (cnt)
  518. dev_info(CARD_TO_DEV(card),
  519. "Freed %d queued DMAs on channel %d\n",
  520. cnt, card->ctrl[i].id);
  521. }
  522. }
  523. static int rsxx_eeh_fifo_flush_poll(struct rsxx_cardinfo *card)
  524. {
  525. unsigned int status;
  526. int iter = 0;
  527. /* We need to wait for the hardware to reset */
  528. while (iter++ < 10) {
  529. status = ioread32(card->regmap + PCI_RECONFIG);
  530. if (status & RSXX_FLUSH_BUSY) {
  531. ssleep(1);
  532. continue;
  533. }
  534. if (status & RSXX_FLUSH_TIMEOUT)
  535. dev_warn(CARD_TO_DEV(card), "HW: flash controller timeout\n");
  536. return 0;
  537. }
  538. /* Hardware failed resetting itself. */
  539. return -1;
  540. }
  541. static pci_ers_result_t rsxx_error_detected(struct pci_dev *dev,
  542. enum pci_channel_state error)
  543. {
  544. int st;
  545. if (dev->revision < RSXX_EEH_SUPPORT)
  546. return PCI_ERS_RESULT_NONE;
  547. if (error == pci_channel_io_perm_failure) {
  548. rsxx_eeh_failure(dev);
  549. return PCI_ERS_RESULT_DISCONNECT;
  550. }
  551. st = rsxx_eeh_frozen(dev);
  552. if (st) {
  553. dev_err(&dev->dev, "Slot reset setup failed\n");
  554. rsxx_eeh_failure(dev);
  555. return PCI_ERS_RESULT_DISCONNECT;
  556. }
  557. return PCI_ERS_RESULT_NEED_RESET;
  558. }
  559. static pci_ers_result_t rsxx_slot_reset(struct pci_dev *dev)
  560. {
  561. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  562. unsigned long flags;
  563. int i;
  564. int st;
  565. dev_warn(&dev->dev,
  566. "IBM Flash Adapter PCI: recovering from slot reset.\n");
  567. st = pci_enable_device(dev);
  568. if (st)
  569. goto failed_hw_setup;
  570. pci_set_master(dev);
  571. st = rsxx_eeh_fifo_flush_poll(card);
  572. if (st)
  573. goto failed_hw_setup;
  574. rsxx_dma_queue_reset(card);
  575. for (i = 0; i < card->n_targets; i++) {
  576. st = rsxx_hw_buffers_init(dev, &card->ctrl[i]);
  577. if (st)
  578. goto failed_hw_buffers_init;
  579. }
  580. if (card->config_valid)
  581. rsxx_dma_configure(card);
  582. /* Clears the ISR register from spurious interrupts */
  583. st = ioread32(card->regmap + ISR);
  584. card->eeh_state = 0;
  585. spin_lock_irqsave(&card->irq_lock, flags);
  586. if (card->n_targets & RSXX_MAX_TARGETS)
  587. rsxx_enable_ier_and_isr(card, CR_INTR_ALL_G);
  588. else
  589. rsxx_enable_ier_and_isr(card, CR_INTR_ALL_C);
  590. spin_unlock_irqrestore(&card->irq_lock, flags);
  591. rsxx_kick_creg_queue(card);
  592. for (i = 0; i < card->n_targets; i++) {
  593. spin_lock(&card->ctrl[i].queue_lock);
  594. if (list_empty(&card->ctrl[i].queue)) {
  595. spin_unlock(&card->ctrl[i].queue_lock);
  596. continue;
  597. }
  598. spin_unlock(&card->ctrl[i].queue_lock);
  599. queue_work(card->ctrl[i].issue_wq,
  600. &card->ctrl[i].issue_dma_work);
  601. }
  602. dev_info(&dev->dev, "IBM Flash Adapter PCI: recovery complete.\n");
  603. return PCI_ERS_RESULT_RECOVERED;
  604. failed_hw_buffers_init:
  605. for (i = 0; i < card->n_targets; i++) {
  606. if (card->ctrl[i].status.buf)
  607. pci_free_consistent(card->dev,
  608. STATUS_BUFFER_SIZE8,
  609. card->ctrl[i].status.buf,
  610. card->ctrl[i].status.dma_addr);
  611. if (card->ctrl[i].cmd.buf)
  612. pci_free_consistent(card->dev,
  613. COMMAND_BUFFER_SIZE8,
  614. card->ctrl[i].cmd.buf,
  615. card->ctrl[i].cmd.dma_addr);
  616. }
  617. failed_hw_setup:
  618. rsxx_eeh_failure(dev);
  619. return PCI_ERS_RESULT_DISCONNECT;
  620. }
  621. /*----------------- Driver Initialization & Setup -------------------*/
  622. /* Returns: 0 if the driver is compatible with the device
  623. -1 if the driver is NOT compatible with the device */
  624. static int rsxx_compatibility_check(struct rsxx_cardinfo *card)
  625. {
  626. unsigned char pci_rev;
  627. pci_read_config_byte(card->dev, PCI_REVISION_ID, &pci_rev);
  628. if (pci_rev > RS70_PCI_REV_SUPPORTED)
  629. return -1;
  630. return 0;
  631. }
  632. static int rsxx_pci_probe(struct pci_dev *dev,
  633. const struct pci_device_id *id)
  634. {
  635. struct rsxx_cardinfo *card;
  636. int st;
  637. unsigned int sync_timeout;
  638. dev_info(&dev->dev, "PCI-Flash SSD discovered\n");
  639. card = kzalloc(sizeof(*card), GFP_KERNEL);
  640. if (!card)
  641. return -ENOMEM;
  642. card->dev = dev;
  643. pci_set_drvdata(dev, card);
  644. st = ida_alloc(&rsxx_disk_ida, GFP_KERNEL);
  645. if (st < 0)
  646. goto failed_ida_get;
  647. card->disk_id = st;
  648. st = pci_enable_device(dev);
  649. if (st)
  650. goto failed_enable;
  651. pci_set_master(dev);
  652. pci_set_dma_max_seg_size(dev, RSXX_HW_BLK_SIZE);
  653. st = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
  654. if (st) {
  655. dev_err(CARD_TO_DEV(card),
  656. "No usable DMA configuration,aborting\n");
  657. goto failed_dma_mask;
  658. }
  659. st = pci_request_regions(dev, DRIVER_NAME);
  660. if (st) {
  661. dev_err(CARD_TO_DEV(card),
  662. "Failed to request memory region\n");
  663. goto failed_request_regions;
  664. }
  665. if (pci_resource_len(dev, 0) == 0) {
  666. dev_err(CARD_TO_DEV(card), "BAR0 has length 0!\n");
  667. st = -ENOMEM;
  668. goto failed_iomap;
  669. }
  670. card->regmap = pci_iomap(dev, 0, 0);
  671. if (!card->regmap) {
  672. dev_err(CARD_TO_DEV(card), "Failed to map BAR0\n");
  673. st = -ENOMEM;
  674. goto failed_iomap;
  675. }
  676. spin_lock_init(&card->irq_lock);
  677. card->halt = 0;
  678. card->eeh_state = 0;
  679. spin_lock_irq(&card->irq_lock);
  680. rsxx_disable_ier_and_isr(card, CR_INTR_ALL);
  681. spin_unlock_irq(&card->irq_lock);
  682. if (!force_legacy) {
  683. st = pci_enable_msi(dev);
  684. if (st)
  685. dev_warn(CARD_TO_DEV(card),
  686. "Failed to enable MSI\n");
  687. }
  688. st = request_irq(dev->irq, rsxx_isr, IRQF_SHARED,
  689. DRIVER_NAME, card);
  690. if (st) {
  691. dev_err(CARD_TO_DEV(card),
  692. "Failed requesting IRQ%d\n", dev->irq);
  693. goto failed_irq;
  694. }
  695. /************* Setup Processor Command Interface *************/
  696. st = rsxx_creg_setup(card);
  697. if (st) {
  698. dev_err(CARD_TO_DEV(card), "Failed to setup creg interface.\n");
  699. goto failed_creg_setup;
  700. }
  701. spin_lock_irq(&card->irq_lock);
  702. rsxx_enable_ier_and_isr(card, CR_INTR_CREG);
  703. spin_unlock_irq(&card->irq_lock);
  704. st = rsxx_compatibility_check(card);
  705. if (st) {
  706. dev_warn(CARD_TO_DEV(card),
  707. "Incompatible driver detected. Please update the driver.\n");
  708. st = -EINVAL;
  709. goto failed_compatiblity_check;
  710. }
  711. /************* Load Card Config *************/
  712. st = rsxx_load_config(card);
  713. if (st)
  714. dev_err(CARD_TO_DEV(card),
  715. "Failed loading card config\n");
  716. /************* Setup DMA Engine *************/
  717. st = rsxx_get_num_targets(card, &card->n_targets);
  718. if (st)
  719. dev_info(CARD_TO_DEV(card),
  720. "Failed reading the number of DMA targets\n");
  721. card->ctrl = kcalloc(card->n_targets, sizeof(*card->ctrl),
  722. GFP_KERNEL);
  723. if (!card->ctrl) {
  724. st = -ENOMEM;
  725. goto failed_dma_setup;
  726. }
  727. st = rsxx_dma_setup(card);
  728. if (st) {
  729. dev_info(CARD_TO_DEV(card),
  730. "Failed to setup DMA engine\n");
  731. goto failed_dma_setup;
  732. }
  733. /************* Setup Card Event Handler *************/
  734. card->event_wq = create_singlethread_workqueue(DRIVER_NAME"_event");
  735. if (!card->event_wq) {
  736. dev_err(CARD_TO_DEV(card), "Failed card event setup.\n");
  737. goto failed_event_handler;
  738. }
  739. INIT_WORK(&card->event_work, card_event_handler);
  740. st = rsxx_setup_dev(card);
  741. if (st)
  742. goto failed_create_dev;
  743. rsxx_get_card_state(card, &card->state);
  744. dev_info(CARD_TO_DEV(card),
  745. "card state: %s\n",
  746. rsxx_card_state_to_str(card->state));
  747. /*
  748. * Now that the DMA Engine and devices have been setup,
  749. * we can enable the event interrupt(it kicks off actions in
  750. * those layers so we couldn't enable it right away.)
  751. */
  752. spin_lock_irq(&card->irq_lock);
  753. rsxx_enable_ier_and_isr(card, CR_INTR_EVENT);
  754. spin_unlock_irq(&card->irq_lock);
  755. if (card->state == CARD_STATE_SHUTDOWN) {
  756. st = rsxx_issue_card_cmd(card, CARD_CMD_STARTUP);
  757. if (st)
  758. dev_crit(CARD_TO_DEV(card),
  759. "Failed issuing card startup\n");
  760. if (sync_start) {
  761. sync_timeout = SYNC_START_TIMEOUT;
  762. dev_info(CARD_TO_DEV(card),
  763. "Waiting for card to startup\n");
  764. do {
  765. ssleep(1);
  766. sync_timeout--;
  767. rsxx_get_card_state(card, &card->state);
  768. } while (sync_timeout &&
  769. (card->state == CARD_STATE_STARTING));
  770. if (card->state == CARD_STATE_STARTING) {
  771. dev_warn(CARD_TO_DEV(card),
  772. "Card startup timed out\n");
  773. card->size8 = 0;
  774. } else {
  775. dev_info(CARD_TO_DEV(card),
  776. "card state: %s\n",
  777. rsxx_card_state_to_str(card->state));
  778. st = rsxx_get_card_size8(card, &card->size8);
  779. if (st)
  780. card->size8 = 0;
  781. }
  782. }
  783. } else if (card->state == CARD_STATE_GOOD ||
  784. card->state == CARD_STATE_RD_ONLY_FAULT) {
  785. st = rsxx_get_card_size8(card, &card->size8);
  786. if (st)
  787. card->size8 = 0;
  788. }
  789. rsxx_attach_dev(card);
  790. /************* Setup Debugfs *************/
  791. rsxx_debugfs_dev_new(card);
  792. return 0;
  793. failed_create_dev:
  794. destroy_workqueue(card->event_wq);
  795. card->event_wq = NULL;
  796. failed_event_handler:
  797. rsxx_dma_destroy(card);
  798. failed_dma_setup:
  799. failed_compatiblity_check:
  800. destroy_workqueue(card->creg_ctrl.creg_wq);
  801. card->creg_ctrl.creg_wq = NULL;
  802. failed_creg_setup:
  803. spin_lock_irq(&card->irq_lock);
  804. rsxx_disable_ier_and_isr(card, CR_INTR_ALL);
  805. spin_unlock_irq(&card->irq_lock);
  806. free_irq(dev->irq, card);
  807. if (!force_legacy)
  808. pci_disable_msi(dev);
  809. failed_irq:
  810. pci_iounmap(dev, card->regmap);
  811. failed_iomap:
  812. pci_release_regions(dev);
  813. failed_request_regions:
  814. failed_dma_mask:
  815. pci_disable_device(dev);
  816. failed_enable:
  817. ida_free(&rsxx_disk_ida, card->disk_id);
  818. failed_ida_get:
  819. kfree(card);
  820. return st;
  821. }
  822. static void rsxx_pci_remove(struct pci_dev *dev)
  823. {
  824. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  825. unsigned long flags;
  826. int st;
  827. int i;
  828. if (!card)
  829. return;
  830. dev_info(CARD_TO_DEV(card),
  831. "Removing PCI-Flash SSD.\n");
  832. rsxx_detach_dev(card);
  833. for (i = 0; i < card->n_targets; i++) {
  834. spin_lock_irqsave(&card->irq_lock, flags);
  835. rsxx_disable_ier_and_isr(card, CR_INTR_DMA(i));
  836. spin_unlock_irqrestore(&card->irq_lock, flags);
  837. }
  838. st = card_shutdown(card);
  839. if (st)
  840. dev_crit(CARD_TO_DEV(card), "Shutdown failed!\n");
  841. /* Sync outstanding event handlers. */
  842. spin_lock_irqsave(&card->irq_lock, flags);
  843. rsxx_disable_ier_and_isr(card, CR_INTR_EVENT);
  844. spin_unlock_irqrestore(&card->irq_lock, flags);
  845. cancel_work_sync(&card->event_work);
  846. destroy_workqueue(card->event_wq);
  847. rsxx_destroy_dev(card);
  848. rsxx_dma_destroy(card);
  849. destroy_workqueue(card->creg_ctrl.creg_wq);
  850. spin_lock_irqsave(&card->irq_lock, flags);
  851. rsxx_disable_ier_and_isr(card, CR_INTR_ALL);
  852. spin_unlock_irqrestore(&card->irq_lock, flags);
  853. /* Prevent work_structs from re-queuing themselves. */
  854. card->halt = 1;
  855. debugfs_remove_recursive(card->debugfs_dir);
  856. free_irq(dev->irq, card);
  857. if (!force_legacy)
  858. pci_disable_msi(dev);
  859. rsxx_creg_destroy(card);
  860. pci_iounmap(dev, card->regmap);
  861. pci_disable_device(dev);
  862. pci_release_regions(dev);
  863. ida_free(&rsxx_disk_ida, card->disk_id);
  864. kfree(card);
  865. }
  866. static int rsxx_pci_suspend(struct pci_dev *dev, pm_message_t state)
  867. {
  868. /* We don't support suspend at this time. */
  869. return -ENOSYS;
  870. }
  871. static void rsxx_pci_shutdown(struct pci_dev *dev)
  872. {
  873. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  874. unsigned long flags;
  875. int i;
  876. if (!card)
  877. return;
  878. dev_info(CARD_TO_DEV(card), "Shutting down PCI-Flash SSD.\n");
  879. rsxx_detach_dev(card);
  880. for (i = 0; i < card->n_targets; i++) {
  881. spin_lock_irqsave(&card->irq_lock, flags);
  882. rsxx_disable_ier_and_isr(card, CR_INTR_DMA(i));
  883. spin_unlock_irqrestore(&card->irq_lock, flags);
  884. }
  885. card_shutdown(card);
  886. }
  887. static const struct pci_error_handlers rsxx_err_handler = {
  888. .error_detected = rsxx_error_detected,
  889. .slot_reset = rsxx_slot_reset,
  890. };
  891. static const struct pci_device_id rsxx_pci_ids[] = {
  892. {PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_FS70_FLASH)},
  893. {PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_FS80_FLASH)},
  894. {0,},
  895. };
  896. MODULE_DEVICE_TABLE(pci, rsxx_pci_ids);
  897. static struct pci_driver rsxx_pci_driver = {
  898. .name = DRIVER_NAME,
  899. .id_table = rsxx_pci_ids,
  900. .probe = rsxx_pci_probe,
  901. .remove = rsxx_pci_remove,
  902. .suspend = rsxx_pci_suspend,
  903. .shutdown = rsxx_pci_shutdown,
  904. .err_handler = &rsxx_err_handler,
  905. };
  906. static int __init rsxx_core_init(void)
  907. {
  908. int st;
  909. st = rsxx_dev_init();
  910. if (st)
  911. return st;
  912. st = rsxx_dma_init();
  913. if (st)
  914. goto dma_init_failed;
  915. st = rsxx_creg_init();
  916. if (st)
  917. goto creg_init_failed;
  918. return pci_register_driver(&rsxx_pci_driver);
  919. creg_init_failed:
  920. rsxx_dma_cleanup();
  921. dma_init_failed:
  922. rsxx_dev_cleanup();
  923. return st;
  924. }
  925. static void __exit rsxx_core_cleanup(void)
  926. {
  927. pci_unregister_driver(&rsxx_pci_driver);
  928. rsxx_creg_cleanup();
  929. rsxx_dma_cleanup();
  930. rsxx_dev_cleanup();
  931. }
  932. module_init(rsxx_core_init);
  933. module_exit(rsxx_core_cleanup);