ahci_mvebu.c 6.5 KB

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  1. /*
  2. * AHCI glue platform driver for Marvell EBU SOCs
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  7. * Marcin Wojtas <mw@semihalf.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/ahci_platform.h>
  14. #include <linux/kernel.h>
  15. #include <linux/mbus.h>
  16. #include <linux/module.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include "ahci.h"
  20. #define DRV_NAME "ahci-mvebu"
  21. #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
  22. #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
  23. #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
  24. #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
  25. #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
  26. struct ahci_mvebu_plat_data {
  27. int (*plat_config)(struct ahci_host_priv *hpriv);
  28. };
  29. static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv,
  30. const struct mbus_dram_target_info *dram)
  31. {
  32. int i;
  33. for (i = 0; i < 4; i++) {
  34. writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
  35. writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
  36. writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
  37. }
  38. for (i = 0; i < dram->num_cs; i++) {
  39. const struct mbus_dram_window *cs = dram->cs + i;
  40. writel((cs->mbus_attr << 8) |
  41. (dram->mbus_dram_target_id << 4) | 1,
  42. hpriv->mmio + AHCI_WINDOW_CTRL(i));
  43. writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i));
  44. writel(((cs->size - 1) & 0xffff0000),
  45. hpriv->mmio + AHCI_WINDOW_SIZE(i));
  46. }
  47. }
  48. static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
  49. {
  50. /*
  51. * Enable the regret bit to allow the SATA unit to regret a
  52. * request that didn't receive an acknowlegde and avoid a
  53. * deadlock
  54. */
  55. writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
  56. writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
  57. }
  58. static int ahci_mvebu_armada_380_config(struct ahci_host_priv *hpriv)
  59. {
  60. const struct mbus_dram_target_info *dram;
  61. int rc = 0;
  62. dram = mv_mbus_dram_info();
  63. if (dram)
  64. ahci_mvebu_mbus_config(hpriv, dram);
  65. else
  66. rc = -ENODEV;
  67. ahci_mvebu_regret_option(hpriv);
  68. return rc;
  69. }
  70. /**
  71. * ahci_mvebu_stop_engine
  72. *
  73. * @ap: Target ata port
  74. *
  75. * Errata Ref#226 - SATA Disk HOT swap issue when connected through
  76. * Port Multiplier in FIS-based Switching mode.
  77. *
  78. * To avoid the issue, according to design, the bits[11:8, 0] of
  79. * register PxFBS are cleared when Port Command and Status (0x18) bit[0]
  80. * changes its value from 1 to 0, i.e. falling edge of Port
  81. * Command and Status bit[0] sends PULSE that resets PxFBS
  82. * bits[11:8; 0].
  83. *
  84. * This function is used to override function of "ahci_stop_engine"
  85. * from libahci.c by adding the mvebu work around(WA) to save PxFBS
  86. * value before the PxCMD ST write of 0, then restore PxFBS value.
  87. *
  88. * Return: 0 on success; Error code otherwise.
  89. */
  90. static int ahci_mvebu_stop_engine(struct ata_port *ap)
  91. {
  92. void __iomem *port_mmio = ahci_port_base(ap);
  93. u32 tmp, port_fbs;
  94. tmp = readl(port_mmio + PORT_CMD);
  95. /* check if the HBA is idle */
  96. if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
  97. return 0;
  98. /* save the port PxFBS register for later restore */
  99. port_fbs = readl(port_mmio + PORT_FBS);
  100. /* setting HBA to idle */
  101. tmp &= ~PORT_CMD_START;
  102. writel(tmp, port_mmio + PORT_CMD);
  103. /*
  104. * bit #15 PxCMD signal doesn't clear PxFBS,
  105. * restore the PxFBS register right after clearing the PxCMD ST,
  106. * no need to wait for the PxCMD bit #15.
  107. */
  108. writel(port_fbs, port_mmio + PORT_FBS);
  109. /* wait for engine to stop. This could be as long as 500 msec */
  110. tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
  111. PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
  112. if (tmp & PORT_CMD_LIST_ON)
  113. return -EIO;
  114. return 0;
  115. }
  116. #ifdef CONFIG_PM_SLEEP
  117. static int ahci_mvebu_suspend(struct platform_device *pdev, pm_message_t state)
  118. {
  119. return ahci_platform_suspend_host(&pdev->dev);
  120. }
  121. static int ahci_mvebu_resume(struct platform_device *pdev)
  122. {
  123. struct ata_host *host = platform_get_drvdata(pdev);
  124. struct ahci_host_priv *hpriv = host->private_data;
  125. const struct ahci_mvebu_plat_data *pdata = hpriv->plat_data;
  126. if (pdata->plat_config)
  127. pdata->plat_config(hpriv);
  128. return ahci_platform_resume_host(&pdev->dev);
  129. }
  130. #else
  131. #define ahci_mvebu_suspend NULL
  132. #define ahci_mvebu_resume NULL
  133. #endif
  134. static const struct ata_port_info ahci_mvebu_port_info = {
  135. .flags = AHCI_FLAG_COMMON,
  136. .pio_mask = ATA_PIO4,
  137. .udma_mask = ATA_UDMA6,
  138. .port_ops = &ahci_platform_ops,
  139. };
  140. static struct scsi_host_template ahci_platform_sht = {
  141. AHCI_SHT(DRV_NAME),
  142. };
  143. static int ahci_mvebu_probe(struct platform_device *pdev)
  144. {
  145. const struct ahci_mvebu_plat_data *pdata;
  146. struct ahci_host_priv *hpriv;
  147. int rc;
  148. pdata = of_device_get_match_data(&pdev->dev);
  149. if (!pdata)
  150. return -EINVAL;
  151. hpriv = ahci_platform_get_resources(pdev, 0);
  152. if (IS_ERR(hpriv))
  153. return PTR_ERR(hpriv);
  154. hpriv->plat_data = (void *)pdata;
  155. rc = ahci_platform_enable_resources(hpriv);
  156. if (rc)
  157. return rc;
  158. hpriv->stop_engine = ahci_mvebu_stop_engine;
  159. pdata = hpriv->plat_data;
  160. if (pdata->plat_config) {
  161. rc = pdata->plat_config(hpriv);
  162. if (rc)
  163. goto disable_resources;
  164. }
  165. rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info,
  166. &ahci_platform_sht);
  167. if (rc)
  168. goto disable_resources;
  169. return 0;
  170. disable_resources:
  171. ahci_platform_disable_resources(hpriv);
  172. return rc;
  173. }
  174. static const struct ahci_mvebu_plat_data ahci_mvebu_armada_380_plat_data = {
  175. .plat_config = ahci_mvebu_armada_380_config,
  176. };
  177. static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = {
  178. .plat_config = NULL,
  179. };
  180. static const struct of_device_id ahci_mvebu_of_match[] = {
  181. {
  182. .compatible = "marvell,armada-380-ahci",
  183. .data = &ahci_mvebu_armada_380_plat_data,
  184. },
  185. {
  186. .compatible = "marvell,armada-3700-ahci",
  187. .data = &ahci_mvebu_armada_3700_plat_data,
  188. },
  189. { },
  190. };
  191. MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
  192. /*
  193. * We currently don't provide power management related operations,
  194. * since there is no suspend/resume support at the platform level for
  195. * Armada 38x for the moment.
  196. */
  197. static struct platform_driver ahci_mvebu_driver = {
  198. .probe = ahci_mvebu_probe,
  199. .remove = ata_platform_remove_one,
  200. .suspend = ahci_mvebu_suspend,
  201. .resume = ahci_mvebu_resume,
  202. .driver = {
  203. .name = DRV_NAME,
  204. .of_match_table = ahci_mvebu_of_match,
  205. },
  206. };
  207. module_platform_driver(ahci_mvebu_driver);
  208. MODULE_DESCRIPTION("Marvell EBU AHCI SATA driver");
  209. MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Marcin Wojtas <mw@semihalf.com>");
  210. MODULE_LICENSE("GPL");
  211. MODULE_ALIAS("platform:ahci_mvebu");