falconfalls.dts 8.9 KB

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  1. /*
  2. * CE4100 on Falcon Falls
  3. *
  4. * (c) Copyright 2010 Intel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; version 2 of the License.
  9. */
  10. /dts-v1/;
  11. / {
  12. model = "intel,falconfalls";
  13. compatible = "intel,falconfalls";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. cpu@0 {
  20. device_type = "cpu";
  21. compatible = "intel,ce4100";
  22. reg = <0>;
  23. lapic = <&lapic0>;
  24. };
  25. };
  26. soc@0 {
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. compatible = "intel,ce4100-cp";
  30. ranges;
  31. ioapic1: interrupt-controller@fec00000 {
  32. #interrupt-cells = <2>;
  33. compatible = "intel,ce4100-ioapic";
  34. interrupt-controller;
  35. reg = <0xfec00000 0x1000>;
  36. };
  37. timer@fed00000 {
  38. compatible = "intel,ce4100-hpet";
  39. reg = <0xfed00000 0x200>;
  40. };
  41. lapic0: interrupt-controller@fee00000 {
  42. compatible = "intel,ce4100-lapic";
  43. reg = <0xfee00000 0x1000>;
  44. };
  45. pci@3fc {
  46. #address-cells = <3>;
  47. #size-cells = <2>;
  48. compatible = "intel,ce4100-pci", "pci";
  49. device_type = "pci";
  50. bus-range = <0 0>;
  51. ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
  52. 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
  53. 0x0000000 0 0x0 0x0 0 0x100>;
  54. /* Secondary IO-APIC */
  55. ioapic2: interrupt-controller@0,1 {
  56. #interrupt-cells = <2>;
  57. compatible = "intel,ce4100-ioapic";
  58. interrupt-controller;
  59. reg = <0x100 0x0 0x0 0x0 0x0>;
  60. assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
  61. };
  62. pci@1,0 {
  63. #address-cells = <3>;
  64. #size-cells = <2>;
  65. compatible = "intel,ce4100-pci", "pci";
  66. device_type = "pci";
  67. bus-range = <1 1>;
  68. reg = <0x0800 0x0 0x0 0x0 0x0>;
  69. ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
  70. interrupt-parent = <&ioapic2>;
  71. display@2,0 {
  72. compatible = "pci8086,2e5b.2",
  73. "pci8086,2e5b",
  74. "pciclass038000",
  75. "pciclass0380";
  76. reg = <0x11000 0x0 0x0 0x0 0x0>;
  77. interrupts = <0 1>;
  78. };
  79. multimedia@3,0 {
  80. compatible = "pci8086,2e5c.2",
  81. "pci8086,2e5c",
  82. "pciclass048000",
  83. "pciclass0480";
  84. reg = <0x11800 0x0 0x0 0x0 0x0>;
  85. interrupts = <2 1>;
  86. };
  87. multimedia@4,0 {
  88. compatible = "pci8086,2e5d.2",
  89. "pci8086,2e5d",
  90. "pciclass048000",
  91. "pciclass0480";
  92. reg = <0x12000 0x0 0x0 0x0 0x0>;
  93. interrupts = <4 1>;
  94. };
  95. multimedia@4,1 {
  96. compatible = "pci8086,2e5e.2",
  97. "pci8086,2e5e",
  98. "pciclass048000",
  99. "pciclass0480";
  100. reg = <0x12100 0x0 0x0 0x0 0x0>;
  101. interrupts = <5 1>;
  102. };
  103. sound@6,0 {
  104. compatible = "pci8086,2e5f.2",
  105. "pci8086,2e5f",
  106. "pciclass040100",
  107. "pciclass0401";
  108. reg = <0x13000 0x0 0x0 0x0 0x0>;
  109. interrupts = <6 1>;
  110. };
  111. sound@6,1 {
  112. compatible = "pci8086,2e5f.2",
  113. "pci8086,2e5f",
  114. "pciclass040100",
  115. "pciclass0401";
  116. reg = <0x13100 0x0 0x0 0x0 0x0>;
  117. interrupts = <7 1>;
  118. };
  119. sound@6,2 {
  120. compatible = "pci8086,2e60.2",
  121. "pci8086,2e60",
  122. "pciclass040100",
  123. "pciclass0401";
  124. reg = <0x13200 0x0 0x0 0x0 0x0>;
  125. interrupts = <8 1>;
  126. };
  127. display@8,0 {
  128. compatible = "pci8086,2e61.2",
  129. "pci8086,2e61",
  130. "pciclass038000",
  131. "pciclass0380";
  132. reg = <0x14000 0x0 0x0 0x0 0x0>;
  133. interrupts = <9 1>;
  134. };
  135. display@8,1 {
  136. compatible = "pci8086,2e62.2",
  137. "pci8086,2e62",
  138. "pciclass038000",
  139. "pciclass0380";
  140. reg = <0x14100 0x0 0x0 0x0 0x0>;
  141. interrupts = <10 1>;
  142. };
  143. multimedia@8,2 {
  144. compatible = "pci8086,2e63.2",
  145. "pci8086,2e63",
  146. "pciclass048000",
  147. "pciclass0480";
  148. reg = <0x14200 0x0 0x0 0x0 0x0>;
  149. interrupts = <11 1>;
  150. };
  151. entertainment-encryption@9,0 {
  152. compatible = "pci8086,2e64.2",
  153. "pci8086,2e64",
  154. "pciclass101000",
  155. "pciclass1010";
  156. reg = <0x14800 0x0 0x0 0x0 0x0>;
  157. interrupts = <12 1>;
  158. };
  159. localbus@a,0 {
  160. compatible = "pci8086,2e65.2",
  161. "pci8086,2e65",
  162. "pciclassff0000",
  163. "pciclassff00";
  164. reg = <0x15000 0x0 0x0 0x0 0x0>;
  165. };
  166. serial@b,0 {
  167. compatible = "pci8086,2e66.2",
  168. "pci8086,2e66",
  169. "pciclass070003",
  170. "pciclass0700";
  171. reg = <0x15800 0x0 0x0 0x0 0x0>;
  172. interrupts = <14 1>;
  173. };
  174. pcigpio: gpio@b,1 {
  175. #gpio-cells = <2>;
  176. #interrupt-cells = <2>;
  177. compatible = "pci8086,2e67.2",
  178. "pci8086,2e67",
  179. "pciclassff0000",
  180. "pciclassff00";
  181. reg = <0x15900 0x0 0x0 0x0 0x0>;
  182. interrupts = <15 1>;
  183. interrupt-controller;
  184. gpio-controller;
  185. intel,muxctl = <0>;
  186. };
  187. i2c-controller@b,2 {
  188. #address-cells = <2>;
  189. #size-cells = <1>;
  190. compatible = "pci8086,2e68.2",
  191. "pci8086,2e68",
  192. "pciclass,ff0000",
  193. "pciclass,ff00";
  194. reg = <0x15a00 0x0 0x0 0x0 0x0>;
  195. interrupts = <16 1>;
  196. ranges = <0 0 0x02000000 0 0xdffe0500 0x100
  197. 1 0 0x02000000 0 0xdffe0600 0x100
  198. 2 0 0x02000000 0 0xdffe0700 0x100>;
  199. i2c@0 {
  200. #address-cells = <1>;
  201. #size-cells = <0>;
  202. compatible = "intel,ce4100-i2c-controller";
  203. reg = <0 0 0x100>;
  204. };
  205. i2c@1 {
  206. #address-cells = <1>;
  207. #size-cells = <0>;
  208. compatible = "intel,ce4100-i2c-controller";
  209. reg = <1 0 0x100>;
  210. gpio@26 {
  211. #gpio-cells = <2>;
  212. compatible = "ti,pcf8575";
  213. reg = <0x26>;
  214. gpio-controller;
  215. };
  216. };
  217. i2c@2 {
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. compatible = "intel,ce4100-i2c-controller";
  221. reg = <2 0 0x100>;
  222. gpio@26 {
  223. #gpio-cells = <2>;
  224. compatible = "ti,pcf8575";
  225. reg = <0x26>;
  226. gpio-controller;
  227. };
  228. };
  229. };
  230. smard-card@b,3 {
  231. compatible = "pci8086,2e69.2",
  232. "pci8086,2e69",
  233. "pciclass070500",
  234. "pciclass0705";
  235. reg = <0x15b00 0x0 0x0 0x0 0x0>;
  236. interrupts = <15 1>;
  237. };
  238. spi-controller@b,4 {
  239. #address-cells = <1>;
  240. #size-cells = <0>;
  241. compatible =
  242. "pci8086,2e6a.2",
  243. "pci8086,2e6a",
  244. "pciclass,ff0000",
  245. "pciclass,ff00";
  246. reg = <0x15c00 0x0 0x0 0x0 0x0>;
  247. interrupts = <15 1>;
  248. dac@0 {
  249. compatible = "ti,pcm1755";
  250. reg = <0>;
  251. spi-max-frequency = <115200>;
  252. };
  253. dac@1 {
  254. compatible = "ti,pcm1609a";
  255. reg = <1>;
  256. spi-max-frequency = <115200>;
  257. };
  258. eeprom@2 {
  259. compatible = "atmel,at93c46";
  260. reg = <2>;
  261. spi-max-frequency = <115200>;
  262. };
  263. };
  264. multimedia@b,7 {
  265. compatible = "pci8086,2e6d.2",
  266. "pci8086,2e6d",
  267. "pciclassff0000",
  268. "pciclassff00";
  269. reg = <0x15f00 0x0 0x0 0x0 0x0>;
  270. };
  271. ethernet@c,0 {
  272. compatible = "pci8086,2e6e.2",
  273. "pci8086,2e6e",
  274. "pciclass020000",
  275. "pciclass0200";
  276. reg = <0x16000 0x0 0x0 0x0 0x0>;
  277. interrupts = <21 1>;
  278. };
  279. clock@c,1 {
  280. compatible = "pci8086,2e6f.2",
  281. "pci8086,2e6f",
  282. "pciclassff0000",
  283. "pciclassff00";
  284. reg = <0x16100 0x0 0x0 0x0 0x0>;
  285. interrupts = <3 1>;
  286. };
  287. usb@d,0 {
  288. compatible = "pci8086,2e70.2",
  289. "pci8086,2e70",
  290. "pciclass0c0320",
  291. "pciclass0c03";
  292. reg = <0x16800 0x0 0x0 0x0 0x0>;
  293. interrupts = <22 1>;
  294. };
  295. usb@d,1 {
  296. compatible = "pci8086,2e70.2",
  297. "pci8086,2e70",
  298. "pciclass0c0320",
  299. "pciclass0c03";
  300. reg = <0x16900 0x0 0x0 0x0 0x0>;
  301. interrupts = <22 1>;
  302. };
  303. sata@e,0 {
  304. compatible = "pci8086,2e71.0",
  305. "pci8086,2e71",
  306. "pciclass010601",
  307. "pciclass0106";
  308. reg = <0x17000 0x0 0x0 0x0 0x0>;
  309. interrupts = <23 1>;
  310. };
  311. flash@f,0 {
  312. compatible = "pci8086,701.1",
  313. "pci8086,701",
  314. "pciclass050100",
  315. "pciclass0501";
  316. reg = <0x17800 0x0 0x0 0x0 0x0>;
  317. interrupts = <13 1>;
  318. };
  319. entertainment-encryption@10,0 {
  320. compatible = "pci8086,702.1",
  321. "pci8086,702",
  322. "pciclass101000",
  323. "pciclass1010";
  324. reg = <0x18000 0x0 0x0 0x0 0x0>;
  325. };
  326. co-processor@11,0 {
  327. compatible = "pci8086,703.1",
  328. "pci8086,703",
  329. "pciclass0b4000",
  330. "pciclass0b40";
  331. reg = <0x18800 0x0 0x0 0x0 0x0>;
  332. interrupts = <1 1>;
  333. };
  334. multimedia@12,0 {
  335. compatible = "pci8086,704.0",
  336. "pci8086,704",
  337. "pciclass048000",
  338. "pciclass0480";
  339. reg = <0x19000 0x0 0x0 0x0 0x0>;
  340. };
  341. };
  342. isa@1f,0 {
  343. #address-cells = <2>;
  344. #size-cells = <1>;
  345. compatible = "isa";
  346. reg = <0xf800 0x0 0x0 0x0 0x0>;
  347. ranges = <1 0 0 0 0 0x100>;
  348. rtc@70 {
  349. compatible = "intel,ce4100-rtc", "motorola,mc146818";
  350. interrupts = <8 3>;
  351. interrupt-parent = <&ioapic1>;
  352. ctrl-reg = <2>;
  353. freq-reg = <0x26>;
  354. reg = <1 0x70 2>;
  355. };
  356. };
  357. };
  358. };
  359. };