smp.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SMP related functions
  4. *
  5. * Copyright IBM Corp. 1999, 2012
  6. * Author(s): Denis Joseph Barrow,
  7. * Martin Schwidefsky <schwidefsky@de.ibm.com>,
  8. * Heiko Carstens <heiko.carstens@de.ibm.com>,
  9. *
  10. * based on other smp stuff by
  11. * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
  12. * (c) 1998 Ingo Molnar
  13. *
  14. * The code outside of smp.c uses logical cpu numbers, only smp.c does
  15. * the translation of logical to physical cpu ids. All new code that
  16. * operates on physical cpu numbers needs to go into smp.c.
  17. */
  18. #define KMSG_COMPONENT "cpu"
  19. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  20. #include <linux/workqueue.h>
  21. #include <linux/bootmem.h>
  22. #include <linux/export.h>
  23. #include <linux/init.h>
  24. #include <linux/mm.h>
  25. #include <linux/err.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/kernel_stat.h>
  28. #include <linux/delay.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/irqflags.h>
  31. #include <linux/cpu.h>
  32. #include <linux/slab.h>
  33. #include <linux/sched/hotplug.h>
  34. #include <linux/sched/task_stack.h>
  35. #include <linux/crash_dump.h>
  36. #include <linux/memblock.h>
  37. #include <linux/kprobes.h>
  38. #include <asm/asm-offsets.h>
  39. #include <asm/diag.h>
  40. #include <asm/switch_to.h>
  41. #include <asm/facility.h>
  42. #include <asm/ipl.h>
  43. #include <asm/setup.h>
  44. #include <asm/irq.h>
  45. #include <asm/tlbflush.h>
  46. #include <asm/vtimer.h>
  47. #include <asm/lowcore.h>
  48. #include <asm/sclp.h>
  49. #include <asm/vdso.h>
  50. #include <asm/debug.h>
  51. #include <asm/os_info.h>
  52. #include <asm/sigp.h>
  53. #include <asm/idle.h>
  54. #include <asm/nmi.h>
  55. #include <asm/topology.h>
  56. #include "entry.h"
  57. enum {
  58. ec_schedule = 0,
  59. ec_call_function_single,
  60. ec_stop_cpu,
  61. };
  62. enum {
  63. CPU_STATE_STANDBY,
  64. CPU_STATE_CONFIGURED,
  65. };
  66. static DEFINE_PER_CPU(struct cpu *, cpu_device);
  67. struct pcpu {
  68. struct lowcore *lowcore; /* lowcore page(s) for the cpu */
  69. unsigned long ec_mask; /* bit mask for ec_xxx functions */
  70. unsigned long ec_clk; /* sigp timestamp for ec_xxx */
  71. signed char state; /* physical cpu state */
  72. signed char polarization; /* physical polarization */
  73. u16 address; /* physical cpu address */
  74. };
  75. static u8 boot_core_type;
  76. static struct pcpu pcpu_devices[NR_CPUS];
  77. unsigned int smp_cpu_mt_shift;
  78. EXPORT_SYMBOL(smp_cpu_mt_shift);
  79. unsigned int smp_cpu_mtid;
  80. EXPORT_SYMBOL(smp_cpu_mtid);
  81. #ifdef CONFIG_CRASH_DUMP
  82. __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
  83. #endif
  84. static unsigned int smp_max_threads __initdata = -1U;
  85. static int __init early_nosmt(char *s)
  86. {
  87. smp_max_threads = 1;
  88. return 0;
  89. }
  90. early_param("nosmt", early_nosmt);
  91. static int __init early_smt(char *s)
  92. {
  93. get_option(&s, &smp_max_threads);
  94. return 0;
  95. }
  96. early_param("smt", early_smt);
  97. /*
  98. * The smp_cpu_state_mutex must be held when changing the state or polarization
  99. * member of a pcpu data structure within the pcpu_devices arreay.
  100. */
  101. DEFINE_MUTEX(smp_cpu_state_mutex);
  102. /*
  103. * Signal processor helper functions.
  104. */
  105. static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
  106. {
  107. int cc;
  108. while (1) {
  109. cc = __pcpu_sigp(addr, order, parm, NULL);
  110. if (cc != SIGP_CC_BUSY)
  111. return cc;
  112. cpu_relax();
  113. }
  114. }
  115. static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
  116. {
  117. int cc, retry;
  118. for (retry = 0; ; retry++) {
  119. cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
  120. if (cc != SIGP_CC_BUSY)
  121. break;
  122. if (retry >= 3)
  123. udelay(10);
  124. }
  125. return cc;
  126. }
  127. static inline int pcpu_stopped(struct pcpu *pcpu)
  128. {
  129. u32 uninitialized_var(status);
  130. if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
  131. 0, &status) != SIGP_CC_STATUS_STORED)
  132. return 0;
  133. return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
  134. }
  135. static inline int pcpu_running(struct pcpu *pcpu)
  136. {
  137. if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
  138. 0, NULL) != SIGP_CC_STATUS_STORED)
  139. return 1;
  140. /* Status stored condition code is equivalent to cpu not running. */
  141. return 0;
  142. }
  143. /*
  144. * Find struct pcpu by cpu address.
  145. */
  146. static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
  147. {
  148. int cpu;
  149. for_each_cpu(cpu, mask)
  150. if (pcpu_devices[cpu].address == address)
  151. return pcpu_devices + cpu;
  152. return NULL;
  153. }
  154. static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
  155. {
  156. int order;
  157. if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
  158. return;
  159. order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
  160. pcpu->ec_clk = get_tod_clock_fast();
  161. pcpu_sigp_retry(pcpu, order, 0);
  162. }
  163. #define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
  164. #define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
  165. static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
  166. {
  167. unsigned long async_stack, panic_stack;
  168. struct lowcore *lc;
  169. if (pcpu != &pcpu_devices[0]) {
  170. pcpu->lowcore = (struct lowcore *)
  171. __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
  172. async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
  173. panic_stack = __get_free_page(GFP_KERNEL);
  174. if (!pcpu->lowcore || !panic_stack || !async_stack)
  175. goto out;
  176. } else {
  177. async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET;
  178. panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET;
  179. }
  180. lc = pcpu->lowcore;
  181. memcpy(lc, &S390_lowcore, 512);
  182. memset((char *) lc + 512, 0, sizeof(*lc) - 512);
  183. lc->async_stack = async_stack + ASYNC_FRAME_OFFSET;
  184. lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET;
  185. lc->cpu_nr = cpu;
  186. lc->spinlock_lockval = arch_spin_lockval(cpu);
  187. lc->spinlock_index = 0;
  188. lc->br_r1_trampoline = 0x07f1; /* br %r1 */
  189. if (nmi_alloc_per_cpu(lc))
  190. goto out;
  191. if (vdso_alloc_per_cpu(lc))
  192. goto out_mcesa;
  193. lowcore_ptr[cpu] = lc;
  194. pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
  195. return 0;
  196. out_mcesa:
  197. nmi_free_per_cpu(lc);
  198. out:
  199. if (pcpu != &pcpu_devices[0]) {
  200. free_page(panic_stack);
  201. free_pages(async_stack, ASYNC_ORDER);
  202. free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
  203. }
  204. return -ENOMEM;
  205. }
  206. #ifdef CONFIG_HOTPLUG_CPU
  207. static void pcpu_free_lowcore(struct pcpu *pcpu)
  208. {
  209. pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
  210. lowcore_ptr[pcpu - pcpu_devices] = NULL;
  211. vdso_free_per_cpu(pcpu->lowcore);
  212. nmi_free_per_cpu(pcpu->lowcore);
  213. if (pcpu == &pcpu_devices[0])
  214. return;
  215. free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET);
  216. free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER);
  217. free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
  218. }
  219. #endif /* CONFIG_HOTPLUG_CPU */
  220. static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
  221. {
  222. struct lowcore *lc = pcpu->lowcore;
  223. cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
  224. cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
  225. lc->cpu_nr = cpu;
  226. lc->spinlock_lockval = arch_spin_lockval(cpu);
  227. lc->spinlock_index = 0;
  228. lc->percpu_offset = __per_cpu_offset[cpu];
  229. lc->kernel_asce = S390_lowcore.kernel_asce;
  230. lc->user_asce = S390_lowcore.kernel_asce;
  231. lc->machine_flags = S390_lowcore.machine_flags;
  232. lc->user_timer = lc->system_timer = lc->steal_timer = 0;
  233. __ctl_store(lc->cregs_save_area, 0, 15);
  234. lc->cregs_save_area[1] = lc->kernel_asce;
  235. lc->cregs_save_area[7] = lc->vdso_asce;
  236. save_access_regs((unsigned int *) lc->access_regs_save_area);
  237. memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
  238. sizeof(lc->stfle_fac_list));
  239. memcpy(lc->alt_stfle_fac_list, S390_lowcore.alt_stfle_fac_list,
  240. sizeof(lc->alt_stfle_fac_list));
  241. arch_spin_lock_setup(cpu);
  242. }
  243. static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
  244. {
  245. struct lowcore *lc = pcpu->lowcore;
  246. lc->kernel_stack = (unsigned long) task_stack_page(tsk)
  247. + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
  248. lc->current_task = (unsigned long) tsk;
  249. lc->lpp = LPP_MAGIC;
  250. lc->current_pid = tsk->pid;
  251. lc->user_timer = tsk->thread.user_timer;
  252. lc->guest_timer = tsk->thread.guest_timer;
  253. lc->system_timer = tsk->thread.system_timer;
  254. lc->hardirq_timer = tsk->thread.hardirq_timer;
  255. lc->softirq_timer = tsk->thread.softirq_timer;
  256. lc->steal_timer = 0;
  257. }
  258. static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
  259. {
  260. struct lowcore *lc = pcpu->lowcore;
  261. lc->restart_stack = lc->kernel_stack;
  262. lc->restart_fn = (unsigned long) func;
  263. lc->restart_data = (unsigned long) data;
  264. lc->restart_source = -1UL;
  265. pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
  266. }
  267. /*
  268. * Call function via PSW restart on pcpu and stop the current cpu.
  269. */
  270. static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
  271. void *data, unsigned long stack)
  272. {
  273. struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
  274. unsigned long source_cpu = stap();
  275. __load_psw_mask(PSW_KERNEL_BITS);
  276. if (pcpu->address == source_cpu)
  277. func(data); /* should not return */
  278. /* Stop target cpu (if func returns this stops the current cpu). */
  279. pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
  280. /* Restart func on the target cpu and stop the current cpu. */
  281. mem_assign_absolute(lc->restart_stack, stack);
  282. mem_assign_absolute(lc->restart_fn, (unsigned long) func);
  283. mem_assign_absolute(lc->restart_data, (unsigned long) data);
  284. mem_assign_absolute(lc->restart_source, source_cpu);
  285. __bpon();
  286. asm volatile(
  287. "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
  288. " brc 2,0b # busy, try again\n"
  289. "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
  290. " brc 2,1b # busy, try again\n"
  291. : : "d" (pcpu->address), "d" (source_cpu),
  292. "K" (SIGP_RESTART), "K" (SIGP_STOP)
  293. : "0", "1", "cc");
  294. for (;;) ;
  295. }
  296. /*
  297. * Enable additional logical cpus for multi-threading.
  298. */
  299. static int pcpu_set_smt(unsigned int mtid)
  300. {
  301. int cc;
  302. if (smp_cpu_mtid == mtid)
  303. return 0;
  304. cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
  305. if (cc == 0) {
  306. smp_cpu_mtid = mtid;
  307. smp_cpu_mt_shift = 0;
  308. while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
  309. smp_cpu_mt_shift++;
  310. pcpu_devices[0].address = stap();
  311. }
  312. return cc;
  313. }
  314. /*
  315. * Call function on an online CPU.
  316. */
  317. void smp_call_online_cpu(void (*func)(void *), void *data)
  318. {
  319. struct pcpu *pcpu;
  320. /* Use the current cpu if it is online. */
  321. pcpu = pcpu_find_address(cpu_online_mask, stap());
  322. if (!pcpu)
  323. /* Use the first online cpu. */
  324. pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
  325. pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
  326. }
  327. /*
  328. * Call function on the ipl CPU.
  329. */
  330. void smp_call_ipl_cpu(void (*func)(void *), void *data)
  331. {
  332. struct lowcore *lc = pcpu_devices->lowcore;
  333. if (pcpu_devices[0].address == stap())
  334. lc = &S390_lowcore;
  335. pcpu_delegate(&pcpu_devices[0], func, data,
  336. lc->panic_stack - PANIC_FRAME_OFFSET + PAGE_SIZE);
  337. }
  338. int smp_find_processor_id(u16 address)
  339. {
  340. int cpu;
  341. for_each_present_cpu(cpu)
  342. if (pcpu_devices[cpu].address == address)
  343. return cpu;
  344. return -1;
  345. }
  346. bool arch_vcpu_is_preempted(int cpu)
  347. {
  348. if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
  349. return false;
  350. if (pcpu_running(pcpu_devices + cpu))
  351. return false;
  352. return true;
  353. }
  354. EXPORT_SYMBOL(arch_vcpu_is_preempted);
  355. void smp_yield_cpu(int cpu)
  356. {
  357. if (MACHINE_HAS_DIAG9C) {
  358. diag_stat_inc_norecursion(DIAG_STAT_X09C);
  359. asm volatile("diag %0,0,0x9c"
  360. : : "d" (pcpu_devices[cpu].address));
  361. } else if (MACHINE_HAS_DIAG44) {
  362. diag_stat_inc_norecursion(DIAG_STAT_X044);
  363. asm volatile("diag 0,0,0x44");
  364. }
  365. }
  366. /*
  367. * Send cpus emergency shutdown signal. This gives the cpus the
  368. * opportunity to complete outstanding interrupts.
  369. */
  370. void notrace smp_emergency_stop(void)
  371. {
  372. cpumask_t cpumask;
  373. u64 end;
  374. int cpu;
  375. cpumask_copy(&cpumask, cpu_online_mask);
  376. cpumask_clear_cpu(smp_processor_id(), &cpumask);
  377. end = get_tod_clock() + (1000000UL << 12);
  378. for_each_cpu(cpu, &cpumask) {
  379. struct pcpu *pcpu = pcpu_devices + cpu;
  380. set_bit(ec_stop_cpu, &pcpu->ec_mask);
  381. while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
  382. 0, NULL) == SIGP_CC_BUSY &&
  383. get_tod_clock() < end)
  384. cpu_relax();
  385. }
  386. while (get_tod_clock() < end) {
  387. for_each_cpu(cpu, &cpumask)
  388. if (pcpu_stopped(pcpu_devices + cpu))
  389. cpumask_clear_cpu(cpu, &cpumask);
  390. if (cpumask_empty(&cpumask))
  391. break;
  392. cpu_relax();
  393. }
  394. }
  395. NOKPROBE_SYMBOL(smp_emergency_stop);
  396. /*
  397. * Stop all cpus but the current one.
  398. */
  399. void smp_send_stop(void)
  400. {
  401. int cpu;
  402. /* Disable all interrupts/machine checks */
  403. __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
  404. trace_hardirqs_off();
  405. debug_set_critical();
  406. if (oops_in_progress)
  407. smp_emergency_stop();
  408. /* stop all processors */
  409. for_each_online_cpu(cpu) {
  410. if (cpu == smp_processor_id())
  411. continue;
  412. pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0);
  413. while (!pcpu_stopped(pcpu_devices + cpu))
  414. cpu_relax();
  415. }
  416. }
  417. /*
  418. * This is the main routine where commands issued by other
  419. * cpus are handled.
  420. */
  421. static void smp_handle_ext_call(void)
  422. {
  423. unsigned long bits;
  424. /* handle bit signal external calls */
  425. bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
  426. if (test_bit(ec_stop_cpu, &bits))
  427. smp_stop_cpu();
  428. if (test_bit(ec_schedule, &bits))
  429. scheduler_ipi();
  430. if (test_bit(ec_call_function_single, &bits))
  431. generic_smp_call_function_single_interrupt();
  432. }
  433. static void do_ext_call_interrupt(struct ext_code ext_code,
  434. unsigned int param32, unsigned long param64)
  435. {
  436. inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
  437. smp_handle_ext_call();
  438. }
  439. void arch_send_call_function_ipi_mask(const struct cpumask *mask)
  440. {
  441. int cpu;
  442. for_each_cpu(cpu, mask)
  443. pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
  444. }
  445. void arch_send_call_function_single_ipi(int cpu)
  446. {
  447. pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
  448. }
  449. /*
  450. * this function sends a 'reschedule' IPI to another CPU.
  451. * it goes straight through and wastes no time serializing
  452. * anything. Worst case is that we lose a reschedule ...
  453. */
  454. void smp_send_reschedule(int cpu)
  455. {
  456. pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
  457. }
  458. /*
  459. * parameter area for the set/clear control bit callbacks
  460. */
  461. struct ec_creg_mask_parms {
  462. unsigned long orval;
  463. unsigned long andval;
  464. int cr;
  465. };
  466. /*
  467. * callback for setting/clearing control bits
  468. */
  469. static void smp_ctl_bit_callback(void *info)
  470. {
  471. struct ec_creg_mask_parms *pp = info;
  472. unsigned long cregs[16];
  473. __ctl_store(cregs, 0, 15);
  474. cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
  475. __ctl_load(cregs, 0, 15);
  476. }
  477. /*
  478. * Set a bit in a control register of all cpus
  479. */
  480. void smp_ctl_set_bit(int cr, int bit)
  481. {
  482. struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
  483. on_each_cpu(smp_ctl_bit_callback, &parms, 1);
  484. }
  485. EXPORT_SYMBOL(smp_ctl_set_bit);
  486. /*
  487. * Clear a bit in a control register of all cpus
  488. */
  489. void smp_ctl_clear_bit(int cr, int bit)
  490. {
  491. struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
  492. on_each_cpu(smp_ctl_bit_callback, &parms, 1);
  493. }
  494. EXPORT_SYMBOL(smp_ctl_clear_bit);
  495. #ifdef CONFIG_CRASH_DUMP
  496. int smp_store_status(int cpu)
  497. {
  498. struct pcpu *pcpu = pcpu_devices + cpu;
  499. unsigned long pa;
  500. pa = __pa(&pcpu->lowcore->floating_pt_save_area);
  501. if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
  502. pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
  503. return -EIO;
  504. if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
  505. return 0;
  506. pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK);
  507. if (MACHINE_HAS_GS)
  508. pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK;
  509. if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
  510. pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
  511. return -EIO;
  512. return 0;
  513. }
  514. /*
  515. * Collect CPU state of the previous, crashed system.
  516. * There are four cases:
  517. * 1) standard zfcp dump
  518. * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
  519. * The state for all CPUs except the boot CPU needs to be collected
  520. * with sigp stop-and-store-status. The boot CPU state is located in
  521. * the absolute lowcore of the memory stored in the HSA. The zcore code
  522. * will copy the boot CPU state from the HSA.
  523. * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
  524. * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
  525. * The state for all CPUs except the boot CPU needs to be collected
  526. * with sigp stop-and-store-status. The firmware or the boot-loader
  527. * stored the registers of the boot CPU in the absolute lowcore in the
  528. * memory of the old system.
  529. * 3) kdump and the old kernel did not store the CPU state,
  530. * or stand-alone kdump for DASD
  531. * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
  532. * The state for all CPUs except the boot CPU needs to be collected
  533. * with sigp stop-and-store-status. The kexec code or the boot-loader
  534. * stored the registers of the boot CPU in the memory of the old system.
  535. * 4) kdump and the old kernel stored the CPU state
  536. * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
  537. * This case does not exist for s390 anymore, setup_arch explicitly
  538. * deactivates the elfcorehdr= kernel parameter
  539. */
  540. static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
  541. bool is_boot_cpu, unsigned long page)
  542. {
  543. __vector128 *vxrs = (__vector128 *) page;
  544. if (is_boot_cpu)
  545. vxrs = boot_cpu_vector_save_area;
  546. else
  547. __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
  548. save_area_add_vxrs(sa, vxrs);
  549. }
  550. static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
  551. bool is_boot_cpu, unsigned long page)
  552. {
  553. void *regs = (void *) page;
  554. if (is_boot_cpu)
  555. copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
  556. else
  557. __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
  558. save_area_add_regs(sa, regs);
  559. }
  560. void __init smp_save_dump_cpus(void)
  561. {
  562. int addr, boot_cpu_addr, max_cpu_addr;
  563. struct save_area *sa;
  564. unsigned long page;
  565. bool is_boot_cpu;
  566. if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
  567. /* No previous system present, normal boot. */
  568. return;
  569. /* Allocate a page as dumping area for the store status sigps */
  570. page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31);
  571. /* Set multi-threading state to the previous system. */
  572. pcpu_set_smt(sclp.mtid_prev);
  573. boot_cpu_addr = stap();
  574. max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
  575. for (addr = 0; addr <= max_cpu_addr; addr++) {
  576. if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
  577. SIGP_CC_NOT_OPERATIONAL)
  578. continue;
  579. is_boot_cpu = (addr == boot_cpu_addr);
  580. /* Allocate save area */
  581. sa = save_area_alloc(is_boot_cpu);
  582. if (!sa)
  583. panic("could not allocate memory for save area\n");
  584. if (MACHINE_HAS_VX)
  585. /* Get the vector registers */
  586. smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
  587. /*
  588. * For a zfcp dump OLDMEM_BASE == NULL and the registers
  589. * of the boot CPU are stored in the HSA. To retrieve
  590. * these registers an SCLP request is required which is
  591. * done by drivers/s390/char/zcore.c:init_cpu_info()
  592. */
  593. if (!is_boot_cpu || OLDMEM_BASE)
  594. /* Get the CPU registers */
  595. smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
  596. }
  597. memblock_free(page, PAGE_SIZE);
  598. diag308_reset();
  599. pcpu_set_smt(0);
  600. }
  601. #endif /* CONFIG_CRASH_DUMP */
  602. void smp_cpu_set_polarization(int cpu, int val)
  603. {
  604. pcpu_devices[cpu].polarization = val;
  605. }
  606. int smp_cpu_get_polarization(int cpu)
  607. {
  608. return pcpu_devices[cpu].polarization;
  609. }
  610. static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
  611. {
  612. static int use_sigp_detection;
  613. int address;
  614. if (use_sigp_detection || sclp_get_core_info(info, early)) {
  615. use_sigp_detection = 1;
  616. for (address = 0;
  617. address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
  618. address += (1U << smp_cpu_mt_shift)) {
  619. if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
  620. SIGP_CC_NOT_OPERATIONAL)
  621. continue;
  622. info->core[info->configured].core_id =
  623. address >> smp_cpu_mt_shift;
  624. info->configured++;
  625. }
  626. info->combined = info->configured;
  627. }
  628. }
  629. static int smp_add_present_cpu(int cpu);
  630. static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail,
  631. bool configured, bool early)
  632. {
  633. struct pcpu *pcpu;
  634. int cpu, nr, i;
  635. u16 address;
  636. nr = 0;
  637. if (sclp.has_core_type && core->type != boot_core_type)
  638. return nr;
  639. cpu = cpumask_first(avail);
  640. address = core->core_id << smp_cpu_mt_shift;
  641. for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) {
  642. if (pcpu_find_address(cpu_present_mask, address + i))
  643. continue;
  644. pcpu = pcpu_devices + cpu;
  645. pcpu->address = address + i;
  646. if (configured)
  647. pcpu->state = CPU_STATE_CONFIGURED;
  648. else
  649. pcpu->state = CPU_STATE_STANDBY;
  650. smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
  651. set_cpu_present(cpu, true);
  652. if (!early && smp_add_present_cpu(cpu) != 0)
  653. set_cpu_present(cpu, false);
  654. else
  655. nr++;
  656. cpumask_clear_cpu(cpu, avail);
  657. cpu = cpumask_next(cpu, avail);
  658. }
  659. return nr;
  660. }
  661. static int __smp_rescan_cpus(struct sclp_core_info *info, bool early)
  662. {
  663. struct sclp_core_entry *core;
  664. cpumask_t avail;
  665. bool configured;
  666. u16 core_id;
  667. int nr, i;
  668. nr = 0;
  669. cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
  670. /*
  671. * Add IPL core first (which got logical CPU number 0) to make sure
  672. * that all SMT threads get subsequent logical CPU numbers.
  673. */
  674. if (early) {
  675. core_id = pcpu_devices[0].address >> smp_cpu_mt_shift;
  676. for (i = 0; i < info->configured; i++) {
  677. core = &info->core[i];
  678. if (core->core_id == core_id) {
  679. nr += smp_add_core(core, &avail, true, early);
  680. break;
  681. }
  682. }
  683. }
  684. for (i = 0; i < info->combined; i++) {
  685. configured = i < info->configured;
  686. nr += smp_add_core(&info->core[i], &avail, configured, early);
  687. }
  688. return nr;
  689. }
  690. void __init smp_detect_cpus(void)
  691. {
  692. unsigned int cpu, mtid, c_cpus, s_cpus;
  693. struct sclp_core_info *info;
  694. u16 address;
  695. /* Get CPU information */
  696. info = memblock_virt_alloc(sizeof(*info), 8);
  697. smp_get_core_info(info, 1);
  698. /* Find boot CPU type */
  699. if (sclp.has_core_type) {
  700. address = stap();
  701. for (cpu = 0; cpu < info->combined; cpu++)
  702. if (info->core[cpu].core_id == address) {
  703. /* The boot cpu dictates the cpu type. */
  704. boot_core_type = info->core[cpu].type;
  705. break;
  706. }
  707. if (cpu >= info->combined)
  708. panic("Could not find boot CPU type");
  709. }
  710. /* Set multi-threading state for the current system */
  711. mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
  712. mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
  713. pcpu_set_smt(mtid);
  714. /* Print number of CPUs */
  715. c_cpus = s_cpus = 0;
  716. for (cpu = 0; cpu < info->combined; cpu++) {
  717. if (sclp.has_core_type &&
  718. info->core[cpu].type != boot_core_type)
  719. continue;
  720. if (cpu < info->configured)
  721. c_cpus += smp_cpu_mtid + 1;
  722. else
  723. s_cpus += smp_cpu_mtid + 1;
  724. }
  725. pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
  726. /* Add CPUs present at boot */
  727. get_online_cpus();
  728. __smp_rescan_cpus(info, true);
  729. put_online_cpus();
  730. memblock_free_early((unsigned long)info, sizeof(*info));
  731. }
  732. /*
  733. * Activate a secondary processor.
  734. */
  735. static void smp_start_secondary(void *cpuvoid)
  736. {
  737. int cpu = smp_processor_id();
  738. S390_lowcore.last_update_clock = get_tod_clock();
  739. S390_lowcore.restart_stack = (unsigned long) restart_stack;
  740. S390_lowcore.restart_fn = (unsigned long) do_restart;
  741. S390_lowcore.restart_data = 0;
  742. S390_lowcore.restart_source = -1UL;
  743. restore_access_regs(S390_lowcore.access_regs_save_area);
  744. __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
  745. __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
  746. set_cpu_flag(CIF_ASCE_PRIMARY);
  747. set_cpu_flag(CIF_ASCE_SECONDARY);
  748. cpu_init();
  749. preempt_disable();
  750. init_cpu_timer();
  751. vtime_init();
  752. pfault_init();
  753. notify_cpu_starting(cpu);
  754. if (topology_cpu_dedicated(cpu))
  755. set_cpu_flag(CIF_DEDICATED_CPU);
  756. else
  757. clear_cpu_flag(CIF_DEDICATED_CPU);
  758. set_cpu_online(cpu, true);
  759. inc_irq_stat(CPU_RST);
  760. local_irq_enable();
  761. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  762. }
  763. /* Upping and downing of CPUs */
  764. int __cpu_up(unsigned int cpu, struct task_struct *tidle)
  765. {
  766. struct pcpu *pcpu;
  767. int base, i, rc;
  768. pcpu = pcpu_devices + cpu;
  769. if (pcpu->state != CPU_STATE_CONFIGURED)
  770. return -EIO;
  771. base = smp_get_base_cpu(cpu);
  772. for (i = 0; i <= smp_cpu_mtid; i++) {
  773. if (base + i < nr_cpu_ids)
  774. if (cpu_online(base + i))
  775. break;
  776. }
  777. /*
  778. * If this is the first CPU of the core to get online
  779. * do an initial CPU reset.
  780. */
  781. if (i > smp_cpu_mtid &&
  782. pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
  783. SIGP_CC_ORDER_CODE_ACCEPTED)
  784. return -EIO;
  785. rc = pcpu_alloc_lowcore(pcpu, cpu);
  786. if (rc)
  787. return rc;
  788. pcpu_prepare_secondary(pcpu, cpu);
  789. pcpu_attach_task(pcpu, tidle);
  790. pcpu_start_fn(pcpu, smp_start_secondary, NULL);
  791. /* Wait until cpu puts itself in the online & active maps */
  792. while (!cpu_online(cpu))
  793. cpu_relax();
  794. return 0;
  795. }
  796. static unsigned int setup_possible_cpus __initdata;
  797. static int __init _setup_possible_cpus(char *s)
  798. {
  799. get_option(&s, &setup_possible_cpus);
  800. return 0;
  801. }
  802. early_param("possible_cpus", _setup_possible_cpus);
  803. #ifdef CONFIG_HOTPLUG_CPU
  804. int __cpu_disable(void)
  805. {
  806. unsigned long cregs[16];
  807. /* Handle possible pending IPIs */
  808. smp_handle_ext_call();
  809. set_cpu_online(smp_processor_id(), false);
  810. /* Disable pseudo page faults on this cpu. */
  811. pfault_fini();
  812. /* Disable interrupt sources via control register. */
  813. __ctl_store(cregs, 0, 15);
  814. cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
  815. cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
  816. cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
  817. __ctl_load(cregs, 0, 15);
  818. clear_cpu_flag(CIF_NOHZ_DELAY);
  819. return 0;
  820. }
  821. void __cpu_die(unsigned int cpu)
  822. {
  823. struct pcpu *pcpu;
  824. /* Wait until target cpu is down */
  825. pcpu = pcpu_devices + cpu;
  826. while (!pcpu_stopped(pcpu))
  827. cpu_relax();
  828. pcpu_free_lowcore(pcpu);
  829. cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
  830. cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
  831. }
  832. void __noreturn cpu_die(void)
  833. {
  834. idle_task_exit();
  835. __bpon();
  836. pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
  837. for (;;) ;
  838. }
  839. #endif /* CONFIG_HOTPLUG_CPU */
  840. void __init smp_fill_possible_mask(void)
  841. {
  842. unsigned int possible, sclp_max, cpu;
  843. sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
  844. sclp_max = min(smp_max_threads, sclp_max);
  845. sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
  846. possible = setup_possible_cpus ?: nr_cpu_ids;
  847. possible = min(possible, sclp_max);
  848. for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
  849. set_cpu_possible(cpu, true);
  850. }
  851. void __init smp_prepare_cpus(unsigned int max_cpus)
  852. {
  853. /* request the 0x1201 emergency signal external interrupt */
  854. if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
  855. panic("Couldn't request external interrupt 0x1201");
  856. /* request the 0x1202 external call external interrupt */
  857. if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
  858. panic("Couldn't request external interrupt 0x1202");
  859. }
  860. void __init smp_prepare_boot_cpu(void)
  861. {
  862. struct pcpu *pcpu = pcpu_devices;
  863. WARN_ON(!cpu_present(0) || !cpu_online(0));
  864. pcpu->state = CPU_STATE_CONFIGURED;
  865. pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
  866. S390_lowcore.percpu_offset = __per_cpu_offset[0];
  867. smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
  868. }
  869. void __init smp_cpus_done(unsigned int max_cpus)
  870. {
  871. }
  872. void __init smp_setup_processor_id(void)
  873. {
  874. pcpu_devices[0].address = stap();
  875. S390_lowcore.cpu_nr = 0;
  876. S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
  877. S390_lowcore.spinlock_index = 0;
  878. }
  879. /*
  880. * the frequency of the profiling timer can be changed
  881. * by writing a multiplier value into /proc/profile.
  882. *
  883. * usually you want to run this on all CPUs ;)
  884. */
  885. int setup_profiling_timer(unsigned int multiplier)
  886. {
  887. return 0;
  888. }
  889. #ifdef CONFIG_HOTPLUG_CPU
  890. static ssize_t cpu_configure_show(struct device *dev,
  891. struct device_attribute *attr, char *buf)
  892. {
  893. ssize_t count;
  894. mutex_lock(&smp_cpu_state_mutex);
  895. count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
  896. mutex_unlock(&smp_cpu_state_mutex);
  897. return count;
  898. }
  899. static ssize_t cpu_configure_store(struct device *dev,
  900. struct device_attribute *attr,
  901. const char *buf, size_t count)
  902. {
  903. struct pcpu *pcpu;
  904. int cpu, val, rc, i;
  905. char delim;
  906. if (sscanf(buf, "%d %c", &val, &delim) != 1)
  907. return -EINVAL;
  908. if (val != 0 && val != 1)
  909. return -EINVAL;
  910. get_online_cpus();
  911. mutex_lock(&smp_cpu_state_mutex);
  912. rc = -EBUSY;
  913. /* disallow configuration changes of online cpus and cpu 0 */
  914. cpu = dev->id;
  915. cpu = smp_get_base_cpu(cpu);
  916. if (cpu == 0)
  917. goto out;
  918. for (i = 0; i <= smp_cpu_mtid; i++)
  919. if (cpu_online(cpu + i))
  920. goto out;
  921. pcpu = pcpu_devices + cpu;
  922. rc = 0;
  923. switch (val) {
  924. case 0:
  925. if (pcpu->state != CPU_STATE_CONFIGURED)
  926. break;
  927. rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
  928. if (rc)
  929. break;
  930. for (i = 0; i <= smp_cpu_mtid; i++) {
  931. if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
  932. continue;
  933. pcpu[i].state = CPU_STATE_STANDBY;
  934. smp_cpu_set_polarization(cpu + i,
  935. POLARIZATION_UNKNOWN);
  936. }
  937. topology_expect_change();
  938. break;
  939. case 1:
  940. if (pcpu->state != CPU_STATE_STANDBY)
  941. break;
  942. rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
  943. if (rc)
  944. break;
  945. for (i = 0; i <= smp_cpu_mtid; i++) {
  946. if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
  947. continue;
  948. pcpu[i].state = CPU_STATE_CONFIGURED;
  949. smp_cpu_set_polarization(cpu + i,
  950. POLARIZATION_UNKNOWN);
  951. }
  952. topology_expect_change();
  953. break;
  954. default:
  955. break;
  956. }
  957. out:
  958. mutex_unlock(&smp_cpu_state_mutex);
  959. put_online_cpus();
  960. return rc ? rc : count;
  961. }
  962. static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
  963. #endif /* CONFIG_HOTPLUG_CPU */
  964. static ssize_t show_cpu_address(struct device *dev,
  965. struct device_attribute *attr, char *buf)
  966. {
  967. return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
  968. }
  969. static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
  970. static struct attribute *cpu_common_attrs[] = {
  971. #ifdef CONFIG_HOTPLUG_CPU
  972. &dev_attr_configure.attr,
  973. #endif
  974. &dev_attr_address.attr,
  975. NULL,
  976. };
  977. static struct attribute_group cpu_common_attr_group = {
  978. .attrs = cpu_common_attrs,
  979. };
  980. static struct attribute *cpu_online_attrs[] = {
  981. &dev_attr_idle_count.attr,
  982. &dev_attr_idle_time_us.attr,
  983. NULL,
  984. };
  985. static struct attribute_group cpu_online_attr_group = {
  986. .attrs = cpu_online_attrs,
  987. };
  988. static int smp_cpu_online(unsigned int cpu)
  989. {
  990. struct device *s = &per_cpu(cpu_device, cpu)->dev;
  991. return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
  992. }
  993. static int smp_cpu_pre_down(unsigned int cpu)
  994. {
  995. struct device *s = &per_cpu(cpu_device, cpu)->dev;
  996. sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
  997. return 0;
  998. }
  999. static int smp_add_present_cpu(int cpu)
  1000. {
  1001. struct device *s;
  1002. struct cpu *c;
  1003. int rc;
  1004. c = kzalloc(sizeof(*c), GFP_KERNEL);
  1005. if (!c)
  1006. return -ENOMEM;
  1007. per_cpu(cpu_device, cpu) = c;
  1008. s = &c->dev;
  1009. c->hotpluggable = 1;
  1010. rc = register_cpu(c, cpu);
  1011. if (rc)
  1012. goto out;
  1013. rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
  1014. if (rc)
  1015. goto out_cpu;
  1016. rc = topology_cpu_init(c);
  1017. if (rc)
  1018. goto out_topology;
  1019. return 0;
  1020. out_topology:
  1021. sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
  1022. out_cpu:
  1023. #ifdef CONFIG_HOTPLUG_CPU
  1024. unregister_cpu(c);
  1025. #endif
  1026. out:
  1027. return rc;
  1028. }
  1029. #ifdef CONFIG_HOTPLUG_CPU
  1030. int __ref smp_rescan_cpus(void)
  1031. {
  1032. struct sclp_core_info *info;
  1033. int nr;
  1034. info = kzalloc(sizeof(*info), GFP_KERNEL);
  1035. if (!info)
  1036. return -ENOMEM;
  1037. smp_get_core_info(info, 0);
  1038. get_online_cpus();
  1039. mutex_lock(&smp_cpu_state_mutex);
  1040. nr = __smp_rescan_cpus(info, false);
  1041. mutex_unlock(&smp_cpu_state_mutex);
  1042. put_online_cpus();
  1043. kfree(info);
  1044. if (nr)
  1045. topology_schedule_update();
  1046. return 0;
  1047. }
  1048. static ssize_t __ref rescan_store(struct device *dev,
  1049. struct device_attribute *attr,
  1050. const char *buf,
  1051. size_t count)
  1052. {
  1053. int rc;
  1054. rc = lock_device_hotplug_sysfs();
  1055. if (rc)
  1056. return rc;
  1057. rc = smp_rescan_cpus();
  1058. unlock_device_hotplug();
  1059. return rc ? rc : count;
  1060. }
  1061. static DEVICE_ATTR_WO(rescan);
  1062. #endif /* CONFIG_HOTPLUG_CPU */
  1063. static int __init s390_smp_init(void)
  1064. {
  1065. int cpu, rc = 0;
  1066. #ifdef CONFIG_HOTPLUG_CPU
  1067. rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
  1068. if (rc)
  1069. return rc;
  1070. #endif
  1071. for_each_present_cpu(cpu) {
  1072. rc = smp_add_present_cpu(cpu);
  1073. if (rc)
  1074. goto out;
  1075. }
  1076. rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
  1077. smp_cpu_online, smp_cpu_pre_down);
  1078. rc = rc <= 0 ? rc : 0;
  1079. out:
  1080. return rc;
  1081. }
  1082. subsys_initcall(s390_smp_init);