head64.S 3.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright IBM Corp. 1999, 2010
  4. *
  5. * Author(s): Hartmut Penner <hp@de.ibm.com>
  6. * Martin Schwidefsky <schwidefsky@de.ibm.com>
  7. * Rob van der Heij <rvdhei@iae.nl>
  8. * Heiko Carstens <heiko.carstens@de.ibm.com>
  9. *
  10. */
  11. #include <linux/init.h>
  12. #include <linux/linkage.h>
  13. #include <asm/asm-offsets.h>
  14. #include <asm/thread_info.h>
  15. #include <asm/page.h>
  16. __HEAD
  17. ENTRY(startup_continue)
  18. tm __LC_STFLE_FAC_LIST+5,0x80 # LPP available ?
  19. jz 0f
  20. xc __LC_LPP+1(7,0),__LC_LPP+1 # clear lpp and current_pid
  21. mvi __LC_LPP,0x80 # and set LPP_MAGIC
  22. .insn s,0xb2800000,__LC_LPP # load program parameter
  23. 0: larl %r1,tod_clock_base
  24. mvc 0(16,%r1),__LC_BOOT_CLOCK
  25. larl %r13,.LPG1 # get base
  26. lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
  27. lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
  28. # move IPL device to lowcore
  29. larl %r0,boot_vdso_data
  30. stg %r0,__LC_VDSO_PER_CPU
  31. #
  32. # Setup stack
  33. #
  34. larl %r14,init_task
  35. stg %r14,__LC_CURRENT
  36. larl %r15,init_thread_union
  37. aghi %r15,1<<(PAGE_SHIFT+THREAD_SIZE_ORDER) # init_task_union + THREAD_SIZE
  38. stg %r15,__LC_KERNEL_STACK # set end of kernel stack
  39. aghi %r15,-160
  40. #
  41. # Early setup functions that may not rely on an initialized bss section,
  42. # like moving the initrd. Returns with an initialized bss section.
  43. #
  44. brasl %r14,startup_init_nobss
  45. #
  46. # Early machine initialization and detection functions.
  47. #
  48. brasl %r14,startup_init
  49. # check control registers
  50. stctg %c0,%c15,0(%r15)
  51. oi 6(%r15),0x60 # enable sigp emergency & external call
  52. oi 4(%r15),0x10 # switch on low address proctection
  53. lctlg %c0,%c15,0(%r15)
  54. lam 0,15,.Laregs-.LPG1(%r13) # load acrs needed by uaccess
  55. brasl %r14,start_kernel # go to C code
  56. #
  57. # We returned from start_kernel ?!? PANIK
  58. #
  59. basr %r13,0
  60. lpswe .Ldw-.(%r13) # load disabled wait psw
  61. .align 16
  62. .LPG1:
  63. .Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
  64. .quad 0 # cr1: primary space segment table
  65. .quad .Lduct # cr2: dispatchable unit control table
  66. .quad 0 # cr3: instruction authorization
  67. .quad 0xffff # cr4: instruction authorization
  68. .quad .Lduct # cr5: primary-aste origin
  69. .quad 0 # cr6: I/O interrupts
  70. .quad 0 # cr7: secondary space segment table
  71. .quad 0 # cr8: access registers translation
  72. .quad 0 # cr9: tracing off
  73. .quad 0 # cr10: tracing off
  74. .quad 0 # cr11: tracing off
  75. .quad 0 # cr12: tracing off
  76. .quad 0 # cr13: home space segment table
  77. .quad 0xc0000000 # cr14: machine check handling off
  78. .quad .Llinkage_stack # cr15: linkage stack operations
  79. .Lpcmsk:.quad 0x0000000180000000
  80. .L4malign:.quad 0xffffffffffc00000
  81. .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
  82. .Lnop: .long 0x07000700
  83. .Lparmaddr:
  84. .quad PARMAREA
  85. .align 64
  86. .Lduct: .long 0,.Laste,.Laste,0,.Lduald,0,0,0
  87. .long 0,0,0,0,0,0,0,0
  88. .Laste: .quad 0,0xffffffffffffffff,0,0,0,0,0,0
  89. .align 128
  90. .Lduald:.rept 8
  91. .long 0x80000000,0,0,0 # invalid access-list entries
  92. .endr
  93. .Llinkage_stack:
  94. .long 0,0,0x89000000,0,0,0,0x8a000000,0
  95. .Ldw: .quad 0x0002000180000000,0x0000000000000000
  96. .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0