dma.h 5.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* asm/dma.h: Defines for using and allocating dma channels.
  3. * Written by Hennus Bergman, 1992.
  4. * High DMA channel support & info by Hannu Savolainen
  5. * and John Boyd, Nov. 1992.
  6. * (c) Copyright 2000, Grant Grundler
  7. */
  8. #ifndef _ASM_DMA_H
  9. #define _ASM_DMA_H
  10. #include <asm/io.h> /* need byte IO */
  11. #define dma_outb outb
  12. #define dma_inb inb
  13. /*
  14. ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
  15. ** (or rather not merge) DMAs into manageable chunks.
  16. ** On parisc, this is more of the software/tuning constraint
  17. ** rather than the HW. I/O MMU allocation algorithms can be
  18. ** faster with smaller sizes (to some degree).
  19. */
  20. #define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE)
  21. /* The maximum address that we can perform a DMA transfer to on this platform
  22. ** New dynamic DMA interfaces should obsolete this....
  23. */
  24. #define MAX_DMA_ADDRESS (~0UL)
  25. /*
  26. ** We don't have DMA channels... well V-class does but the
  27. ** Dynamic DMA Mapping interface will support them... right? :^)
  28. ** Note: this is not relevant right now for PA-RISC, but we cannot
  29. ** leave this as undefined because some things (e.g. sound)
  30. ** won't compile :-(
  31. */
  32. #define MAX_DMA_CHANNELS 8
  33. #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
  34. #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
  35. #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
  36. #define DMA_AUTOINIT 0x10
  37. /* 8237 DMA controllers */
  38. #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
  39. #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
  40. /* DMA controller registers */
  41. #define DMA1_CMD_REG 0x08 /* command register (w) */
  42. #define DMA1_STAT_REG 0x08 /* status register (r) */
  43. #define DMA1_REQ_REG 0x09 /* request register (w) */
  44. #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
  45. #define DMA1_MODE_REG 0x0B /* mode register (w) */
  46. #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
  47. #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
  48. #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
  49. #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
  50. #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
  51. #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
  52. #define DMA2_CMD_REG 0xD0 /* command register (w) */
  53. #define DMA2_STAT_REG 0xD0 /* status register (r) */
  54. #define DMA2_REQ_REG 0xD2 /* request register (w) */
  55. #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
  56. #define DMA2_MODE_REG 0xD6 /* mode register (w) */
  57. #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
  58. #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
  59. #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
  60. #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
  61. #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
  62. #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
  63. static __inline__ unsigned long claim_dma_lock(void)
  64. {
  65. return 0;
  66. }
  67. static __inline__ void release_dma_lock(unsigned long flags)
  68. {
  69. }
  70. /* Get DMA residue count. After a DMA transfer, this
  71. * should return zero. Reading this while a DMA transfer is
  72. * still in progress will return unpredictable results.
  73. * If called before the channel has been used, it may return 1.
  74. * Otherwise, it returns the number of _bytes_ left to transfer.
  75. *
  76. * Assumes DMA flip-flop is clear.
  77. */
  78. static __inline__ int get_dma_residue(unsigned int dmanr)
  79. {
  80. unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
  81. : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
  82. /* using short to get 16-bit wrap around */
  83. unsigned short count;
  84. count = 1 + dma_inb(io_port);
  85. count += dma_inb(io_port) << 8;
  86. return (dmanr<=3)? count : (count<<1);
  87. }
  88. /* enable/disable a specific DMA channel */
  89. static __inline__ void enable_dma(unsigned int dmanr)
  90. {
  91. #ifdef CONFIG_SUPERIO
  92. if (dmanr<=3)
  93. dma_outb(dmanr, DMA1_MASK_REG);
  94. else
  95. dma_outb(dmanr & 3, DMA2_MASK_REG);
  96. #endif
  97. }
  98. static __inline__ void disable_dma(unsigned int dmanr)
  99. {
  100. #ifdef CONFIG_SUPERIO
  101. if (dmanr<=3)
  102. dma_outb(dmanr | 4, DMA1_MASK_REG);
  103. else
  104. dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
  105. #endif
  106. }
  107. /* reserve a DMA channel */
  108. #define request_dma(dmanr, device_id) (0)
  109. /* Clear the 'DMA Pointer Flip Flop'.
  110. * Write 0 for LSB/MSB, 1 for MSB/LSB access.
  111. * Use this once to initialize the FF to a known state.
  112. * After that, keep track of it. :-)
  113. * --- In order to do that, the DMA routines below should ---
  114. * --- only be used while holding the DMA lock ! ---
  115. */
  116. static __inline__ void clear_dma_ff(unsigned int dmanr)
  117. {
  118. }
  119. /* set mode (above) for a specific DMA channel */
  120. static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
  121. {
  122. }
  123. /* Set only the page register bits of the transfer address.
  124. * This is used for successive transfers when we know the contents of
  125. * the lower 16 bits of the DMA current address register, but a 64k boundary
  126. * may have been crossed.
  127. */
  128. static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
  129. {
  130. }
  131. /* Set transfer address & page bits for specific DMA channel.
  132. * Assumes dma flipflop is clear.
  133. */
  134. static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
  135. {
  136. }
  137. /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
  138. * a specific DMA channel.
  139. * You must ensure the parameters are valid.
  140. * NOTE: from a manual: "the number of transfers is one more
  141. * than the initial word count"! This is taken into account.
  142. * Assumes dma flip-flop is clear.
  143. * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
  144. */
  145. static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
  146. {
  147. }
  148. #define free_dma(dmanr)
  149. #ifdef CONFIG_PCI
  150. extern int isa_dma_bridge_buggy;
  151. #else
  152. #define isa_dma_bridge_buggy (0)
  153. #endif
  154. #endif /* _ASM_DMA_H */