3c120_devboard.dts 4.1 KB

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  1. /*
  2. * Copyright (C) 2013 Altera Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  16. *
  17. * This file is generated by sopc2dts.
  18. */
  19. /dts-v1/;
  20. / {
  21. model = "altr,qsys_ghrd_3c120";
  22. compatible = "altr,qsys_ghrd_3c120";
  23. #address-cells = <1>;
  24. #size-cells = <1>;
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. cpu: cpu@0 {
  29. device_type = "cpu";
  30. compatible = "altr,nios2-1.0";
  31. reg = <0x00000000>;
  32. interrupt-controller;
  33. #interrupt-cells = <1>;
  34. clock-frequency = <125000000>;
  35. dcache-line-size = <32>;
  36. icache-line-size = <32>;
  37. dcache-size = <32768>;
  38. icache-size = <32768>;
  39. altr,implementation = "fast";
  40. altr,pid-num-bits = <8>;
  41. altr,tlb-num-ways = <16>;
  42. altr,tlb-num-entries = <128>;
  43. altr,tlb-ptr-sz = <7>;
  44. altr,has-div = <1>;
  45. altr,has-mul = <1>;
  46. altr,reset-addr = <0xc2800000>;
  47. altr,fast-tlb-miss-addr = <0xc7fff400>;
  48. altr,exception-addr = <0xd0000020>;
  49. altr,has-initda = <1>;
  50. altr,has-mmu = <1>;
  51. };
  52. };
  53. memory@0 {
  54. device_type = "memory";
  55. reg = <0x10000000 0x08000000>,
  56. <0x07fff400 0x00000400>;
  57. };
  58. sopc@0 {
  59. device_type = "soc";
  60. ranges;
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. compatible = "altr,avalon", "simple-bus";
  64. bus-frequency = <125000000>;
  65. pb_cpu_to_io: bridge@8000000 {
  66. compatible = "simple-bus";
  67. reg = <0x08000000 0x00800000>;
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. ranges = <0x00002000 0x08002000 0x00002000>,
  71. <0x00004000 0x08004000 0x00000400>,
  72. <0x00004400 0x08004400 0x00000040>,
  73. <0x00004800 0x08004800 0x00000040>,
  74. <0x00004c80 0x08004c80 0x00000020>,
  75. <0x00004d50 0x08004d50 0x00000008>,
  76. <0x00008000 0x08008000 0x00000020>,
  77. <0x00400000 0x08400000 0x00000020>;
  78. timer_1ms: timer@400000 {
  79. compatible = "altr,timer-1.0";
  80. reg = <0x00400000 0x00000020>;
  81. interrupt-parent = <&cpu>;
  82. interrupts = <11>;
  83. clock-frequency = <125000000>;
  84. };
  85. timer_0: timer@8000 {
  86. compatible = "altr,timer-1.0";
  87. reg = < 0x00008000 0x00000020 >;
  88. interrupt-parent = < &cpu >;
  89. interrupts = < 5 >;
  90. clock-frequency = < 125000000 >;
  91. };
  92. jtag_uart: serial@4d50 {
  93. compatible = "altr,juart-1.0";
  94. reg = <0x00004d50 0x00000008>;
  95. interrupt-parent = <&cpu>;
  96. interrupts = <1>;
  97. };
  98. tse_mac: ethernet@4000 {
  99. compatible = "altr,tse-1.0";
  100. reg = <0x00004000 0x00000400>,
  101. <0x00004400 0x00000040>,
  102. <0x00004800 0x00000040>,
  103. <0x00002000 0x00002000>;
  104. reg-names = "control_port", "rx_csr", "tx_csr", "s1";
  105. interrupt-parent = <&cpu>;
  106. interrupts = <2 3>;
  107. interrupt-names = "rx_irq", "tx_irq";
  108. rx-fifo-depth = <8192>;
  109. tx-fifo-depth = <8192>;
  110. max-frame-size = <1518>;
  111. local-mac-address = [ 00 00 00 00 00 00 ];
  112. phy-mode = "rgmii-id";
  113. phy-handle = <&phy0>;
  114. tse_mac_mdio: mdio {
  115. compatible = "altr,tse-mdio";
  116. #address-cells = <1>;
  117. #size-cells = <0>;
  118. phy0: ethernet-phy@18 {
  119. reg = <18>;
  120. device_type = "ethernet-phy";
  121. };
  122. };
  123. };
  124. uart: serial@4c80 {
  125. compatible = "altr,uart-1.0";
  126. reg = <0x00004c80 0x00000020>;
  127. interrupt-parent = <&cpu>;
  128. interrupts = <10>;
  129. current-speed = <115200>;
  130. clock-frequency = <62500000>;
  131. };
  132. };
  133. cfi_flash_64m: flash@0 {
  134. compatible = "cfi-flash";
  135. reg = <0x00000000 0x04000000>;
  136. bank-width = <2>;
  137. device-width = <1>;
  138. #address-cells = <1>;
  139. #size-cells = <1>;
  140. partition@800000 {
  141. reg = <0x00800000 0x01e00000>;
  142. label = "JFFS2 Filesystem";
  143. };
  144. };
  145. };
  146. chosen {
  147. bootargs = "debug earlycon console=ttyJ0,115200";
  148. stdout-path = &jtag_uart;
  149. };
  150. };