txx9tmr.h 1.6 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768
  1. /*
  2. * include/asm-mips/txx9tmr.h
  3. * TX39/TX49 timer controller definitions.
  4. *
  5. * This file is subject to the terms and conditions of the GNU General Public
  6. * License. See the file "COPYING" in the main directory of this archive
  7. * for more details.
  8. */
  9. #ifndef __ASM_TXX9TMR_H
  10. #define __ASM_TXX9TMR_H
  11. #include <linux/types.h>
  12. struct txx9_tmr_reg {
  13. u32 tcr;
  14. u32 tisr;
  15. u32 cpra;
  16. u32 cprb;
  17. u32 itmr;
  18. u32 unused0[3];
  19. u32 ccdr;
  20. u32 unused1[3];
  21. u32 pgmr;
  22. u32 unused2[3];
  23. u32 wtmr;
  24. u32 unused3[43];
  25. u32 trr;
  26. };
  27. /* TMTCR : Timer Control */
  28. #define TXx9_TMTCR_TCE 0x00000080
  29. #define TXx9_TMTCR_CCDE 0x00000040
  30. #define TXx9_TMTCR_CRE 0x00000020
  31. #define TXx9_TMTCR_ECES 0x00000008
  32. #define TXx9_TMTCR_CCS 0x00000004
  33. #define TXx9_TMTCR_TMODE_MASK 0x00000003
  34. #define TXx9_TMTCR_TMODE_ITVL 0x00000000
  35. #define TXx9_TMTCR_TMODE_PGEN 0x00000001
  36. #define TXx9_TMTCR_TMODE_WDOG 0x00000002
  37. /* TMTISR : Timer Int. Status */
  38. #define TXx9_TMTISR_TPIBS 0x00000004
  39. #define TXx9_TMTISR_TPIAS 0x00000002
  40. #define TXx9_TMTISR_TIIS 0x00000001
  41. /* TMITMR : Interval Timer Mode */
  42. #define TXx9_TMITMR_TIIE 0x00008000
  43. #define TXx9_TMITMR_TZCE 0x00000001
  44. /* TMWTMR : Watchdog Timer Mode */
  45. #define TXx9_TMWTMR_TWIE 0x00008000
  46. #define TXx9_TMWTMR_WDIS 0x00000080
  47. #define TXx9_TMWTMR_TWC 0x00000001
  48. void txx9_clocksource_init(unsigned long baseaddr,
  49. unsigned int imbusclk);
  50. void txx9_clockevent_init(unsigned long baseaddr, int irq,
  51. unsigned int imbusclk);
  52. void txx9_tmr_init(unsigned long baseaddr);
  53. #ifdef CONFIG_CPU_TX39XX
  54. #define TXX9_TIMER_BITS 24
  55. #else
  56. #define TXX9_TIMER_BITS 32
  57. #endif
  58. #endif /* __ASM_TXX9TMR_H */