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maltaint.h

maltaint.h 1.7 KB
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  1. /*
    2. 

  2.  * This file is subject to the terms and conditions of the GNU General Public
    3. 

  3.  * License.  See the file "COPYING" in the main directory of this archive
    4. 

  4.  * for more details.
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
    7. 

  7.  *	Carsten Langgaard <carstenl@mips.com>
    8. 

  8.  *	Steven J. Hill <sjhill@mips.com>
    9. 

  9.  */
    10. 

  10. #ifndef _MIPS_MALTAINT_H
    11. 

  11. #define _MIPS_MALTAINT_H
    12. 

  12. 

  13. /*
    14. 

  14.  * Interrupts 0..15 are used for Malta ISA compatible interrupts
    15. 

  15.  */
    16. 

  16. #define MALTA_INT_BASE		0
    17. 

  17. 

  18. /* CPU interrupt offsets */
    19. 

  19. #define MIPSCPU_INT_SW0		0
    20. 

  20. #define MIPSCPU_INT_SW1		1
    21. 

  21. #define MIPSCPU_INT_MB0		2
    22. 

  22. #define MIPSCPU_INT_I8259A	MIPSCPU_INT_MB0
    23. 

  23. #define MIPSCPU_INT_GIC		MIPSCPU_INT_MB0 /* GIC chained interrupt */
    24. 

  24. #define MIPSCPU_INT_MB1		3
    25. 

  25. #define MIPSCPU_INT_SMI		MIPSCPU_INT_MB1
    26. 

  26. #define MIPSCPU_INT_MB2		4
    27. 

  27. #define MIPSCPU_INT_MB3		5
    28. 

  28. #define MIPSCPU_INT_COREHI	MIPSCPU_INT_MB3
    29. 

  29. #define MIPSCPU_INT_MB4		6
    30. 

  30. #define MIPSCPU_INT_CORELO	MIPSCPU_INT_MB4
    31. 

  31. 

  32. /*
    33. 

  33.  * Interrupts 96..127 are used for Soc-it Classic interrupts
    34. 

  34.  */
    35. 

  35. #define MSC01C_INT_BASE		96
    36. 

  36. 

  37. /* SOC-it Classic interrupt offsets */
    38. 

  38. #define MSC01C_INT_TMR		0
    39. 

  39. #define MSC01C_INT_PCI		1
    40. 

  40. 

  41. /*
    42. 

  42.  * Interrupts 96..127 are used for Soc-it EIC interrupts
    43. 

  43.  */
    44. 

  44. #define MSC01E_INT_BASE		96
    45. 

  45. 

  46. /* SOC-it EIC interrupt offsets */
    47. 

  47. #define MSC01E_INT_SW0		1
    48. 

  48. #define MSC01E_INT_SW1		2
    49. 

  49. #define MSC01E_INT_MB0		3
    50. 

  50. #define MSC01E_INT_I8259A	MSC01E_INT_MB0
    51. 

  51. #define MSC01E_INT_MB1		4
    52. 

  52. #define MSC01E_INT_SMI		MSC01E_INT_MB1
    53. 

  53. #define MSC01E_INT_MB2		5
    54. 

  54. #define MSC01E_INT_MB3		6
    55. 

  55. #define MSC01E_INT_COREHI	MSC01E_INT_MB3
    56. 

  56. #define MSC01E_INT_MB4		7
    57. 

  57. #define MSC01E_INT_CORELO	MSC01E_INT_MB4
    58. 

  58. #define MSC01E_INT_TMR		8
    59. 

  59. #define MSC01E_INT_PCI		9
    60. 

  60. #define MSC01E_INT_PERFCTR	10
    61. 

  61. #define MSC01E_INT_CPUCTR	11
    62. 

  62. 

  63. #endif /* !(_MIPS_MALTAINT_H) */
    64. 

  64.