macints.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Macintosh interrupts
  4. *
  5. * General design:
  6. * In contrary to the Amiga and Atari platforms, the Mac hardware seems to
  7. * exclusively use the autovector interrupts (the 'generic level0-level7'
  8. * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
  9. * are used:
  10. * 1 - VIA1
  11. * - slot 0: one second interrupt (CA2)
  12. * - slot 1: VBlank (CA1)
  13. * - slot 2: ADB data ready (SR full)
  14. * - slot 3: ADB data (CB2)
  15. * - slot 4: ADB clock (CB1)
  16. * - slot 5: timer 2
  17. * - slot 6: timer 1
  18. * - slot 7: status of IRQ; signals 'any enabled int.'
  19. *
  20. * 2 - VIA2 or RBV
  21. * - slot 0: SCSI DRQ (CA2)
  22. * - slot 1: NUBUS IRQ (CA1) need to read port A to find which
  23. * - slot 2: /EXP IRQ (only on IIci)
  24. * - slot 3: SCSI IRQ (CB2)
  25. * - slot 4: ASC IRQ (CB1)
  26. * - slot 5: timer 2 (not on IIci)
  27. * - slot 6: timer 1 (not on IIci)
  28. * - slot 7: status of IRQ; signals 'any enabled int.'
  29. *
  30. * Levels 3-6 vary by machine type. For VIA or RBV Macintoshes:
  31. *
  32. * 3 - unused (?)
  33. *
  34. * 4 - SCC
  35. *
  36. * 5 - unused (?)
  37. * [serial errors or special conditions seem to raise level 6
  38. * interrupts on some models (LC4xx?)]
  39. *
  40. * 6 - off switch (?)
  41. *
  42. * Machines with Quadra-like VIA hardware, except PSC and PMU machines, support
  43. * an alternate interrupt mapping, as used by A/UX. It spreads ethernet and
  44. * sound out to their own autovector IRQs and gives VIA1 a higher priority:
  45. *
  46. * 1 - unused (?)
  47. *
  48. * 3 - on-board SONIC
  49. *
  50. * 5 - Apple Sound Chip (ASC)
  51. *
  52. * 6 - VIA1
  53. *
  54. * For OSS Macintoshes (IIfx only), we apply an interrupt mapping similar to
  55. * the Quadra (A/UX) mapping:
  56. *
  57. * 1 - ISM IOP (ADB)
  58. *
  59. * 2 - SCSI
  60. *
  61. * 3 - NuBus
  62. *
  63. * 4 - SCC IOP
  64. *
  65. * 6 - VIA1
  66. *
  67. * For PSC Macintoshes (660AV, 840AV):
  68. *
  69. * 3 - PSC level 3
  70. * - slot 0: MACE
  71. *
  72. * 4 - PSC level 4
  73. * - slot 1: SCC channel A interrupt
  74. * - slot 2: SCC channel B interrupt
  75. * - slot 3: MACE DMA
  76. *
  77. * 5 - PSC level 5
  78. *
  79. * 6 - PSC level 6
  80. *
  81. * Finally we have good 'ole level 7, the non-maskable interrupt:
  82. *
  83. * 7 - NMI (programmer's switch on the back of some Macs)
  84. * Also RAM parity error on models which support it (IIc, IIfx?)
  85. *
  86. * The current interrupt logic looks something like this:
  87. *
  88. * - We install dispatchers for the autovector interrupts (1-7). These
  89. * dispatchers are responsible for querying the hardware (the
  90. * VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using
  91. * this information a machspec interrupt number is generated by placing the
  92. * index of the interrupt hardware into the low three bits and the original
  93. * autovector interrupt number in the upper 5 bits. The handlers for the
  94. * resulting machspec interrupt are then called.
  95. *
  96. * - Nubus is a special case because its interrupts are hidden behind two
  97. * layers of hardware. Nubus interrupts come in as index 1 on VIA #2,
  98. * which translates to IRQ number 17. In this spot we install _another_
  99. * dispatcher. This dispatcher finds the interrupting slot number (9-F) and
  100. * then forms a new machspec interrupt number as above with the slot number
  101. * minus 9 in the low three bits and the pseudo-level 7 in the upper five
  102. * bits. The handlers for this new machspec interrupt number are then
  103. * called. This puts Nubus interrupts into the range 56-62.
  104. *
  105. * - The Baboon interrupts (used on some PowerBooks) are an even more special
  106. * case. They're hidden behind the Nubus slot $C interrupt thus adding a
  107. * third layer of indirection. Why oh why did the Apple engineers do that?
  108. *
  109. */
  110. #include <linux/types.h>
  111. #include <linux/kernel.h>
  112. #include <linux/sched.h>
  113. #include <linux/sched/debug.h>
  114. #include <linux/interrupt.h>
  115. #include <linux/irq.h>
  116. #include <linux/delay.h>
  117. #include <asm/irq.h>
  118. #include <asm/macintosh.h>
  119. #include <asm/macints.h>
  120. #include <asm/mac_via.h>
  121. #include <asm/mac_psc.h>
  122. #include <asm/mac_oss.h>
  123. #include <asm/mac_iop.h>
  124. #include <asm/mac_baboon.h>
  125. #include <asm/hwtest.h>
  126. #include <asm/irq_regs.h>
  127. extern void show_registers(struct pt_regs *);
  128. irqreturn_t mac_nmi_handler(int, void *);
  129. static unsigned int mac_irq_startup(struct irq_data *);
  130. static void mac_irq_shutdown(struct irq_data *);
  131. static struct irq_chip mac_irq_chip = {
  132. .name = "mac",
  133. .irq_enable = mac_irq_enable,
  134. .irq_disable = mac_irq_disable,
  135. .irq_startup = mac_irq_startup,
  136. .irq_shutdown = mac_irq_shutdown,
  137. };
  138. void __init mac_init_IRQ(void)
  139. {
  140. m68k_setup_irq_controller(&mac_irq_chip, handle_simple_irq, IRQ_USER,
  141. NUM_MAC_SOURCES - IRQ_USER);
  142. /*
  143. * Now register the handlers for the master IRQ handlers
  144. * at levels 1-7. Most of the work is done elsewhere.
  145. */
  146. if (oss_present)
  147. oss_register_interrupts();
  148. else
  149. via_register_interrupts();
  150. if (psc)
  151. psc_register_interrupts();
  152. if (baboon_present)
  153. baboon_register_interrupts();
  154. iop_register_interrupts();
  155. if (request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI",
  156. mac_nmi_handler))
  157. pr_err("Couldn't register NMI\n");
  158. }
  159. /*
  160. * mac_irq_enable - enable an interrupt source
  161. * mac_irq_disable - disable an interrupt source
  162. *
  163. * These routines are just dispatchers to the VIA/OSS/PSC routines.
  164. */
  165. void mac_irq_enable(struct irq_data *data)
  166. {
  167. int irq = data->irq;
  168. int irq_src = IRQ_SRC(irq);
  169. switch(irq_src) {
  170. case 1:
  171. case 2:
  172. case 7:
  173. if (oss_present)
  174. oss_irq_enable(irq);
  175. else
  176. via_irq_enable(irq);
  177. break;
  178. case 3:
  179. case 4:
  180. case 5:
  181. case 6:
  182. if (psc)
  183. psc_irq_enable(irq);
  184. else if (oss_present)
  185. oss_irq_enable(irq);
  186. break;
  187. case 8:
  188. if (baboon_present)
  189. baboon_irq_enable(irq);
  190. break;
  191. }
  192. }
  193. void mac_irq_disable(struct irq_data *data)
  194. {
  195. int irq = data->irq;
  196. int irq_src = IRQ_SRC(irq);
  197. switch(irq_src) {
  198. case 1:
  199. case 2:
  200. case 7:
  201. if (oss_present)
  202. oss_irq_disable(irq);
  203. else
  204. via_irq_disable(irq);
  205. break;
  206. case 3:
  207. case 4:
  208. case 5:
  209. case 6:
  210. if (psc)
  211. psc_irq_disable(irq);
  212. else if (oss_present)
  213. oss_irq_disable(irq);
  214. break;
  215. case 8:
  216. if (baboon_present)
  217. baboon_irq_disable(irq);
  218. break;
  219. }
  220. }
  221. static unsigned int mac_irq_startup(struct irq_data *data)
  222. {
  223. int irq = data->irq;
  224. if (IRQ_SRC(irq) == 7 && !oss_present)
  225. via_nubus_irq_startup(irq);
  226. else
  227. mac_irq_enable(data);
  228. return 0;
  229. }
  230. static void mac_irq_shutdown(struct irq_data *data)
  231. {
  232. int irq = data->irq;
  233. if (IRQ_SRC(irq) == 7 && !oss_present)
  234. via_nubus_irq_shutdown(irq);
  235. else
  236. mac_irq_disable(data);
  237. }
  238. static volatile int in_nmi;
  239. irqreturn_t mac_nmi_handler(int irq, void *dev_id)
  240. {
  241. if (in_nmi)
  242. return IRQ_HANDLED;
  243. in_nmi = 1;
  244. pr_info("Non-Maskable Interrupt\n");
  245. show_registers(get_irq_regs());
  246. in_nmi = 0;
  247. return IRQ_HANDLED;
  248. }