m523x.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106
  1. // SPDX-License-Identifier: GPL-2.0
  2. /***************************************************************************/
  3. /*
  4. * m523x.c -- platform support for ColdFire 523x based boards
  5. *
  6. * Sub-architcture dependent initialization code for the Freescale
  7. * 523x CPUs.
  8. *
  9. * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
  10. * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
  11. */
  12. /***************************************************************************/
  13. #include <linux/kernel.h>
  14. #include <linux/param.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <asm/machdep.h>
  18. #include <asm/coldfire.h>
  19. #include <asm/mcfsim.h>
  20. #include <asm/mcfclk.h>
  21. /***************************************************************************/
  22. DEFINE_CLK(pll, "pll.0", MCF_CLK);
  23. DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  24. DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
  25. DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
  26. DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
  27. DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
  28. DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  29. DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  30. DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
  31. DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
  32. DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
  33. DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
  34. struct clk *mcf_clks[] = {
  35. &clk_pll,
  36. &clk_sys,
  37. &clk_mcfpit0,
  38. &clk_mcfpit1,
  39. &clk_mcfpit2,
  40. &clk_mcfpit3,
  41. &clk_mcfuart0,
  42. &clk_mcfuart1,
  43. &clk_mcfuart2,
  44. &clk_mcfqspi0,
  45. &clk_fec0,
  46. &clk_mcfi2c0,
  47. NULL
  48. };
  49. /***************************************************************************/
  50. static void __init m523x_qspi_init(void)
  51. {
  52. #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  53. u16 par;
  54. /* setup QSPS pins for QSPI with gpio CS control */
  55. writeb(0x1f, MCFGPIO_PAR_QSPI);
  56. /* and CS2 & CS3 as gpio */
  57. par = readw(MCFGPIO_PAR_TIMER);
  58. par &= 0x3f3f;
  59. writew(par, MCFGPIO_PAR_TIMER);
  60. #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  61. }
  62. /***************************************************************************/
  63. static void __init m523x_i2c_init(void)
  64. {
  65. #if IS_ENABLED(CONFIG_I2C_IMX)
  66. u8 par;
  67. /* setup Port AS Pin Assignment Register for I2C */
  68. /* set PASPA0 to SCL and PASPA1 to SDA */
  69. par = readb(MCFGPIO_PAR_FECI2C);
  70. par |= 0x0f;
  71. writeb(par, MCFGPIO_PAR_FECI2C);
  72. #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
  73. }
  74. /***************************************************************************/
  75. static void __init m523x_fec_init(void)
  76. {
  77. /* Set multi-function pins to ethernet use */
  78. writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
  79. }
  80. /***************************************************************************/
  81. void __init config_BSP(char *commandp, int size)
  82. {
  83. mach_sched_init = hw_timer_init;
  84. m523x_fec_init();
  85. m523x_qspi_init();
  86. m523x_i2c_init();
  87. }
  88. /***************************************************************************/