perfmon_mckinley.h 9.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * This file contains the McKinley PMU register description tables
  4. * and pmc checker used by perfmon.c.
  5. *
  6. * Copyright (C) 2002-2003 Hewlett Packard Co
  7. * Stephane Eranian <eranian@hpl.hp.com>
  8. */
  9. static int pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
  10. static pfm_reg_desc_t pfm_mck_pmc_desc[PMU_MAX_PMCS]={
  11. /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  12. /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  13. /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  14. /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  15. /* pmc4 */ { PFM_REG_COUNTING, 6, 0x0000000000800000UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  16. /* pmc5 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  17. /* pmc6 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  18. /* pmc7 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  19. /* pmc8 */ { PFM_REG_CONFIG , 0, 0xffffffff3fffffffUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  20. /* pmc9 */ { PFM_REG_CONFIG , 0, 0xffffffff3ffffffcUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  21. /* pmc10 */ { PFM_REG_MONITOR , 4, 0x0UL, 0xffffUL, NULL, pfm_mck_pmc_check, {RDEP(0)|RDEP(1),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  22. /* pmc11 */ { PFM_REG_MONITOR , 6, 0x0UL, 0x30f01cf, NULL, pfm_mck_pmc_check, {RDEP(2)|RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  23. /* pmc12 */ { PFM_REG_MONITOR , 6, 0x0UL, 0xffffUL, NULL, pfm_mck_pmc_check, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  24. /* pmc13 */ { PFM_REG_CONFIG , 0, 0x00002078fefefefeUL, 0x1e00018181818UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  25. /* pmc14 */ { PFM_REG_CONFIG , 0, 0x0db60db60db60db6UL, 0x2492UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  26. /* pmc15 */ { PFM_REG_CONFIG , 0, 0x00000000fffffff0UL, 0xfUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
  27. { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
  28. };
  29. static pfm_reg_desc_t pfm_mck_pmd_desc[PMU_MAX_PMDS]={
  30. /* pmd0 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(1),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
  31. /* pmd1 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(0),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
  32. /* pmd2 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
  33. /* pmd3 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
  34. /* pmd4 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}},
  35. /* pmd5 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}},
  36. /* pmd6 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(6),0UL, 0UL, 0UL}},
  37. /* pmd7 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(7),0UL, 0UL, 0UL}},
  38. /* pmd8 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  39. /* pmd9 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  40. /* pmd10 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  41. /* pmd11 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  42. /* pmd12 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  43. /* pmd13 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  44. /* pmd14 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  45. /* pmd15 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  46. /* pmd16 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
  47. /* pmd17 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(3),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
  48. { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
  49. };
  50. /*
  51. * PMC reserved fields must have their power-up values preserved
  52. */
  53. static int
  54. pfm_mck_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs)
  55. {
  56. unsigned long tmp1, tmp2, ival = *val;
  57. /* remove reserved areas from user value */
  58. tmp1 = ival & PMC_RSVD_MASK(cnum);
  59. /* get reserved fields values */
  60. tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum);
  61. *val = tmp1 | tmp2;
  62. DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
  63. cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val));
  64. return 0;
  65. }
  66. /*
  67. * task can be NULL if the context is unloaded
  68. */
  69. static int
  70. pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
  71. {
  72. int ret = 0, check_case1 = 0;
  73. unsigned long val8 = 0, val14 = 0, val13 = 0;
  74. int is_loaded;
  75. /* first preserve the reserved fields */
  76. pfm_mck_reserved(cnum, val, regs);
  77. /* sanitfy check */
  78. if (ctx == NULL) return -EINVAL;
  79. is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED;
  80. /*
  81. * we must clear the debug registers if pmc13 has a value which enable
  82. * memory pipeline event constraints. In this case we need to clear the
  83. * the debug registers if they have not yet been accessed. This is required
  84. * to avoid picking stale state.
  85. * PMC13 is "active" if:
  86. * one of the pmc13.cfg_dbrpXX field is different from 0x3
  87. * AND
  88. * at the corresponding pmc13.ena_dbrpXX is set.
  89. */
  90. DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, *val, ctx->ctx_fl_using_dbreg, is_loaded));
  91. if (cnum == 13 && is_loaded
  92. && (*val & 0x1e00000000000UL) && (*val & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) {
  93. DPRINT(("pmc[%d]=0x%lx has active pmc13 settings, clearing dbr\n", cnum, *val));
  94. /* don't mix debug with perfmon */
  95. if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
  96. /*
  97. * a count of 0 will mark the debug registers as in use and also
  98. * ensure that they are properly cleared.
  99. */
  100. ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs);
  101. if (ret) return ret;
  102. }
  103. /*
  104. * we must clear the (instruction) debug registers if any pmc14.ibrpX bit is enabled
  105. * before they are (fl_using_dbreg==0) to avoid picking up stale information.
  106. */
  107. if (cnum == 14 && is_loaded && ((*val & 0x2222UL) != 0x2222UL) && ctx->ctx_fl_using_dbreg == 0) {
  108. DPRINT(("pmc[%d]=0x%lx has active pmc14 settings, clearing ibr\n", cnum, *val));
  109. /* don't mix debug with perfmon */
  110. if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
  111. /*
  112. * a count of 0 will mark the debug registers as in use and also
  113. * ensure that they are properly cleared.
  114. */
  115. ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs);
  116. if (ret) return ret;
  117. }
  118. switch(cnum) {
  119. case 4: *val |= 1UL << 23; /* force power enable bit */
  120. break;
  121. case 8: val8 = *val;
  122. val13 = ctx->ctx_pmcs[13];
  123. val14 = ctx->ctx_pmcs[14];
  124. check_case1 = 1;
  125. break;
  126. case 13: val8 = ctx->ctx_pmcs[8];
  127. val13 = *val;
  128. val14 = ctx->ctx_pmcs[14];
  129. check_case1 = 1;
  130. break;
  131. case 14: val8 = ctx->ctx_pmcs[8];
  132. val13 = ctx->ctx_pmcs[13];
  133. val14 = *val;
  134. check_case1 = 1;
  135. break;
  136. }
  137. /* check illegal configuration which can produce inconsistencies in tagging
  138. * i-side events in L1D and L2 caches
  139. */
  140. if (check_case1) {
  141. ret = ((val13 >> 45) & 0xf) == 0
  142. && ((val8 & 0x1) == 0)
  143. && ((((val14>>1) & 0x3) == 0x2 || ((val14>>1) & 0x3) == 0x0)
  144. ||(((val14>>4) & 0x3) == 0x2 || ((val14>>4) & 0x3) == 0x0));
  145. if (ret) DPRINT((KERN_DEBUG "perfmon: failure check_case1\n"));
  146. }
  147. return ret ? -EINVAL : 0;
  148. }
  149. /*
  150. * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
  151. */
  152. static pmu_config_t pmu_conf_mck={
  153. .pmu_name = "Itanium 2",
  154. .pmu_family = 0x1f,
  155. .flags = PFM_PMU_IRQ_RESEND,
  156. .ovfl_val = (1UL << 47) - 1,
  157. .pmd_desc = pfm_mck_pmd_desc,
  158. .pmc_desc = pfm_mck_pmc_desc,
  159. .num_ibrs = 8,
  160. .num_dbrs = 8,
  161. .use_rr_dbregs = 1 /* debug register are use for range restrictions */
  162. };