atomic.h 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _ASM_IA64_ATOMIC_H
  3. #define _ASM_IA64_ATOMIC_H
  4. /*
  5. * Atomic operations that C can't guarantee us. Useful for
  6. * resource counting etc..
  7. *
  8. * NOTE: don't mess with the types below! The "unsigned long" and
  9. * "int" types were carefully placed so as to ensure proper operation
  10. * of the macros.
  11. *
  12. * Copyright (C) 1998, 1999, 2002-2003 Hewlett-Packard Co
  13. * David Mosberger-Tang <davidm@hpl.hp.com>
  14. */
  15. #include <linux/types.h>
  16. #include <asm/intrinsics.h>
  17. #include <asm/barrier.h>
  18. #define ATOMIC_INIT(i) { (i) }
  19. #define ATOMIC64_INIT(i) { (i) }
  20. #define atomic_read(v) READ_ONCE((v)->counter)
  21. #define atomic64_read(v) READ_ONCE((v)->counter)
  22. #define atomic_set(v,i) WRITE_ONCE(((v)->counter), (i))
  23. #define atomic64_set(v,i) WRITE_ONCE(((v)->counter), (i))
  24. #define ATOMIC_OP(op, c_op) \
  25. static __inline__ int \
  26. ia64_atomic_##op (int i, atomic_t *v) \
  27. { \
  28. __s32 old, new; \
  29. CMPXCHG_BUGCHECK_DECL \
  30. \
  31. do { \
  32. CMPXCHG_BUGCHECK(v); \
  33. old = atomic_read(v); \
  34. new = old c_op i; \
  35. } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old); \
  36. return new; \
  37. }
  38. #define ATOMIC_FETCH_OP(op, c_op) \
  39. static __inline__ int \
  40. ia64_atomic_fetch_##op (int i, atomic_t *v) \
  41. { \
  42. __s32 old, new; \
  43. CMPXCHG_BUGCHECK_DECL \
  44. \
  45. do { \
  46. CMPXCHG_BUGCHECK(v); \
  47. old = atomic_read(v); \
  48. new = old c_op i; \
  49. } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old); \
  50. return old; \
  51. }
  52. #define ATOMIC_OPS(op, c_op) \
  53. ATOMIC_OP(op, c_op) \
  54. ATOMIC_FETCH_OP(op, c_op)
  55. ATOMIC_OPS(add, +)
  56. ATOMIC_OPS(sub, -)
  57. #ifdef __OPTIMIZE__
  58. #define __ia64_atomic_const(i) \
  59. static const int __ia64_atomic_p = __builtin_constant_p(i) ? \
  60. ((i) == 1 || (i) == 4 || (i) == 8 || (i) == 16 || \
  61. (i) == -1 || (i) == -4 || (i) == -8 || (i) == -16) : 0;\
  62. __ia64_atomic_p
  63. #else
  64. #define __ia64_atomic_const(i) 0
  65. #endif
  66. #define atomic_add_return(i,v) \
  67. ({ \
  68. int __ia64_aar_i = (i); \
  69. __ia64_atomic_const(i) \
  70. ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
  71. : ia64_atomic_add(__ia64_aar_i, v); \
  72. })
  73. #define atomic_sub_return(i,v) \
  74. ({ \
  75. int __ia64_asr_i = (i); \
  76. __ia64_atomic_const(i) \
  77. ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
  78. : ia64_atomic_sub(__ia64_asr_i, v); \
  79. })
  80. #define atomic_fetch_add(i,v) \
  81. ({ \
  82. int __ia64_aar_i = (i); \
  83. __ia64_atomic_const(i) \
  84. ? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \
  85. : ia64_atomic_fetch_add(__ia64_aar_i, v); \
  86. })
  87. #define atomic_fetch_sub(i,v) \
  88. ({ \
  89. int __ia64_asr_i = (i); \
  90. __ia64_atomic_const(i) \
  91. ? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \
  92. : ia64_atomic_fetch_sub(__ia64_asr_i, v); \
  93. })
  94. ATOMIC_FETCH_OP(and, &)
  95. ATOMIC_FETCH_OP(or, |)
  96. ATOMIC_FETCH_OP(xor, ^)
  97. #define atomic_and(i,v) (void)ia64_atomic_fetch_and(i,v)
  98. #define atomic_or(i,v) (void)ia64_atomic_fetch_or(i,v)
  99. #define atomic_xor(i,v) (void)ia64_atomic_fetch_xor(i,v)
  100. #define atomic_fetch_and(i,v) ia64_atomic_fetch_and(i,v)
  101. #define atomic_fetch_or(i,v) ia64_atomic_fetch_or(i,v)
  102. #define atomic_fetch_xor(i,v) ia64_atomic_fetch_xor(i,v)
  103. #undef ATOMIC_OPS
  104. #undef ATOMIC_FETCH_OP
  105. #undef ATOMIC_OP
  106. #define ATOMIC64_OP(op, c_op) \
  107. static __inline__ long \
  108. ia64_atomic64_##op (__s64 i, atomic64_t *v) \
  109. { \
  110. __s64 old, new; \
  111. CMPXCHG_BUGCHECK_DECL \
  112. \
  113. do { \
  114. CMPXCHG_BUGCHECK(v); \
  115. old = atomic64_read(v); \
  116. new = old c_op i; \
  117. } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); \
  118. return new; \
  119. }
  120. #define ATOMIC64_FETCH_OP(op, c_op) \
  121. static __inline__ long \
  122. ia64_atomic64_fetch_##op (__s64 i, atomic64_t *v) \
  123. { \
  124. __s64 old, new; \
  125. CMPXCHG_BUGCHECK_DECL \
  126. \
  127. do { \
  128. CMPXCHG_BUGCHECK(v); \
  129. old = atomic64_read(v); \
  130. new = old c_op i; \
  131. } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); \
  132. return old; \
  133. }
  134. #define ATOMIC64_OPS(op, c_op) \
  135. ATOMIC64_OP(op, c_op) \
  136. ATOMIC64_FETCH_OP(op, c_op)
  137. ATOMIC64_OPS(add, +)
  138. ATOMIC64_OPS(sub, -)
  139. #define atomic64_add_return(i,v) \
  140. ({ \
  141. long __ia64_aar_i = (i); \
  142. __ia64_atomic_const(i) \
  143. ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
  144. : ia64_atomic64_add(__ia64_aar_i, v); \
  145. })
  146. #define atomic64_sub_return(i,v) \
  147. ({ \
  148. long __ia64_asr_i = (i); \
  149. __ia64_atomic_const(i) \
  150. ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
  151. : ia64_atomic64_sub(__ia64_asr_i, v); \
  152. })
  153. #define atomic64_fetch_add(i,v) \
  154. ({ \
  155. long __ia64_aar_i = (i); \
  156. __ia64_atomic_const(i) \
  157. ? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \
  158. : ia64_atomic64_fetch_add(__ia64_aar_i, v); \
  159. })
  160. #define atomic64_fetch_sub(i,v) \
  161. ({ \
  162. long __ia64_asr_i = (i); \
  163. __ia64_atomic_const(i) \
  164. ? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \
  165. : ia64_atomic64_fetch_sub(__ia64_asr_i, v); \
  166. })
  167. ATOMIC64_FETCH_OP(and, &)
  168. ATOMIC64_FETCH_OP(or, |)
  169. ATOMIC64_FETCH_OP(xor, ^)
  170. #define atomic64_and(i,v) (void)ia64_atomic64_fetch_and(i,v)
  171. #define atomic64_or(i,v) (void)ia64_atomic64_fetch_or(i,v)
  172. #define atomic64_xor(i,v) (void)ia64_atomic64_fetch_xor(i,v)
  173. #define atomic64_fetch_and(i,v) ia64_atomic64_fetch_and(i,v)
  174. #define atomic64_fetch_or(i,v) ia64_atomic64_fetch_or(i,v)
  175. #define atomic64_fetch_xor(i,v) ia64_atomic64_fetch_xor(i,v)
  176. #undef ATOMIC64_OPS
  177. #undef ATOMIC64_FETCH_OP
  178. #undef ATOMIC64_OP
  179. #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
  180. #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
  181. #define atomic64_cmpxchg(v, old, new) \
  182. (cmpxchg(&((v)->counter), old, new))
  183. #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
  184. #define atomic_add(i,v) (void)atomic_add_return((i), (v))
  185. #define atomic_sub(i,v) (void)atomic_sub_return((i), (v))
  186. #define atomic64_add(i,v) (void)atomic64_add_return((i), (v))
  187. #define atomic64_sub(i,v) (void)atomic64_sub_return((i), (v))
  188. #endif /* _ASM_IA64_ATOMIC_H */