zynqmp-zc1751-xm017-dc3.dts 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * dts file for Xilinx ZynqMP zc1751-xm017-dc3
  4. *
  5. * (C) Copyright 2016 - 2018, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk.dtsi"
  12. / {
  13. model = "ZynqMP zc1751-xm017-dc3 RevA";
  14. compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  15. aliases {
  16. ethernet0 = &gem0;
  17. i2c0 = &i2c0;
  18. i2c1 = &i2c1;
  19. mmc0 = &sdhci1;
  20. rtc0 = &rtc;
  21. serial0 = &uart0;
  22. serial1 = &uart1;
  23. };
  24. chosen {
  25. bootargs = "earlycon";
  26. stdout-path = "serial0:115200n8";
  27. };
  28. memory@0 {
  29. device_type = "memory";
  30. reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  31. };
  32. };
  33. &fpd_dma_chan1 {
  34. status = "okay";
  35. };
  36. &fpd_dma_chan2 {
  37. status = "okay";
  38. };
  39. &fpd_dma_chan3 {
  40. status = "okay";
  41. };
  42. &fpd_dma_chan4 {
  43. status = "okay";
  44. };
  45. &fpd_dma_chan5 {
  46. status = "okay";
  47. };
  48. &fpd_dma_chan6 {
  49. status = "okay";
  50. };
  51. &fpd_dma_chan7 {
  52. status = "okay";
  53. };
  54. &fpd_dma_chan8 {
  55. status = "okay";
  56. };
  57. &gem0 {
  58. status = "okay";
  59. phy-handle = <&phy0>;
  60. phy-mode = "rgmii-id";
  61. phy0: phy@0 { /* VSC8211 */
  62. reg = <0>;
  63. };
  64. };
  65. &gpio {
  66. status = "okay";
  67. };
  68. /* just eeprom here */
  69. &i2c0 {
  70. status = "okay";
  71. clock-frequency = <400000>;
  72. tca6416_u26: gpio@20 {
  73. compatible = "ti,tca6416";
  74. reg = <0x20>;
  75. gpio-controller;
  76. #gpio-cells = <2>;
  77. /* IRQ not connected */
  78. };
  79. rtc@68 {
  80. compatible = "dallas,ds1339";
  81. reg = <0x68>;
  82. };
  83. };
  84. /* eeprom24c02 and SE98A temp chip pca9306 */
  85. &i2c1 {
  86. status = "okay";
  87. clock-frequency = <400000>;
  88. };
  89. &rtc {
  90. status = "okay";
  91. };
  92. &sata {
  93. status = "okay";
  94. /* SATA phy OOB timing settings */
  95. ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
  96. ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
  97. ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  98. ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  99. ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
  100. ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
  101. ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  102. ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  103. };
  104. &sdhci1 { /* emmc with some settings */
  105. status = "okay";
  106. };
  107. /* main */
  108. &uart0 {
  109. status = "okay";
  110. };
  111. /* DB9 */
  112. &uart1 {
  113. status = "okay";
  114. };
  115. &usb0 {
  116. status = "okay";
  117. dr_mode = "host";
  118. };
  119. /* ULPI SMSC USB3320 */
  120. &usb1 {
  121. status = "okay";
  122. dr_mode = "host";
  123. };