zynqmp-zc1751-xm015-dc1.dts 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  4. *
  5. * (C) Copyright 2015 - 2018, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk.dtsi"
  12. #include <dt-bindings/gpio/gpio.h>
  13. / {
  14. model = "ZynqMP zc1751-xm015-dc1 RevA";
  15. compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  16. aliases {
  17. ethernet0 = &gem3;
  18. i2c0 = &i2c1;
  19. mmc0 = &sdhci0;
  20. mmc1 = &sdhci1;
  21. rtc0 = &rtc;
  22. serial0 = &uart0;
  23. };
  24. chosen {
  25. bootargs = "earlycon";
  26. stdout-path = "serial0:115200n8";
  27. };
  28. memory@0 {
  29. device_type = "memory";
  30. reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  31. };
  32. };
  33. &fpd_dma_chan1 {
  34. status = "okay";
  35. };
  36. &fpd_dma_chan2 {
  37. status = "okay";
  38. };
  39. &fpd_dma_chan3 {
  40. status = "okay";
  41. };
  42. &fpd_dma_chan4 {
  43. status = "okay";
  44. };
  45. &fpd_dma_chan5 {
  46. status = "okay";
  47. };
  48. &fpd_dma_chan6 {
  49. status = "okay";
  50. };
  51. &fpd_dma_chan7 {
  52. status = "okay";
  53. };
  54. &fpd_dma_chan8 {
  55. status = "okay";
  56. };
  57. &gem3 {
  58. status = "okay";
  59. phy-handle = <&phy0>;
  60. phy-mode = "rgmii-id";
  61. phy0: phy@0 {
  62. reg = <0>;
  63. };
  64. };
  65. &gpio {
  66. status = "okay";
  67. };
  68. &i2c1 {
  69. status = "okay";
  70. clock-frequency = <400000>;
  71. eeprom: eeprom@55 {
  72. compatible = "atmel,24c64"; /* 24AA64 */
  73. reg = <0x55>;
  74. };
  75. };
  76. &rtc {
  77. status = "okay";
  78. };
  79. &sata {
  80. status = "okay";
  81. /* SATA phy OOB timing settings */
  82. ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
  83. ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
  84. ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  85. ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  86. ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
  87. ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
  88. ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  89. ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  90. };
  91. /* eMMC */
  92. &sdhci0 {
  93. status = "okay";
  94. bus-width = <8>;
  95. };
  96. /* SD1 with level shifter */
  97. &sdhci1 {
  98. status = "okay";
  99. };
  100. &uart0 {
  101. status = "okay";
  102. };
  103. /* ULPI SMSC USB3320 */
  104. &usb0 {
  105. status = "okay";
  106. };