r8a77980-condor.dts 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the Condor board
  4. *
  5. * Copyright (C) 2018 Renesas Electronics Corp.
  6. * Copyright (C) 2018 Cogent Embedded, Inc.
  7. */
  8. /dts-v1/;
  9. #include "r8a77980.dtsi"
  10. / {
  11. model = "Renesas Condor board based on r8a77980";
  12. compatible = "renesas,condor", "renesas,r8a77980";
  13. aliases {
  14. serial0 = &scif0;
  15. ethernet0 = &gether;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory@48000000 {
  21. device_type = "memory";
  22. /* first 128MB is reserved for secure area. */
  23. reg = <0 0x48000000 0 0x78000000>;
  24. };
  25. d3_3v: regulator-0 {
  26. compatible = "regulator-fixed";
  27. regulator-name = "D3.3V";
  28. regulator-min-microvolt = <3300000>;
  29. regulator-max-microvolt = <3300000>;
  30. regulator-boot-on;
  31. regulator-always-on;
  32. };
  33. vddq_vin01: regulator-1 {
  34. compatible = "regulator-fixed";
  35. regulator-name = "VDDQ_VIN01";
  36. regulator-min-microvolt = <1800000>;
  37. regulator-max-microvolt = <1800000>;
  38. regulator-boot-on;
  39. regulator-always-on;
  40. };
  41. };
  42. &canfd {
  43. pinctrl-0 = <&canfd0_pins>;
  44. pinctrl-names = "default";
  45. status = "okay";
  46. channel0 {
  47. status = "okay";
  48. };
  49. };
  50. &extal_clk {
  51. clock-frequency = <16666666>;
  52. };
  53. &extalr_clk {
  54. clock-frequency = <32768>;
  55. };
  56. &gether {
  57. pinctrl-0 = <&gether_pins>;
  58. pinctrl-names = "default";
  59. phy-mode = "rgmii-id";
  60. phy-handle = <&phy0>;
  61. renesas,no-ether-link;
  62. status = "okay";
  63. phy0: ethernet-phy@0 {
  64. rxc-skew-ps = <1500>;
  65. reg = <0>;
  66. interrupt-parent = <&gpio4>;
  67. interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
  68. };
  69. };
  70. &i2c0 {
  71. pinctrl-0 = <&i2c0_pins>;
  72. pinctrl-names = "default";
  73. status = "okay";
  74. clock-frequency = <400000>;
  75. io_expander0: gpio@20 {
  76. compatible = "onnn,pca9654";
  77. reg = <0x20>;
  78. gpio-controller;
  79. #gpio-cells = <2>;
  80. };
  81. io_expander1: gpio@21 {
  82. compatible = "onnn,pca9654";
  83. reg = <0x21>;
  84. gpio-controller;
  85. #gpio-cells = <2>;
  86. };
  87. };
  88. &mmc0 {
  89. pinctrl-0 = <&mmc_pins>;
  90. pinctrl-1 = <&mmc_pins_uhs>;
  91. pinctrl-names = "default", "state_uhs";
  92. vmmc-supply = <&d3_3v>;
  93. vqmmc-supply = <&vddq_vin01>;
  94. mmc-hs200-1_8v;
  95. bus-width = <8>;
  96. non-removable;
  97. status = "okay";
  98. };
  99. &pfc {
  100. canfd0_pins: canfd0 {
  101. groups = "canfd0_data_a";
  102. function = "canfd0";
  103. };
  104. gether_pins: gether {
  105. groups = "gether_mdio_a", "gether_rgmii",
  106. "gether_txcrefclk", "gether_txcrefclk_mega";
  107. function = "gether";
  108. };
  109. i2c0_pins: i2c0 {
  110. groups = "i2c0";
  111. function = "i2c0";
  112. };
  113. mmc_pins: mmc {
  114. groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
  115. function = "mmc";
  116. power-source = <3300>;
  117. };
  118. mmc_pins_uhs: mmc_uhs {
  119. groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
  120. function = "mmc";
  121. power-source = <1800>;
  122. };
  123. scif0_pins: scif0 {
  124. groups = "scif0_data";
  125. function = "scif0";
  126. };
  127. scif_clk_pins: scif_clk {
  128. groups = "scif_clk_b";
  129. function = "scif_clk";
  130. };
  131. };
  132. &scif0 {
  133. pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
  134. pinctrl-names = "default";
  135. status = "okay";
  136. };
  137. &scif_clk {
  138. clock-frequency = <14745600>;
  139. };