tegra210-p2595.dtsi 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. / {
  3. model = "NVIDIA Tegra210 P2595 I/O board";
  4. compatible = "nvidia,p2595", "nvidia,tegra210";
  5. pinmux: pinmux@700008d4 {
  6. pinctrl-names = "boot";
  7. pinctrl-0 = <&state_boot>;
  8. state_boot: pinmux {
  9. pex_l0_rst_n_pa0 {
  10. nvidia,pins = "pex_l0_rst_n_pa0";
  11. nvidia,function = "pe0";
  12. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  13. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  14. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  15. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  16. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  17. };
  18. pex_l0_clkreq_n_pa1 {
  19. nvidia,pins = "pex_l0_clkreq_n_pa1";
  20. nvidia,function = "pe0";
  21. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  22. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  23. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  24. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  25. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  26. };
  27. pex_wake_n_pa2 {
  28. nvidia,pins = "pex_wake_n_pa2";
  29. nvidia,function = "pe";
  30. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  31. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  32. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  33. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  34. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  35. };
  36. pex_l1_rst_n_pa3 {
  37. nvidia,pins = "pex_l1_rst_n_pa3";
  38. nvidia,function = "pe1";
  39. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  40. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  41. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  42. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  43. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  44. };
  45. pex_l1_clkreq_n_pa4 {
  46. nvidia,pins = "pex_l1_clkreq_n_pa4";
  47. nvidia,function = "pe1";
  48. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  49. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  50. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  51. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  52. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  53. };
  54. sata_led_active_pa5 {
  55. nvidia,pins = "sata_led_active_pa5";
  56. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  57. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  58. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  59. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  60. };
  61. pa6 {
  62. nvidia,pins = "pa6";
  63. nvidia,function = "rsvd1";
  64. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  65. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  66. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  67. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  68. };
  69. dap1_fs_pb0 {
  70. nvidia,pins = "dap1_fs_pb0";
  71. nvidia,function = "i2s1";
  72. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  73. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  74. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  75. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  76. };
  77. dap1_din_pb1 {
  78. nvidia,pins = "dap1_din_pb1";
  79. nvidia,function = "i2s1";
  80. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  81. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  82. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  83. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  84. };
  85. dap1_dout_pb2 {
  86. nvidia,pins = "dap1_dout_pb2";
  87. nvidia,function = "i2s1";
  88. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  89. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  90. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  91. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  92. };
  93. dap1_sclk_pb3 {
  94. nvidia,pins = "dap1_sclk_pb3";
  95. nvidia,function = "i2s1";
  96. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  97. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  98. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  99. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  100. };
  101. spi2_mosi_pb4 {
  102. nvidia,pins = "spi2_mosi_pb4";
  103. nvidia,function = "rsvd2";
  104. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  105. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  106. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  107. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  108. };
  109. spi2_miso_pb5 {
  110. nvidia,pins = "spi2_miso_pb5";
  111. nvidia,function = "rsvd2";
  112. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  113. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  114. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  115. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  116. };
  117. spi2_sck_pb6 {
  118. nvidia,pins = "spi2_sck_pb6";
  119. nvidia,function = "rsvd2";
  120. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  121. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  122. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  123. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  124. };
  125. spi2_cs0_pb7 {
  126. nvidia,pins = "spi2_cs0_pb7";
  127. nvidia,function = "rsvd2";
  128. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  129. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  130. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  131. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  132. };
  133. spi1_mosi_pc0 {
  134. nvidia,pins = "spi1_mosi_pc0";
  135. nvidia,function = "spi1";
  136. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  137. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  138. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  139. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  140. };
  141. spi1_miso_pc1 {
  142. nvidia,pins = "spi1_miso_pc1";
  143. nvidia,function = "spi1";
  144. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  145. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  146. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  147. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  148. };
  149. spi1_sck_pc2 {
  150. nvidia,pins = "spi1_sck_pc2";
  151. nvidia,function = "spi1";
  152. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  153. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  154. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  155. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  156. };
  157. spi1_cs0_pc3 {
  158. nvidia,pins = "spi1_cs0_pc3";
  159. nvidia,function = "spi1";
  160. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  161. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  162. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  163. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  164. };
  165. spi1_cs1_pc4 {
  166. nvidia,pins = "spi1_cs1_pc4";
  167. nvidia,function = "spi1";
  168. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  169. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  170. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  171. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  172. };
  173. spi4_sck_pc5 {
  174. nvidia,pins = "spi4_sck_pc5";
  175. nvidia,function = "spi4";
  176. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  177. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  178. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  179. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  180. };
  181. spi4_cs0_pc6 {
  182. nvidia,pins = "spi4_cs0_pc6";
  183. nvidia,function = "spi4";
  184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  186. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  187. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  188. };
  189. spi4_mosi_pc7 {
  190. nvidia,pins = "spi4_mosi_pc7";
  191. nvidia,function = "spi4";
  192. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  193. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  194. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  195. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  196. };
  197. spi4_miso_pd0 {
  198. nvidia,pins = "spi4_miso_pd0";
  199. nvidia,function = "spi4";
  200. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  201. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  202. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  203. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  204. };
  205. uart3_tx_pd1 {
  206. nvidia,pins = "uart3_tx_pd1";
  207. nvidia,function = "uartc";
  208. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  209. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  210. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  211. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  212. };
  213. uart3_rx_pd2 {
  214. nvidia,pins = "uart3_rx_pd2";
  215. nvidia,function = "uartc";
  216. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  217. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  218. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  219. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  220. };
  221. uart3_rts_pd3 {
  222. nvidia,pins = "uart3_rts_pd3";
  223. nvidia,function = "uartc";
  224. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  225. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  226. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  227. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  228. };
  229. uart3_cts_pd4 {
  230. nvidia,pins = "uart3_cts_pd4";
  231. nvidia,function = "uartc";
  232. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  233. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  234. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  235. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  236. };
  237. dmic1_clk_pe0 {
  238. nvidia,pins = "dmic1_clk_pe0";
  239. nvidia,function = "dmic1";
  240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  241. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  242. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  243. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  244. };
  245. dmic1_dat_pe1 {
  246. nvidia,pins = "dmic1_dat_pe1";
  247. nvidia,function = "dmic1";
  248. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  251. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  252. };
  253. dmic2_clk_pe2 {
  254. nvidia,pins = "dmic2_clk_pe2";
  255. nvidia,function = "dmic2";
  256. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  258. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  259. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  260. };
  261. dmic2_dat_pe3 {
  262. nvidia,pins = "dmic2_dat_pe3";
  263. nvidia,function = "dmic2";
  264. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  265. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  266. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  267. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  268. };
  269. dmic3_clk_pe4 {
  270. nvidia,pins = "dmic3_clk_pe4";
  271. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  272. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  273. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  274. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  275. };
  276. dmic3_dat_pe5 {
  277. nvidia,pins = "dmic3_dat_pe5";
  278. nvidia,function = "rsvd2";
  279. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  280. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  281. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  282. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  283. };
  284. pe6 {
  285. nvidia,pins = "pe6";
  286. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  287. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  288. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  289. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  290. };
  291. pe7 {
  292. nvidia,pins = "pe7";
  293. nvidia,function = "pwm3";
  294. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  295. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  296. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  297. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  298. };
  299. gen3_i2c_scl_pf0 {
  300. nvidia,pins = "gen3_i2c_scl_pf0";
  301. nvidia,function = "i2c3";
  302. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  303. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  304. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  305. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  306. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  307. };
  308. gen3_i2c_sda_pf1 {
  309. nvidia,pins = "gen3_i2c_sda_pf1";
  310. nvidia,function = "i2c3";
  311. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  312. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  313. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  314. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  315. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  316. };
  317. uart2_tx_pg0 {
  318. nvidia,pins = "uart2_tx_pg0";
  319. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  320. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  321. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  322. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  323. };
  324. uart2_rx_pg1 {
  325. nvidia,pins = "uart2_rx_pg1";
  326. nvidia,function = "uartb";
  327. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  328. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  329. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  330. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  331. };
  332. uart2_rts_pg2 {
  333. nvidia,pins = "uart2_rts_pg2";
  334. nvidia,function = "rsvd2";
  335. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  336. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  337. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  338. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  339. };
  340. uart2_cts_pg3 {
  341. nvidia,pins = "uart2_cts_pg3";
  342. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  343. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  344. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  345. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  346. };
  347. wifi_en_ph0 {
  348. nvidia,pins = "wifi_en_ph0";
  349. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  350. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  351. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  352. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  353. };
  354. wifi_rst_ph1 {
  355. nvidia,pins = "wifi_rst_ph1";
  356. nvidia,function = "rsvd0";
  357. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  358. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  359. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  360. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  361. };
  362. wifi_wake_ap_ph2 {
  363. nvidia,pins = "wifi_wake_ap_ph2";
  364. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  365. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  366. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  367. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  368. };
  369. ap_wake_bt_ph3 {
  370. nvidia,pins = "ap_wake_bt_ph3";
  371. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  372. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  373. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  374. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  375. };
  376. bt_rst_ph4 {
  377. nvidia,pins = "bt_rst_ph4";
  378. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  379. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  380. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  381. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  382. };
  383. bt_wake_ap_ph5 {
  384. nvidia,pins = "bt_wake_ap_ph5";
  385. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  386. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  387. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  388. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  389. };
  390. ph6 {
  391. nvidia,pins = "ph6";
  392. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  393. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  394. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  395. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  396. };
  397. ap_wake_nfc_ph7 {
  398. nvidia,pins = "ap_wake_nfc_ph7";
  399. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  400. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  401. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  402. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  403. };
  404. nfc_en_pi0 {
  405. nvidia,pins = "nfc_en_pi0";
  406. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  407. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  408. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  409. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  410. };
  411. nfc_int_pi1 {
  412. nvidia,pins = "nfc_int_pi1";
  413. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  414. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  415. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  416. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  417. };
  418. gps_en_pi2 {
  419. nvidia,pins = "gps_en_pi2";
  420. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  421. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  422. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  423. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  424. };
  425. gps_rst_pi3 {
  426. nvidia,pins = "gps_rst_pi3";
  427. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  428. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  429. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  430. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  431. };
  432. uart4_tx_pi4 {
  433. nvidia,pins = "uart4_tx_pi4";
  434. nvidia,function = "uartd";
  435. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  436. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  437. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  438. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  439. };
  440. uart4_rx_pi5 {
  441. nvidia,pins = "uart4_rx_pi5";
  442. nvidia,function = "uartd";
  443. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  444. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  445. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  446. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  447. };
  448. uart4_rts_pi6 {
  449. nvidia,pins = "uart4_rts_pi6";
  450. nvidia,function = "uartd";
  451. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  452. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  453. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  454. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  455. };
  456. uart4_cts_pi7 {
  457. nvidia,pins = "uart4_cts_pi7";
  458. nvidia,function = "uartd";
  459. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  460. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  461. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  462. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  463. };
  464. gen1_i2c_sda_pj0 {
  465. nvidia,pins = "gen1_i2c_sda_pj0";
  466. nvidia,function = "i2c1";
  467. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  468. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  469. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  470. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  471. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  472. };
  473. gen1_i2c_scl_pj1 {
  474. nvidia,pins = "gen1_i2c_scl_pj1";
  475. nvidia,function = "i2c1";
  476. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  477. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  478. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  479. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  480. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  481. };
  482. gen2_i2c_scl_pj2 {
  483. nvidia,pins = "gen2_i2c_scl_pj2";
  484. nvidia,function = "i2c2";
  485. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  486. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  487. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  488. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  489. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  490. };
  491. gen2_i2c_sda_pj3 {
  492. nvidia,pins = "gen2_i2c_sda_pj3";
  493. nvidia,function = "i2c2";
  494. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  495. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  496. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  497. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  498. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  499. };
  500. dap4_fs_pj4 {
  501. nvidia,pins = "dap4_fs_pj4";
  502. nvidia,function = "i2s4b";
  503. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  504. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  505. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  506. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  507. };
  508. dap4_din_pj5 {
  509. nvidia,pins = "dap4_din_pj5";
  510. nvidia,function = "i2s4b";
  511. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  512. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  513. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  514. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  515. };
  516. dap4_dout_pj6 {
  517. nvidia,pins = "dap4_dout_pj6";
  518. nvidia,function = "i2s4b";
  519. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  520. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  521. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  522. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  523. };
  524. dap4_sclk_pj7 {
  525. nvidia,pins = "dap4_sclk_pj7";
  526. nvidia,function = "i2s4b";
  527. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  528. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  529. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  530. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  531. };
  532. pk0 {
  533. nvidia,pins = "pk0";
  534. nvidia,function = "i2s5b";
  535. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  536. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  537. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  538. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  539. };
  540. pk1 {
  541. nvidia,pins = "pk1";
  542. nvidia,function = "i2s5b";
  543. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  544. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  545. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  546. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  547. };
  548. pk2 {
  549. nvidia,pins = "pk2";
  550. nvidia,function = "i2s5b";
  551. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  552. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  553. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  554. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  555. };
  556. pk3 {
  557. nvidia,pins = "pk3";
  558. nvidia,function = "i2s5b";
  559. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  560. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  561. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  562. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  563. };
  564. pk4 {
  565. nvidia,pins = "pk4";
  566. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  567. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  568. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  569. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  570. };
  571. pk5 {
  572. nvidia,pins = "pk5";
  573. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  574. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  575. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  576. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  577. };
  578. pk6 {
  579. nvidia,pins = "pk6";
  580. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  581. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  582. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  583. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  584. };
  585. pk7 {
  586. nvidia,pins = "pk7";
  587. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  588. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  589. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  590. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  591. };
  592. pl0 {
  593. nvidia,pins = "pl0";
  594. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  595. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  596. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  597. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  598. };
  599. pl1 {
  600. nvidia,pins = "pl1";
  601. nvidia,function = "soc";
  602. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  603. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  604. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  605. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  606. };
  607. sdmmc1_clk_pm0 {
  608. nvidia,pins = "sdmmc1_clk_pm0";
  609. nvidia,function = "sdmmc1";
  610. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  611. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  612. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  613. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  614. };
  615. sdmmc1_cmd_pm1 {
  616. nvidia,pins = "sdmmc1_cmd_pm1";
  617. nvidia,function = "sdmmc1";
  618. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  619. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  620. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  621. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  622. };
  623. sdmmc1_dat3_pm2 {
  624. nvidia,pins = "sdmmc1_dat3_pm2";
  625. nvidia,function = "sdmmc1";
  626. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  627. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  628. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  629. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  630. };
  631. sdmmc1_dat2_pm3 {
  632. nvidia,pins = "sdmmc1_dat2_pm3";
  633. nvidia,function = "sdmmc1";
  634. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  635. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  636. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  637. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  638. };
  639. sdmmc1_dat1_pm4 {
  640. nvidia,pins = "sdmmc1_dat1_pm4";
  641. nvidia,function = "sdmmc1";
  642. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  643. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  644. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  645. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  646. };
  647. sdmmc1_dat0_pm5 {
  648. nvidia,pins = "sdmmc1_dat0_pm5";
  649. nvidia,function = "sdmmc1";
  650. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  651. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  652. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  653. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  654. };
  655. sdmmc3_clk_pp0 {
  656. nvidia,pins = "sdmmc3_clk_pp0";
  657. nvidia,function = "sdmmc3";
  658. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  659. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  660. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  661. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  662. };
  663. sdmmc3_cmd_pp1 {
  664. nvidia,pins = "sdmmc3_cmd_pp1";
  665. nvidia,function = "sdmmc3";
  666. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  667. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  668. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  669. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  670. };
  671. sdmmc3_dat3_pp2 {
  672. nvidia,pins = "sdmmc3_dat3_pp2";
  673. nvidia,function = "sdmmc3";
  674. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  675. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  676. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  677. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  678. };
  679. sdmmc3_dat2_pp3 {
  680. nvidia,pins = "sdmmc3_dat2_pp3";
  681. nvidia,function = "sdmmc3";
  682. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  683. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  684. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  685. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  686. };
  687. sdmmc3_dat1_pp4 {
  688. nvidia,pins = "sdmmc3_dat1_pp4";
  689. nvidia,function = "sdmmc3";
  690. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  691. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  692. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  693. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  694. };
  695. sdmmc3_dat0_pp5 {
  696. nvidia,pins = "sdmmc3_dat0_pp5";
  697. nvidia,function = "sdmmc3";
  698. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  699. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  700. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  701. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  702. };
  703. cam1_mclk_ps0 {
  704. nvidia,pins = "cam1_mclk_ps0";
  705. nvidia,function = "extperiph3";
  706. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  707. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  708. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  709. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  710. };
  711. cam2_mclk_ps1 {
  712. nvidia,pins = "cam2_mclk_ps1";
  713. nvidia,function = "extperiph3";
  714. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  715. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  716. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  717. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  718. };
  719. cam_i2c_scl_ps2 {
  720. nvidia,pins = "cam_i2c_scl_ps2";
  721. nvidia,function = "i2cvi";
  722. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  723. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  724. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  725. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  726. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  727. };
  728. cam_i2c_sda_ps3 {
  729. nvidia,pins = "cam_i2c_sda_ps3";
  730. nvidia,function = "i2cvi";
  731. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  732. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  733. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  734. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  735. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  736. };
  737. cam_rst_ps4 {
  738. nvidia,pins = "cam_rst_ps4";
  739. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  740. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  741. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  742. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  743. };
  744. cam_af_en_ps5 {
  745. nvidia,pins = "cam_af_en_ps5";
  746. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  747. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  748. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  749. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  750. };
  751. cam_flash_en_ps6 {
  752. nvidia,pins = "cam_flash_en_ps6";
  753. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  754. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  755. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  756. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  757. };
  758. cam1_pwdn_ps7 {
  759. nvidia,pins = "cam1_pwdn_ps7";
  760. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  761. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  762. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  763. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  764. };
  765. cam2_pwdn_pt0 {
  766. nvidia,pins = "cam2_pwdn_pt0";
  767. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  768. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  769. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  770. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  771. };
  772. cam1_strobe_pt1 {
  773. nvidia,pins = "cam1_strobe_pt1";
  774. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  775. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  776. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  777. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  778. };
  779. uart1_tx_pu0 {
  780. nvidia,pins = "uart1_tx_pu0";
  781. nvidia,function = "uarta";
  782. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  783. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  784. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  785. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  786. };
  787. uart1_rx_pu1 {
  788. nvidia,pins = "uart1_rx_pu1";
  789. nvidia,function = "uarta";
  790. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  791. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  792. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  793. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  794. };
  795. uart1_rts_pu2 {
  796. nvidia,pins = "uart1_rts_pu2";
  797. nvidia,function = "uarta";
  798. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  799. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  800. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  801. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  802. };
  803. uart1_cts_pu3 {
  804. nvidia,pins = "uart1_cts_pu3";
  805. nvidia,function = "uarta";
  806. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  807. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  808. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  809. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  810. };
  811. lcd_bl_pwm_pv0 {
  812. nvidia,pins = "lcd_bl_pwm_pv0";
  813. nvidia,function = "pwm0";
  814. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  815. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  816. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  817. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  818. };
  819. lcd_bl_en_pv1 {
  820. nvidia,pins = "lcd_bl_en_pv1";
  821. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  822. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  823. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  824. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  825. };
  826. lcd_rst_pv2 {
  827. nvidia,pins = "lcd_rst_pv2";
  828. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  829. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  830. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  831. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  832. };
  833. lcd_gpio1_pv3 {
  834. nvidia,pins = "lcd_gpio1_pv3";
  835. nvidia,function = "rsvd1";
  836. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  837. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  838. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  839. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  840. };
  841. lcd_gpio2_pv4 {
  842. nvidia,pins = "lcd_gpio2_pv4";
  843. nvidia,function = "pwm1";
  844. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  845. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  846. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  847. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  848. };
  849. ap_ready_pv5 {
  850. nvidia,pins = "ap_ready_pv5";
  851. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  852. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  853. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  854. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  855. };
  856. touch_rst_pv6 {
  857. nvidia,pins = "touch_rst_pv6";
  858. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  859. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  860. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  861. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  862. };
  863. touch_clk_pv7 {
  864. nvidia,pins = "touch_clk_pv7";
  865. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  866. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  867. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  868. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  869. };
  870. modem_wake_ap_px0 {
  871. nvidia,pins = "modem_wake_ap_px0";
  872. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  873. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  874. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  875. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  876. };
  877. touch_int_px1 {
  878. nvidia,pins = "touch_int_px1";
  879. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  880. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  881. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  882. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  883. };
  884. motion_int_px2 {
  885. nvidia,pins = "motion_int_px2";
  886. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  887. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  888. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  889. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  890. };
  891. als_prox_int_px3 {
  892. nvidia,pins = "als_prox_int_px3";
  893. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  894. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  895. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  896. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  897. };
  898. temp_alert_px4 {
  899. nvidia,pins = "temp_alert_px4";
  900. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  901. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  902. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  903. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  904. };
  905. button_power_on_px5 {
  906. nvidia,pins = "button_power_on_px5";
  907. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  908. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  909. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  910. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  911. };
  912. button_vol_up_px6 {
  913. nvidia,pins = "button_vol_up_px6";
  914. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  915. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  916. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  917. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  918. };
  919. button_vol_down_px7 {
  920. nvidia,pins = "button_vol_down_px7";
  921. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  922. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  923. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  924. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  925. };
  926. button_slide_sw_py0 {
  927. nvidia,pins = "button_slide_sw_py0";
  928. nvidia,function = "rsvd0";
  929. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  930. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  931. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  932. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  933. };
  934. button_home_py1 {
  935. nvidia,pins = "button_home_py1";
  936. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  937. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  938. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  939. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  940. };
  941. lcd_te_py2 {
  942. nvidia,pins = "lcd_te_py2";
  943. nvidia,function = "displaya";
  944. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  945. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  946. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  947. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  948. };
  949. pwr_i2c_scl_py3 {
  950. nvidia,pins = "pwr_i2c_scl_py3";
  951. nvidia,function = "i2cpmu";
  952. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  953. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  954. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  955. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  956. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  957. };
  958. pwr_i2c_sda_py4 {
  959. nvidia,pins = "pwr_i2c_sda_py4";
  960. nvidia,function = "i2cpmu";
  961. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  962. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  963. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  964. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  965. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  966. };
  967. clk_32k_out_py5 {
  968. nvidia,pins = "clk_32k_out_py5";
  969. nvidia,function = "soc";
  970. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  971. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  972. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  973. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  974. };
  975. pz0 {
  976. nvidia,pins = "pz0";
  977. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  978. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  979. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  980. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  981. };
  982. pz1 {
  983. nvidia,pins = "pz1";
  984. nvidia,function = "sdmmc1";
  985. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  986. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  987. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  988. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  989. };
  990. pz2 {
  991. nvidia,pins = "pz2";
  992. nvidia,function = "rsvd2";
  993. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  994. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  995. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  996. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  997. };
  998. pz3 {
  999. nvidia,pins = "pz3";
  1000. nvidia,function = "rsvd1";
  1001. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1002. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1003. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1004. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1005. };
  1006. pz4 {
  1007. nvidia,pins = "pz4";
  1008. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1009. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1010. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1011. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1012. };
  1013. pz5 {
  1014. nvidia,pins = "pz5";
  1015. nvidia,function = "soc";
  1016. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1017. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1018. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1019. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1020. };
  1021. dap2_fs_paa0 {
  1022. nvidia,pins = "dap2_fs_paa0";
  1023. nvidia,function = "i2s2";
  1024. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1025. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1026. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1027. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1028. };
  1029. dap2_sclk_paa1 {
  1030. nvidia,pins = "dap2_sclk_paa1";
  1031. nvidia,function = "i2s2";
  1032. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1033. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1034. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1035. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1036. };
  1037. dap2_din_paa2 {
  1038. nvidia,pins = "dap2_din_paa2";
  1039. nvidia,function = "i2s2";
  1040. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1041. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1042. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1043. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1044. };
  1045. dap2_dout_paa3 {
  1046. nvidia,pins = "dap2_dout_paa3";
  1047. nvidia,function = "i2s2";
  1048. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1049. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1050. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1051. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1052. };
  1053. aud_mclk_pbb0 {
  1054. nvidia,pins = "aud_mclk_pbb0";
  1055. nvidia,function = "aud";
  1056. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1057. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1058. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1059. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1060. };
  1061. dvfs_pwm_pbb1 {
  1062. nvidia,pins = "dvfs_pwm_pbb1";
  1063. nvidia,function = "cldvfs";
  1064. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1065. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1066. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1067. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1068. };
  1069. dvfs_clk_pbb2 {
  1070. nvidia,pins = "dvfs_clk_pbb2";
  1071. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1072. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1073. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1074. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1075. };
  1076. gpio_x1_aud_pbb3 {
  1077. nvidia,pins = "gpio_x1_aud_pbb3";
  1078. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1079. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1080. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1081. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1082. };
  1083. gpio_x3_aud_pbb4 {
  1084. nvidia,pins = "gpio_x3_aud_pbb4";
  1085. nvidia,function = "rsvd0";
  1086. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1087. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1088. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1089. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1090. };
  1091. hdmi_cec_pcc0 {
  1092. nvidia,pins = "hdmi_cec_pcc0";
  1093. nvidia,function = "cec";
  1094. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1095. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1096. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1097. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1098. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1099. };
  1100. hdmi_int_dp_hpd_pcc1 {
  1101. nvidia,pins = "hdmi_int_dp_hpd_pcc1";
  1102. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1103. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1104. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1105. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1106. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1107. };
  1108. spdif_out_pcc2 {
  1109. nvidia,pins = "spdif_out_pcc2";
  1110. nvidia,function = "rsvd1";
  1111. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1112. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1113. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1114. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1115. };
  1116. spdif_in_pcc3 {
  1117. nvidia,pins = "spdif_in_pcc3";
  1118. nvidia,function = "rsvd1";
  1119. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1120. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1121. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1122. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1123. };
  1124. usb_vbus_en0_pcc4 {
  1125. nvidia,pins = "usb_vbus_en0_pcc4";
  1126. nvidia,function = "usb";
  1127. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1128. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1129. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1130. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1131. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1132. };
  1133. usb_vbus_en1_pcc5 {
  1134. nvidia,pins = "usb_vbus_en1_pcc5";
  1135. nvidia,function = "rsvd1";
  1136. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1137. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1138. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1139. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1140. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1141. };
  1142. dp_hpd0_pcc6 {
  1143. nvidia,pins = "dp_hpd0_pcc6";
  1144. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1145. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1146. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1147. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1148. };
  1149. pcc7 {
  1150. nvidia,pins = "pcc7";
  1151. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1152. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1153. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1154. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1155. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1156. };
  1157. spi2_cs1_pdd0 {
  1158. nvidia,pins = "spi2_cs1_pdd0";
  1159. nvidia,function = "rsvd1";
  1160. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1161. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1162. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1163. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1164. };
  1165. qspi_sck_pee0 {
  1166. nvidia,pins = "qspi_sck_pee0";
  1167. nvidia,function = "rsvd1";
  1168. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1169. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1170. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1171. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1172. };
  1173. qspi_cs_n_pee1 {
  1174. nvidia,pins = "qspi_cs_n_pee1";
  1175. nvidia,function = "rsvd1";
  1176. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1177. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1178. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1179. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1180. };
  1181. qspi_io0_pee2 {
  1182. nvidia,pins = "qspi_io0_pee2";
  1183. nvidia,function = "rsvd1";
  1184. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1185. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1186. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1187. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1188. };
  1189. qspi_io1_pee3 {
  1190. nvidia,pins = "qspi_io1_pee3";
  1191. nvidia,function = "rsvd1";
  1192. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1193. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1194. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1195. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1196. };
  1197. qspi_io2_pee4 {
  1198. nvidia,pins = "qspi_io2_pee4";
  1199. nvidia,function = "rsvd1";
  1200. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1201. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1202. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1203. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1204. };
  1205. qspi_io3_pee5 {
  1206. nvidia,pins = "qspi_io3_pee5";
  1207. nvidia,function = "rsvd1";
  1208. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1209. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1210. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1211. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1212. };
  1213. core_pwr_req {
  1214. nvidia,pins = "core_pwr_req";
  1215. nvidia,function = "core";
  1216. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1217. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1218. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1219. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1220. };
  1221. cpu_pwr_req {
  1222. nvidia,pins = "cpu_pwr_req";
  1223. nvidia,function = "cpu";
  1224. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1225. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1226. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1227. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1228. };
  1229. pwr_int_n {
  1230. nvidia,pins = "pwr_int_n";
  1231. nvidia,function = "pmi";
  1232. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1233. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1234. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1235. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1236. };
  1237. clk_32k_in {
  1238. nvidia,pins = "clk_32k_in";
  1239. nvidia,function = "clk";
  1240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1241. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1242. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1243. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1244. };
  1245. jtag_rtck {
  1246. nvidia,pins = "jtag_rtck";
  1247. nvidia,function = "jtag";
  1248. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1250. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1251. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1252. };
  1253. clk_req {
  1254. nvidia,pins = "clk_req";
  1255. nvidia,function = "sys";
  1256. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1258. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1259. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1260. };
  1261. shutdown {
  1262. nvidia,pins = "shutdown";
  1263. nvidia,function = "shutdown";
  1264. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1265. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1266. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1267. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1268. };
  1269. };
  1270. };
  1271. };