hip06.dtsi 21 KB

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  1. /**
  2. * dts file for Hisilicon D03 Development Board
  3. *
  4. * Copyright (C) 2016 Hisilicon Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * publishhed by the Free Software Foundation.
  9. *
  10. */
  11. #include <dt-bindings/interrupt-controller/arm-gic.h>
  12. / {
  13. compatible = "hisilicon,hip06-d03";
  14. interrupt-parent = <&gic>;
  15. #address-cells = <2>;
  16. #size-cells = <2>;
  17. psci {
  18. compatible = "arm,psci-0.2";
  19. method = "smc";
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu-map {
  25. cluster0 {
  26. core0 {
  27. cpu = <&cpu0>;
  28. };
  29. core1 {
  30. cpu = <&cpu1>;
  31. };
  32. core2 {
  33. cpu = <&cpu2>;
  34. };
  35. core3 {
  36. cpu = <&cpu3>;
  37. };
  38. };
  39. cluster1 {
  40. core0 {
  41. cpu = <&cpu4>;
  42. };
  43. core1 {
  44. cpu = <&cpu5>;
  45. };
  46. core2 {
  47. cpu = <&cpu6>;
  48. };
  49. core3 {
  50. cpu = <&cpu7>;
  51. };
  52. };
  53. cluster2 {
  54. core0 {
  55. cpu = <&cpu8>;
  56. };
  57. core1 {
  58. cpu = <&cpu9>;
  59. };
  60. core2 {
  61. cpu = <&cpu10>;
  62. };
  63. core3 {
  64. cpu = <&cpu11>;
  65. };
  66. };
  67. cluster3 {
  68. core0 {
  69. cpu = <&cpu12>;
  70. };
  71. core1 {
  72. cpu = <&cpu13>;
  73. };
  74. core2 {
  75. cpu = <&cpu14>;
  76. };
  77. core3 {
  78. cpu = <&cpu15>;
  79. };
  80. };
  81. };
  82. cpu0: cpu@10000 {
  83. device_type = "cpu";
  84. compatible = "arm,cortex-a57", "arm,armv8";
  85. reg = <0x10000>;
  86. enable-method = "psci";
  87. next-level-cache = <&cluster0_l2>;
  88. };
  89. cpu1: cpu@10001 {
  90. device_type = "cpu";
  91. compatible = "arm,cortex-a57", "arm,armv8";
  92. reg = <0x10001>;
  93. enable-method = "psci";
  94. next-level-cache = <&cluster0_l2>;
  95. };
  96. cpu2: cpu@10002 {
  97. device_type = "cpu";
  98. compatible = "arm,cortex-a57", "arm,armv8";
  99. reg = <0x10002>;
  100. enable-method = "psci";
  101. next-level-cache = <&cluster0_l2>;
  102. };
  103. cpu3: cpu@10003 {
  104. device_type = "cpu";
  105. compatible = "arm,cortex-a57", "arm,armv8";
  106. reg = <0x10003>;
  107. enable-method = "psci";
  108. next-level-cache = <&cluster0_l2>;
  109. };
  110. cpu4: cpu@10100 {
  111. device_type = "cpu";
  112. compatible = "arm,cortex-a57", "arm,armv8";
  113. reg = <0x10100>;
  114. enable-method = "psci";
  115. next-level-cache = <&cluster1_l2>;
  116. };
  117. cpu5: cpu@10101 {
  118. device_type = "cpu";
  119. compatible = "arm,cortex-a57", "arm,armv8";
  120. reg = <0x10101>;
  121. enable-method = "psci";
  122. next-level-cache = <&cluster1_l2>;
  123. };
  124. cpu6: cpu@10102 {
  125. device_type = "cpu";
  126. compatible = "arm,cortex-a57", "arm,armv8";
  127. reg = <0x10102>;
  128. enable-method = "psci";
  129. next-level-cache = <&cluster1_l2>;
  130. };
  131. cpu7: cpu@10103 {
  132. device_type = "cpu";
  133. compatible = "arm,cortex-a57", "arm,armv8";
  134. reg = <0x10103>;
  135. enable-method = "psci";
  136. next-level-cache = <&cluster1_l2>;
  137. };
  138. cpu8: cpu@10200 {
  139. device_type = "cpu";
  140. compatible = "arm,cortex-a57", "arm,armv8";
  141. reg = <0x10200>;
  142. enable-method = "psci";
  143. next-level-cache = <&cluster2_l2>;
  144. };
  145. cpu9: cpu@10201 {
  146. device_type = "cpu";
  147. compatible = "arm,cortex-a57", "arm,armv8";
  148. reg = <0x10201>;
  149. enable-method = "psci";
  150. next-level-cache = <&cluster2_l2>;
  151. };
  152. cpu10: cpu@10202 {
  153. device_type = "cpu";
  154. compatible = "arm,cortex-a57", "arm,armv8";
  155. reg = <0x10202>;
  156. enable-method = "psci";
  157. next-level-cache = <&cluster2_l2>;
  158. };
  159. cpu11: cpu@10203 {
  160. device_type = "cpu";
  161. compatible = "arm,cortex-a57", "arm,armv8";
  162. reg = <0x10203>;
  163. enable-method = "psci";
  164. next-level-cache = <&cluster2_l2>;
  165. };
  166. cpu12: cpu@10300 {
  167. device_type = "cpu";
  168. compatible = "arm,cortex-a57", "arm,armv8";
  169. reg = <0x10300>;
  170. enable-method = "psci";
  171. next-level-cache = <&cluster3_l2>;
  172. };
  173. cpu13: cpu@10301 {
  174. device_type = "cpu";
  175. compatible = "arm,cortex-a57", "arm,armv8";
  176. reg = <0x10301>;
  177. enable-method = "psci";
  178. next-level-cache = <&cluster3_l2>;
  179. };
  180. cpu14: cpu@10302 {
  181. device_type = "cpu";
  182. compatible = "arm,cortex-a57", "arm,armv8";
  183. reg = <0x10302>;
  184. enable-method = "psci";
  185. next-level-cache = <&cluster3_l2>;
  186. };
  187. cpu15: cpu@10303 {
  188. device_type = "cpu";
  189. compatible = "arm,cortex-a57", "arm,armv8";
  190. reg = <0x10303>;
  191. enable-method = "psci";
  192. next-level-cache = <&cluster3_l2>;
  193. };
  194. cluster0_l2: l2-cache0 {
  195. compatible = "cache";
  196. };
  197. cluster1_l2: l2-cache1 {
  198. compatible = "cache";
  199. };
  200. cluster2_l2: l2-cache2 {
  201. compatible = "cache";
  202. };
  203. cluster3_l2: l2-cache3 {
  204. compatible = "cache";
  205. };
  206. };
  207. gic: interrupt-controller@4d000000 {
  208. compatible = "arm,gic-v3";
  209. #interrupt-cells = <3>;
  210. #address-cells = <2>;
  211. #size-cells = <2>;
  212. ranges;
  213. interrupt-controller;
  214. #redistributor-regions = <1>;
  215. redistributor-stride = <0x0 0x30000>;
  216. reg = <0x0 0x4d000000 0 0x10000>, /* GICD */
  217. <0x0 0x4d100000 0 0x300000>, /* GICR */
  218. <0x0 0xfe000000 0 0x10000>, /* GICC */
  219. <0x0 0xfe010000 0 0x10000>, /* GICH */
  220. <0x0 0xfe020000 0 0x10000>; /* GICV */
  221. interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  222. its_dsa: interrupt-controller@c6000000 {
  223. compatible = "arm,gic-v3-its";
  224. msi-controller;
  225. #msi-cells = <1>;
  226. reg = <0x0 0xc6000000 0x0 0x40000>;
  227. };
  228. };
  229. timer {
  230. compatible = "arm,armv8-timer";
  231. interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  232. <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  233. <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  234. <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  235. };
  236. pmu {
  237. compatible = "arm,cortex-a57-pmu";
  238. interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  239. };
  240. mbigen_pcie@a0080000 {
  241. compatible = "hisilicon,mbigen-v2";
  242. reg = <0x0 0xa0080000 0x0 0x10000>;
  243. mbigen_usb: intc_usb {
  244. msi-parent = <&its_dsa 0x40080>;
  245. interrupt-controller;
  246. #interrupt-cells = <2>;
  247. num-pins = <2>;
  248. };
  249. mbigen_sas1: intc_sas1 {
  250. msi-parent = <&its_dsa 0x40000>;
  251. interrupt-controller;
  252. #interrupt-cells = <2>;
  253. num-pins = <128>;
  254. };
  255. mbigen_sas2: intc_sas2 {
  256. msi-parent = <&its_dsa 0x40040>;
  257. interrupt-controller;
  258. #interrupt-cells = <2>;
  259. num-pins = <128>;
  260. };
  261. mbigen_pcie0: intc_pcie0 {
  262. msi-parent = <&its_dsa 0x40085>;
  263. interrupt-controller;
  264. #interrupt-cells = <2>;
  265. num-pins = <10>;
  266. };
  267. };
  268. mbigen_dsa@c0080000 {
  269. compatible = "hisilicon,mbigen-v2";
  270. reg = <0x0 0xc0080000 0x0 0x10000>;
  271. mbigen_dsaf0: intc_dsaf0 {
  272. msi-parent = <&its_dsa 0x40800>;
  273. interrupt-controller;
  274. #interrupt-cells = <2>;
  275. num-pins = <409>;
  276. };
  277. mbigen_sas0: intc-sas0 {
  278. msi-parent = <&its_dsa 0x40900>;
  279. interrupt-controller;
  280. #interrupt-cells = <2>;
  281. num-pins = <128>;
  282. };
  283. };
  284. /**
  285. * HiSilicon erratum 161010801: This describes the limitation
  286. * of HiSilicon platforms hip06/hip07 to support the SMMUv3
  287. * mappings for PCIe MSI transactions.
  288. * PCIe controller on these platforms has to differentiate the
  289. * MSI payload against other DMA payload and has to modify the
  290. * MSI payload. This makes it difficult for these platforms to
  291. * have a SMMU translation for MSI. In order to workaround this,
  292. * ARM SMMUv3 driver requires a quirk to treat the MSI regions
  293. * separately. Such a quirk is currently missing for DT based
  294. * systems. Hence please make sure that the smmu pcie node on
  295. * hip06 is disabled as this will break the PCIe functionality
  296. * when iommu-map entry is used along with the PCIe node.
  297. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
  298. */
  299. smmu0: smmu_pcie {
  300. compatible = "arm,smmu-v3";
  301. reg = <0x0 0xa0040000 0x0 0x20000>;
  302. #iommu-cells = <1>;
  303. dma-coherent;
  304. smmu-cb-memtype = <0x0 0x1>;
  305. hisilicon,broken-prefetch-cmd;
  306. status = "disabled";
  307. };
  308. soc {
  309. compatible = "simple-bus";
  310. #address-cells = <2>;
  311. #size-cells = <2>;
  312. ranges;
  313. isa@a01b0000 {
  314. compatible = "hisilicon,hip06-lpc";
  315. #size-cells = <1>;
  316. #address-cells = <2>;
  317. reg = <0x0 0xa01b0000 0x0 0x1000>;
  318. ipmi0: bt@e4 {
  319. compatible = "ipmi-bt";
  320. device_type = "ipmi";
  321. reg = <0x01 0xe4 0x04>;
  322. status = "disabled";
  323. };
  324. uart0: lpc-uart@2f8 {
  325. compatible = "ns16550a";
  326. clock-frequency = <1843200>;
  327. reg = <0x01 0x2f8 0x08>;
  328. status = "disabled";
  329. };
  330. };
  331. refclk: refclk {
  332. compatible = "fixed-clock";
  333. clock-frequency = <50000000>;
  334. #clock-cells = <0>;
  335. };
  336. usb_ohci: ohci@a7030000 {
  337. compatible = "generic-ohci";
  338. reg = <0x0 0xa7030000 0x0 0x10000>;
  339. interrupt-parent = <&mbigen_usb>;
  340. interrupts = <640 4>;
  341. dma-coherent;
  342. status = "disabled";
  343. };
  344. usb_ehci: ehci@a7020000 {
  345. compatible = "generic-ehci";
  346. reg = <0x0 0xa7020000 0x0 0x10000>;
  347. interrupt-parent = <&mbigen_usb>;
  348. interrupts = <641 4>;
  349. dma-coherent;
  350. status = "disabled";
  351. };
  352. peri_c_subctrl: sub_ctrl_c@60000000 {
  353. compatible = "hisilicon,peri-subctrl","syscon";
  354. reg = <0 0x60000000 0x0 0x10000>;
  355. };
  356. dsa_subctrl: dsa_subctrl@c0000000 {
  357. compatible = "hisilicon,dsa-subctrl", "syscon";
  358. reg = <0x0 0xc0000000 0x0 0x10000>;
  359. };
  360. pcie_subctl: pcie_subctl@a0000000 {
  361. compatible = "hisilicon,pcie-sas-subctrl", "syscon";
  362. reg = <0x0 0xa0000000 0x0 0x10000>;
  363. };
  364. serdes_ctrl: sds_ctrl@c2200000 {
  365. compatible = "syscon";
  366. reg = <0 0xc2200000 0x0 0x80000>;
  367. };
  368. mdio@603c0000 {
  369. compatible = "hisilicon,hns-mdio";
  370. reg = <0x0 0x603c0000 0x0 0x1000>;
  371. subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
  372. #address-cells = <1>;
  373. #size-cells = <0>;
  374. phy0: ethernet-phy@0 {
  375. compatible = "ethernet-phy-ieee802.3-c22";
  376. reg = <0>;
  377. };
  378. phy1: ethernet-phy@1 {
  379. compatible = "ethernet-phy-ieee802.3-c22";
  380. reg = <1>;
  381. };
  382. };
  383. dsaf0: dsa@c7000000 {
  384. #address-cells = <1>;
  385. #size-cells = <0>;
  386. compatible = "hisilicon,hns-dsaf-v2";
  387. mode = "6port-16rss";
  388. reg = <0x0 0xc5000000 0x0 0x890000
  389. 0x0 0xc7000000 0x0 0x600000>;
  390. reg-names = "ppe-base", "dsaf-base";
  391. interrupt-parent = <&mbigen_dsaf0>;
  392. subctrl-syscon = <&dsa_subctrl>;
  393. reset-field-offset = <0>;
  394. interrupts =
  395. <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
  396. <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
  397. <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
  398. <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
  399. <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
  400. <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
  401. <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
  402. <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
  403. <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
  404. <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
  405. <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
  406. <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
  407. <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
  408. <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
  409. <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
  410. <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
  411. <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
  412. <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
  413. <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
  414. <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
  415. <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
  416. <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
  417. <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
  418. <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
  419. <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
  420. <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
  421. <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
  422. <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
  423. <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
  424. <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
  425. <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
  426. <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
  427. <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
  428. <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
  429. <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
  430. <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
  431. <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
  432. <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
  433. <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
  434. <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
  435. <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
  436. <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
  437. <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
  438. <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
  439. <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
  440. <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
  441. <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
  442. <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
  443. <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
  444. <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
  445. <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
  446. <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
  447. <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
  448. <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
  449. <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
  450. <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
  451. <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
  452. <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
  453. <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
  454. <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
  455. <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
  456. <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
  457. <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
  458. <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
  459. <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
  460. <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
  461. <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
  462. <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
  463. <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
  464. <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
  465. <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
  466. <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
  467. <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
  468. <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
  469. <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
  470. <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
  471. <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
  472. <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
  473. <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
  474. <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
  475. <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
  476. <1340 1>, <1341 1>, <1342 1>, <1343 1>;
  477. desc-num = <0x400>;
  478. buf-size = <0x1000>;
  479. dma-coherent;
  480. port@0 {
  481. reg = <0>;
  482. serdes-syscon = <&serdes_ctrl>;
  483. port-rst-offset = <0>;
  484. port-mode-offset = <0>;
  485. media-type = "fiber";
  486. };
  487. port@1 {
  488. reg = <1>;
  489. serdes-syscon= <&serdes_ctrl>;
  490. port-rst-offset = <1>;
  491. port-mode-offset = <1>;
  492. media-type = "fiber";
  493. };
  494. port@4 {
  495. reg = <4>;
  496. phy-handle = <&phy0>;
  497. serdes-syscon= <&serdes_ctrl>;
  498. port-rst-offset = <4>;
  499. port-mode-offset = <2>;
  500. media-type = "copper";
  501. };
  502. port@5 {
  503. reg = <5>;
  504. phy-handle = <&phy1>;
  505. serdes-syscon= <&serdes_ctrl>;
  506. port-rst-offset = <5>;
  507. port-mode-offset = <3>;
  508. media-type = "copper";
  509. };
  510. };
  511. eth0: ethernet-4{
  512. compatible = "hisilicon,hns-nic-v2";
  513. ae-handle = <&dsaf0>;
  514. port-idx-in-ae = <4>;
  515. local-mac-address = [00 00 00 00 00 00];
  516. status = "disabled";
  517. dma-coherent;
  518. };
  519. eth1: ethernet-5{
  520. compatible = "hisilicon,hns-nic-v2";
  521. ae-handle = <&dsaf0>;
  522. port-idx-in-ae = <5>;
  523. local-mac-address = [00 00 00 00 00 00];
  524. status = "disabled";
  525. dma-coherent;
  526. };
  527. eth2: ethernet-0{
  528. compatible = "hisilicon,hns-nic-v2";
  529. ae-handle = <&dsaf0>;
  530. port-idx-in-ae = <0>;
  531. local-mac-address = [00 00 00 00 00 00];
  532. status = "disabled";
  533. dma-coherent;
  534. };
  535. eth3: ethernet-1{
  536. compatible = "hisilicon,hns-nic-v2";
  537. ae-handle = <&dsaf0>;
  538. port-idx-in-ae = <1>;
  539. local-mac-address = [00 00 00 00 00 00];
  540. status = "disabled";
  541. dma-coherent;
  542. };
  543. sas0: sas@c3000000 {
  544. compatible = "hisilicon,hip06-sas-v2";
  545. reg = <0 0xc3000000 0 0x10000>;
  546. sas-addr = [50 01 88 20 16 00 00 00];
  547. hisilicon,sas-syscon = <&dsa_subctrl>;
  548. ctrl-reset-reg = <0xa60>;
  549. ctrl-reset-sts-reg = <0x5a30>;
  550. ctrl-clock-ena-reg = <0x338>;
  551. clocks = <&refclk 0>;
  552. queue-count = <16>;
  553. phy-count = <8>;
  554. dma-coherent;
  555. interrupt-parent = <&mbigen_sas0>;
  556. interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
  557. <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
  558. <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
  559. <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
  560. <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
  561. <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
  562. <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
  563. <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
  564. <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
  565. <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
  566. <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
  567. <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
  568. <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
  569. <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
  570. <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
  571. <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
  572. <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
  573. <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
  574. <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
  575. <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
  576. <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
  577. <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
  578. <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
  579. <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
  580. <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
  581. <630 1>,<631 1>,<632 1>;
  582. status = "disabled";
  583. };
  584. sas1: sas@a2000000 {
  585. compatible = "hisilicon,hip06-sas-v2";
  586. reg = <0 0xa2000000 0 0x10000>;
  587. sas-addr = [50 01 88 20 16 00 00 00];
  588. hisilicon,sas-syscon = <&pcie_subctl>;
  589. hip06-sas-v2-quirk-amt;
  590. ctrl-reset-reg = <0xa18>;
  591. ctrl-reset-sts-reg = <0x5a0c>;
  592. ctrl-clock-ena-reg = <0x318>;
  593. clocks = <&refclk 0>;
  594. queue-count = <16>;
  595. phy-count = <8>;
  596. dma-coherent;
  597. interrupt-parent = <&mbigen_sas1>;
  598. interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
  599. <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
  600. <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
  601. <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
  602. <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
  603. <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
  604. <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
  605. <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
  606. <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
  607. <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
  608. <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
  609. <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
  610. <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
  611. <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
  612. <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
  613. <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
  614. <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
  615. <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
  616. <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
  617. <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
  618. <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
  619. <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
  620. <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
  621. <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
  622. <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
  623. <605 1>,<606 1>,<607 1>;
  624. status = "disabled";
  625. };
  626. sas2: sas@a3000000 {
  627. compatible = "hisilicon,hip06-sas-v2";
  628. reg = <0 0xa3000000 0 0x10000>;
  629. sas-addr = [50 01 88 20 16 00 00 00];
  630. hisilicon,sas-syscon = <&pcie_subctl>;
  631. ctrl-reset-reg = <0xae0>;
  632. ctrl-reset-sts-reg = <0x5a70>;
  633. ctrl-clock-ena-reg = <0x3a8>;
  634. clocks = <&refclk 0>;
  635. queue-count = <16>;
  636. phy-count = <9>;
  637. dma-coherent;
  638. interrupt-parent = <&mbigen_sas2>;
  639. interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
  640. <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
  641. <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
  642. <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
  643. <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
  644. <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
  645. <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
  646. <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
  647. <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
  648. <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
  649. <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
  650. <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
  651. <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
  652. <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
  653. <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
  654. <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
  655. <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
  656. <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
  657. <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
  658. <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
  659. <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
  660. <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
  661. <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
  662. <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
  663. <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
  664. <637 1>,<638 1>,<639 1>;
  665. status = "disabled";
  666. };
  667. pcie0: pcie@a0090000 {
  668. compatible = "hisilicon,hip06-pcie-ecam";
  669. reg = <0 0xb0000000 0 0x2000000>,
  670. <0 0xa0090000 0 0x10000>;
  671. bus-range = <0 31>;
  672. msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
  673. msi-map-mask = <0xffff>;
  674. #address-cells = <3>;
  675. #size-cells = <2>;
  676. device_type = "pci";
  677. dma-coherent;
  678. ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0
  679. 0x5ff0000 0x01000000 0 0 0 0xb7ff0000
  680. 0 0x10000>;
  681. #interrupt-cells = <1>;
  682. interrupt-map-mask = <0xf800 0 0 7>;
  683. interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
  684. 0x0 0 0 2 &mbigen_pcie0 650 4
  685. 0x0 0 0 3 &mbigen_pcie0 650 4
  686. 0x0 0 0 4 &mbigen_pcie0 650 4>;
  687. status = "disabled";
  688. };
  689. };
  690. };