regs-adc.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2004 Shannon Holland <holland@loser.net>
  4. *
  5. * S3C2410 ADC registers
  6. */
  7. #ifndef __ASM_ARCH_REGS_ADC_H
  8. #define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
  9. #define S3C2410_ADCREG(x) (x)
  10. #define S3C2410_ADCCON S3C2410_ADCREG(0x00)
  11. #define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
  12. #define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
  13. #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
  14. #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
  15. #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
  16. #define S3C2443_ADCMUX S3C2410_ADCREG(0x18)
  17. #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
  18. #define S5P_ADCMUX S3C2410_ADCREG(0x1C)
  19. #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
  20. /* ADCCON Register Bits */
  21. #define S3C64XX_ADCCON_RESSEL (1<<16)
  22. #define S3C2410_ADCCON_ECFLG (1<<15)
  23. #define S3C2410_ADCCON_PRSCEN (1<<14)
  24. #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
  25. #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
  26. #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
  27. #define S3C2410_ADCCON_MUXMASK (0x7<<3)
  28. #define S3C2416_ADCCON_RESSEL (1 << 3)
  29. #define S3C2410_ADCCON_STDBM (1<<2)
  30. #define S3C2410_ADCCON_READ_START (1<<1)
  31. #define S3C2410_ADCCON_ENABLE_START (1<<0)
  32. #define S3C2410_ADCCON_STARTMASK (0x3<<0)
  33. /* ADCTSC Register Bits */
  34. #define S3C2443_ADCTSC_UD_SEN (1 << 8)
  35. #define S3C2410_ADCTSC_YM_SEN (1<<7)
  36. #define S3C2410_ADCTSC_YP_SEN (1<<6)
  37. #define S3C2410_ADCTSC_XM_SEN (1<<5)
  38. #define S3C2410_ADCTSC_XP_SEN (1<<4)
  39. #define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
  40. #define S3C2410_ADCTSC_AUTO_PST (1<<2)
  41. #define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
  42. /* ADCDAT0 Bits */
  43. #define S3C2410_ADCDAT0_UPDOWN (1<<15)
  44. #define S3C2410_ADCDAT0_AUTO_PST (1<<14)
  45. #define S3C2410_ADCDAT0_XY_PST (0x3<<12)
  46. #define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
  47. /* ADCDAT1 Bits */
  48. #define S3C2410_ADCDAT1_UPDOWN (1<<15)
  49. #define S3C2410_ADCDAT1_AUTO_PST (1<<14)
  50. #define S3C2410_ADCDAT1_XY_PST (0x3<<12)
  51. #define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
  52. #endif /* __ASM_ARCH_REGS_ADC_H */