saar.c 13 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/saar.c
  3. *
  4. * Support for the Marvell PXA930 Handheld Platform (aka SAAR)
  5. *
  6. * Copyright (C) 2007-2008 Marvell International Ltd.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * publishhed by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/clk.h>
  18. #include <linux/gpio.h>
  19. #include <linux/delay.h>
  20. #include <linux/fb.h>
  21. #include <linux/i2c.h>
  22. #include <linux/platform_data/i2c-pxa.h>
  23. #include <linux/smc91x.h>
  24. #include <linux/mfd/da903x.h>
  25. #include <linux/mtd/mtd.h>
  26. #include <linux/mtd/partitions.h>
  27. #include <linux/mtd/onenand.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/mach/arch.h>
  30. #include <asm/mach/flash.h>
  31. #include "pxa930.h"
  32. #include <linux/platform_data/video-pxafb.h>
  33. #include "devices.h"
  34. #include "generic.h"
  35. #define GPIO_LCD_RESET (16)
  36. /* SAAR MFP configurations */
  37. static mfp_cfg_t saar_mfp_cfg[] __initdata = {
  38. /* LCD */
  39. GPIO23_LCD_DD0,
  40. GPIO24_LCD_DD1,
  41. GPIO25_LCD_DD2,
  42. GPIO26_LCD_DD3,
  43. GPIO27_LCD_DD4,
  44. GPIO28_LCD_DD5,
  45. GPIO29_LCD_DD6,
  46. GPIO44_LCD_DD7,
  47. GPIO21_LCD_CS,
  48. GPIO22_LCD_VSYNC,
  49. GPIO17_LCD_FCLK_RD,
  50. GPIO18_LCD_LCLK_A0,
  51. GPIO19_LCD_PCLK_WR,
  52. GPIO16_GPIO, /* LCD reset */
  53. /* Ethernet */
  54. DF_nCS1_nCS3,
  55. GPIO97_GPIO,
  56. /* DFI */
  57. DF_INT_RnB_ND_INT_RnB,
  58. DF_nRE_nOE_ND_nRE,
  59. DF_nWE_ND_nWE,
  60. DF_CLE_nOE_ND_CLE,
  61. DF_nADV1_ALE_ND_ALE,
  62. DF_nADV2_ALE_nCS3,
  63. DF_nCS0_ND_nCS0,
  64. DF_IO0_ND_IO0,
  65. DF_IO1_ND_IO1,
  66. DF_IO2_ND_IO2,
  67. DF_IO3_ND_IO3,
  68. DF_IO4_ND_IO4,
  69. DF_IO5_ND_IO5,
  70. DF_IO6_ND_IO6,
  71. DF_IO7_ND_IO7,
  72. DF_IO8_ND_IO8,
  73. DF_IO9_ND_IO9,
  74. DF_IO10_ND_IO10,
  75. DF_IO11_ND_IO11,
  76. DF_IO12_ND_IO12,
  77. DF_IO13_ND_IO13,
  78. DF_IO14_ND_IO14,
  79. DF_IO15_ND_IO15,
  80. };
  81. #define SAAR_ETH_PHYS (0x14000000)
  82. static struct resource smc91x_resources[] = {
  83. [0] = {
  84. .start = (SAAR_ETH_PHYS + 0x300),
  85. .end = (SAAR_ETH_PHYS + 0xfffff),
  86. .flags = IORESOURCE_MEM,
  87. },
  88. [1] = {
  89. .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
  90. .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
  91. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  92. }
  93. };
  94. static struct smc91x_platdata saar_smc91x_info = {
  95. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
  96. };
  97. static struct platform_device smc91x_device = {
  98. .name = "smc91x",
  99. .id = 0,
  100. .num_resources = ARRAY_SIZE(smc91x_resources),
  101. .resource = smc91x_resources,
  102. .dev = {
  103. .platform_data = &saar_smc91x_info,
  104. },
  105. };
  106. #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
  107. static uint16_t lcd_power_on[] = {
  108. /* single frame */
  109. SMART_CMD_NOOP,
  110. SMART_CMD(0x00),
  111. SMART_DELAY(0),
  112. SMART_CMD_NOOP,
  113. SMART_CMD(0x00),
  114. SMART_DELAY(0),
  115. SMART_CMD_NOOP,
  116. SMART_CMD(0x00),
  117. SMART_DELAY(0),
  118. SMART_CMD_NOOP,
  119. SMART_CMD(0x00),
  120. SMART_DELAY(10),
  121. /* calibration control */
  122. SMART_CMD(0x00),
  123. SMART_CMD(0xA4),
  124. SMART_DAT(0x80),
  125. SMART_DAT(0x01),
  126. SMART_DELAY(150),
  127. /*Power-On Init sequence*/
  128. SMART_CMD(0x00), /* output ctrl */
  129. SMART_CMD(0x01),
  130. SMART_DAT(0x01),
  131. SMART_DAT(0x00),
  132. SMART_CMD(0x00), /* wave ctrl */
  133. SMART_CMD(0x02),
  134. SMART_DAT(0x07),
  135. SMART_DAT(0x00),
  136. SMART_CMD(0x00),
  137. SMART_CMD(0x03), /* entry mode */
  138. SMART_DAT(0xD0),
  139. SMART_DAT(0x30),
  140. SMART_CMD(0x00),
  141. SMART_CMD(0x08), /* display ctrl 2 */
  142. SMART_DAT(0x08),
  143. SMART_DAT(0x08),
  144. SMART_CMD(0x00),
  145. SMART_CMD(0x09), /* display ctrl 3 */
  146. SMART_DAT(0x04),
  147. SMART_DAT(0x2F),
  148. SMART_CMD(0x00),
  149. SMART_CMD(0x0A), /* display ctrl 4 */
  150. SMART_DAT(0x00),
  151. SMART_DAT(0x08),
  152. SMART_CMD(0x00),
  153. SMART_CMD(0x0D), /* Frame Marker position */
  154. SMART_DAT(0x00),
  155. SMART_DAT(0x08),
  156. SMART_CMD(0x00),
  157. SMART_CMD(0x60), /* Driver output control */
  158. SMART_DAT(0x27),
  159. SMART_DAT(0x00),
  160. SMART_CMD(0x00),
  161. SMART_CMD(0x61), /* Base image display control */
  162. SMART_DAT(0x00),
  163. SMART_DAT(0x01),
  164. SMART_CMD(0x00),
  165. SMART_CMD(0x30), /* Y settings 30h-3Dh */
  166. SMART_DAT(0x07),
  167. SMART_DAT(0x07),
  168. SMART_CMD(0x00),
  169. SMART_CMD(0x31),
  170. SMART_DAT(0x00),
  171. SMART_DAT(0x07),
  172. SMART_CMD(0x00),
  173. SMART_CMD(0x32), /* Timing(3), ASW HOLD=0.5CLK */
  174. SMART_DAT(0x04),
  175. SMART_DAT(0x00),
  176. SMART_CMD(0x00),
  177. SMART_CMD(0x33), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
  178. SMART_DAT(0x03),
  179. SMART_DAT(0x03),
  180. SMART_CMD(0x00),
  181. SMART_CMD(0x34),
  182. SMART_DAT(0x00),
  183. SMART_DAT(0x00),
  184. SMART_CMD(0x00),
  185. SMART_CMD(0x35),
  186. SMART_DAT(0x02),
  187. SMART_DAT(0x05),
  188. SMART_CMD(0x00),
  189. SMART_CMD(0x36),
  190. SMART_DAT(0x1F),
  191. SMART_DAT(0x1F),
  192. SMART_CMD(0x00),
  193. SMART_CMD(0x37),
  194. SMART_DAT(0x07),
  195. SMART_DAT(0x07),
  196. SMART_CMD(0x00),
  197. SMART_CMD(0x38),
  198. SMART_DAT(0x00),
  199. SMART_DAT(0x07),
  200. SMART_CMD(0x00),
  201. SMART_CMD(0x39),
  202. SMART_DAT(0x04),
  203. SMART_DAT(0x00),
  204. SMART_CMD(0x00),
  205. SMART_CMD(0x3A),
  206. SMART_DAT(0x03),
  207. SMART_DAT(0x03),
  208. SMART_CMD(0x00),
  209. SMART_CMD(0x3B),
  210. SMART_DAT(0x00),
  211. SMART_DAT(0x00),
  212. SMART_CMD(0x00),
  213. SMART_CMD(0x3C),
  214. SMART_DAT(0x02),
  215. SMART_DAT(0x05),
  216. SMART_CMD(0x00),
  217. SMART_CMD(0x3D),
  218. SMART_DAT(0x1F),
  219. SMART_DAT(0x1F),
  220. SMART_CMD(0x00), /* Display control 1 */
  221. SMART_CMD(0x07),
  222. SMART_DAT(0x00),
  223. SMART_DAT(0x01),
  224. SMART_CMD(0x00), /* Power control 5 */
  225. SMART_CMD(0x17),
  226. SMART_DAT(0x00),
  227. SMART_DAT(0x01),
  228. SMART_CMD(0x00), /* Power control 1 */
  229. SMART_CMD(0x10),
  230. SMART_DAT(0x10),
  231. SMART_DAT(0xB0),
  232. SMART_CMD(0x00), /* Power control 2 */
  233. SMART_CMD(0x11),
  234. SMART_DAT(0x01),
  235. SMART_DAT(0x30),
  236. SMART_CMD(0x00), /* Power control 3 */
  237. SMART_CMD(0x12),
  238. SMART_DAT(0x01),
  239. SMART_DAT(0x9E),
  240. SMART_CMD(0x00), /* Power control 4 */
  241. SMART_CMD(0x13),
  242. SMART_DAT(0x17),
  243. SMART_DAT(0x00),
  244. SMART_CMD(0x00), /* Power control 3 */
  245. SMART_CMD(0x12),
  246. SMART_DAT(0x01),
  247. SMART_DAT(0xBE),
  248. SMART_DELAY(100),
  249. /* display mode : 240*320 */
  250. SMART_CMD(0x00), /* RAM address set(H) 0*/
  251. SMART_CMD(0x20),
  252. SMART_DAT(0x00),
  253. SMART_DAT(0x00),
  254. SMART_CMD(0x00), /* RAM address set(V) 4*/
  255. SMART_CMD(0x21),
  256. SMART_DAT(0x00),
  257. SMART_DAT(0x00),
  258. SMART_CMD(0x00), /* Start of Window RAM address set(H) 8*/
  259. SMART_CMD(0x50),
  260. SMART_DAT(0x00),
  261. SMART_DAT(0x00),
  262. SMART_CMD(0x00), /* End of Window RAM address set(H) 12*/
  263. SMART_CMD(0x51),
  264. SMART_DAT(0x00),
  265. SMART_DAT(0xEF),
  266. SMART_CMD(0x00), /* Start of Window RAM address set(V) 16*/
  267. SMART_CMD(0x52),
  268. SMART_DAT(0x00),
  269. SMART_DAT(0x00),
  270. SMART_CMD(0x00), /* End of Window RAM address set(V) 20*/
  271. SMART_CMD(0x53),
  272. SMART_DAT(0x01),
  273. SMART_DAT(0x3F),
  274. SMART_CMD(0x00), /* Panel interface control 1 */
  275. SMART_CMD(0x90),
  276. SMART_DAT(0x00),
  277. SMART_DAT(0x1A),
  278. SMART_CMD(0x00), /* Panel interface control 2 */
  279. SMART_CMD(0x92),
  280. SMART_DAT(0x04),
  281. SMART_DAT(0x00),
  282. SMART_CMD(0x00), /* Panel interface control 3 */
  283. SMART_CMD(0x93),
  284. SMART_DAT(0x00),
  285. SMART_DAT(0x05),
  286. SMART_DELAY(20),
  287. };
  288. static uint16_t lcd_panel_on[] = {
  289. SMART_CMD(0x00),
  290. SMART_CMD(0x07),
  291. SMART_DAT(0x00),
  292. SMART_DAT(0x21),
  293. SMART_DELAY(1),
  294. SMART_CMD(0x00),
  295. SMART_CMD(0x07),
  296. SMART_DAT(0x00),
  297. SMART_DAT(0x61),
  298. SMART_DELAY(100),
  299. SMART_CMD(0x00),
  300. SMART_CMD(0x07),
  301. SMART_DAT(0x01),
  302. SMART_DAT(0x73),
  303. SMART_DELAY(1),
  304. };
  305. static uint16_t lcd_panel_off[] = {
  306. SMART_CMD(0x00),
  307. SMART_CMD(0x07),
  308. SMART_DAT(0x00),
  309. SMART_DAT(0x72),
  310. SMART_DELAY(40),
  311. SMART_CMD(0x00),
  312. SMART_CMD(0x07),
  313. SMART_DAT(0x00),
  314. SMART_DAT(0x01),
  315. SMART_DELAY(1),
  316. SMART_CMD(0x00),
  317. SMART_CMD(0x07),
  318. SMART_DAT(0x00),
  319. SMART_DAT(0x00),
  320. SMART_DELAY(1),
  321. };
  322. static uint16_t lcd_power_off[] = {
  323. SMART_CMD(0x00),
  324. SMART_CMD(0x10),
  325. SMART_DAT(0x00),
  326. SMART_DAT(0x80),
  327. SMART_CMD(0x00),
  328. SMART_CMD(0x11),
  329. SMART_DAT(0x01),
  330. SMART_DAT(0x60),
  331. SMART_CMD(0x00),
  332. SMART_CMD(0x12),
  333. SMART_DAT(0x01),
  334. SMART_DAT(0xAE),
  335. SMART_DELAY(40),
  336. SMART_CMD(0x00),
  337. SMART_CMD(0x10),
  338. SMART_DAT(0x00),
  339. SMART_DAT(0x00),
  340. };
  341. static uint16_t update_framedata[] = {
  342. /* set display ram: 240*320 */
  343. SMART_CMD(0x00), /* RAM address set(H) 0*/
  344. SMART_CMD(0x20),
  345. SMART_DAT(0x00),
  346. SMART_DAT(0x00),
  347. SMART_CMD(0x00), /* RAM address set(V) 4*/
  348. SMART_CMD(0x21),
  349. SMART_DAT(0x00),
  350. SMART_DAT(0x00),
  351. SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */
  352. SMART_CMD(0x50),
  353. SMART_DAT(0x00),
  354. SMART_DAT(0x00),
  355. SMART_CMD(0x00), /* End of Window RAM address set(H) 12 */
  356. SMART_CMD(0x51),
  357. SMART_DAT(0x00),
  358. SMART_DAT(0xEF),
  359. SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */
  360. SMART_CMD(0x52),
  361. SMART_DAT(0x00),
  362. SMART_DAT(0x00),
  363. SMART_CMD(0x00), /* End of Window RAM address set(V) 20 */
  364. SMART_CMD(0x53),
  365. SMART_DAT(0x01),
  366. SMART_DAT(0x3F),
  367. /* wait for vsync cmd before transferring frame data */
  368. SMART_CMD_WAIT_FOR_VSYNC,
  369. /* write ram */
  370. SMART_CMD(0x00),
  371. SMART_CMD(0x22),
  372. /* write frame data */
  373. SMART_CMD_WRITE_FRAME,
  374. };
  375. static void ltm022a97a_lcd_power(int on, struct fb_var_screeninfo *var)
  376. {
  377. static int pin_requested = 0;
  378. struct fb_info *info = container_of(var, struct fb_info, var);
  379. int err;
  380. if (!pin_requested) {
  381. err = gpio_request(GPIO_LCD_RESET, "lcd reset");
  382. if (err) {
  383. pr_err("failed to request gpio for LCD reset\n");
  384. return;
  385. }
  386. gpio_direction_output(GPIO_LCD_RESET, 0);
  387. pin_requested = 1;
  388. }
  389. if (on) {
  390. gpio_set_value(GPIO_LCD_RESET, 0); msleep(100);
  391. gpio_set_value(GPIO_LCD_RESET, 1); msleep(10);
  392. pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_on));
  393. pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_on));
  394. } else {
  395. pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_off));
  396. pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_off));
  397. }
  398. err = pxafb_smart_flush(info);
  399. if (err)
  400. pr_err("%s: timed out\n", __func__);
  401. }
  402. static void ltm022a97a_update(struct fb_info *info)
  403. {
  404. pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
  405. pxafb_smart_flush(info);
  406. }
  407. static struct pxafb_mode_info toshiba_ltm022a97a_modes[] = {
  408. [0] = {
  409. .xres = 240,
  410. .yres = 320,
  411. .bpp = 16,
  412. .a0csrd_set_hld = 30,
  413. .a0cswr_set_hld = 30,
  414. .wr_pulse_width = 30,
  415. .rd_pulse_width = 30,
  416. .op_hold_time = 30,
  417. .cmd_inh_time = 60,
  418. /* L_LCLK_A0 and L_LCLK_RD active low */
  419. .sync = FB_SYNC_HOR_HIGH_ACT |
  420. FB_SYNC_VERT_HIGH_ACT,
  421. },
  422. };
  423. static struct pxafb_mach_info saar_lcd_info = {
  424. .modes = toshiba_ltm022a97a_modes,
  425. .num_modes = 1,
  426. .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
  427. .pxafb_lcd_power = ltm022a97a_lcd_power,
  428. .smart_update = ltm022a97a_update,
  429. };
  430. static void __init saar_init_lcd(void)
  431. {
  432. pxa_set_fb_info(NULL, &saar_lcd_info);
  433. }
  434. #else
  435. static inline void saar_init_lcd(void) {}
  436. #endif
  437. #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
  438. static struct da9034_backlight_pdata saar_da9034_backlight = {
  439. .output_current = 4, /* 4mA */
  440. };
  441. static struct da903x_subdev_info saar_da9034_subdevs[] = {
  442. [0] = {
  443. .name = "da903x-backlight",
  444. .id = DA9034_ID_WLED,
  445. .platform_data = &saar_da9034_backlight,
  446. },
  447. };
  448. static struct da903x_platform_data saar_da9034_info = {
  449. .num_subdevs = ARRAY_SIZE(saar_da9034_subdevs),
  450. .subdevs = saar_da9034_subdevs,
  451. };
  452. static struct i2c_board_info saar_i2c_info[] = {
  453. [0] = {
  454. .type = "da9034",
  455. .addr = 0x34,
  456. .platform_data = &saar_da9034_info,
  457. .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
  458. },
  459. };
  460. static void __init saar_init_i2c(void)
  461. {
  462. pxa_set_i2c_info(NULL);
  463. i2c_register_board_info(0, ARRAY_AND_SIZE(saar_i2c_info));
  464. }
  465. #else
  466. static inline void saar_init_i2c(void) {}
  467. #endif
  468. #if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE)
  469. static struct mtd_partition saar_onenand_partitions[] = {
  470. {
  471. .name = "bootloader",
  472. .offset = 0,
  473. .size = SZ_1M,
  474. .mask_flags = MTD_WRITEABLE,
  475. }, {
  476. .name = "reserved",
  477. .offset = MTDPART_OFS_APPEND,
  478. .size = SZ_128K,
  479. .mask_flags = MTD_WRITEABLE,
  480. }, {
  481. .name = "reserved",
  482. .offset = MTDPART_OFS_APPEND,
  483. .size = SZ_8M,
  484. .mask_flags = MTD_WRITEABLE,
  485. }, {
  486. .name = "kernel",
  487. .offset = MTDPART_OFS_APPEND,
  488. .size = (SZ_2M + SZ_1M),
  489. .mask_flags = 0,
  490. }, {
  491. .name = "filesystem",
  492. .offset = MTDPART_OFS_APPEND,
  493. .size = SZ_32M + SZ_16M,
  494. .mask_flags = 0,
  495. }
  496. };
  497. static struct onenand_platform_data saar_onenand_info = {
  498. .parts = saar_onenand_partitions,
  499. .nr_parts = ARRAY_SIZE(saar_onenand_partitions),
  500. };
  501. #define SMC_CS0_PHYS_BASE (0x10000000)
  502. static struct resource saar_resource_onenand[] = {
  503. [0] = {
  504. .start = SMC_CS0_PHYS_BASE,
  505. .end = SMC_CS0_PHYS_BASE + SZ_1M,
  506. .flags = IORESOURCE_MEM,
  507. },
  508. };
  509. static struct platform_device saar_device_onenand = {
  510. .name = "onenand-flash",
  511. .id = -1,
  512. .dev = {
  513. .platform_data = &saar_onenand_info,
  514. },
  515. .resource = saar_resource_onenand,
  516. .num_resources = ARRAY_SIZE(saar_resource_onenand),
  517. };
  518. static void __init saar_init_onenand(void)
  519. {
  520. platform_device_register(&saar_device_onenand);
  521. }
  522. #else
  523. static void __init saar_init_onenand(void) {}
  524. #endif
  525. static void __init saar_init(void)
  526. {
  527. /* initialize MFP configurations */
  528. pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg));
  529. pxa_set_ffuart_info(NULL);
  530. pxa_set_btuart_info(NULL);
  531. pxa_set_stuart_info(NULL);
  532. platform_device_register(&smc91x_device);
  533. saar_init_onenand();
  534. saar_init_i2c();
  535. saar_init_lcd();
  536. }
  537. MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
  538. /* Maintainer: Eric Miao <eric.miao@marvell.com> */
  539. .atag_offset = 0x100,
  540. .map_io = pxa3xx_map_io,
  541. .nr_irqs = PXA_NR_IRQS,
  542. .init_irq = pxa3xx_init_irq,
  543. .handle_irq = pxa3xx_handle_irq,
  544. .init_time = pxa_timer_init,
  545. .init_machine = saar_init,
  546. .restart = pxa_restart,
  547. MACHINE_END