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dove.h

dove.h 6.9 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-dove/include/mach/dove.h
    3. 

  3.  *
    4. 

  4.  * Generic definitions for Marvell Dove 88AP510 SoC
    5. 

  5.  *
    6. 

  6.  * This file is licensed under the terms of the GNU General Public
    7. 

  7.  * License version 2.  This program is licensed "as is" without any
    8. 

  8.  * warranty of any kind, whether express or implied.
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __ASM_ARCH_DOVE_H
    12. 

  12. #define __ASM_ARCH_DOVE_H
    13. 

  13. 

  14. #include <mach/irqs.h>
    15. 

  15. 

  16. /*
    17. 

  17.  * Marvell Dove address maps.
    18. 

  18.  *
    19. 

  19.  * phys		virt		size
    20. 

  20.  * c8000000	fdb00000	1M	Cryptographic SRAM
    21. 

  21.  * e0000000	@runtime	128M	PCIe-0 Memory space
    22. 

  22.  * e8000000	@runtime	128M	PCIe-1 Memory space
    23. 

  23.  * f1000000	fde00000	8M	on-chip south-bridge registers
    24. 

  24.  * f1800000	fe600000	8M	on-chip north-bridge registers
    25. 

  25.  * f2000000	fee00000	1M	PCIe-0 I/O space
    26. 

  26.  * f2100000	fef00000	1M	PCIe-1 I/O space
    27. 

  27.  */
    28. 

  28. 

  29. #define DOVE_CESA_PHYS_BASE		0xc8000000
    30. 

  30. #define DOVE_CESA_VIRT_BASE		IOMEM(0xfdb00000)
    31. 

  31. #define DOVE_CESA_SIZE			SZ_1M
    32. 

  32. 

  33. #define DOVE_PCIE0_MEM_PHYS_BASE	0xe0000000
    34. 

  34. #define DOVE_PCIE0_MEM_SIZE		SZ_128M
    35. 

  35. 

  36. #define DOVE_PCIE1_MEM_PHYS_BASE	0xe8000000
    37. 

  37. #define DOVE_PCIE1_MEM_SIZE		SZ_128M
    38. 

  38. 

  39. #define DOVE_BOOTROM_PHYS_BASE		0xf8000000
    40. 

  40. #define DOVE_BOOTROM_SIZE		SZ_128M
    41. 

  41. 

  42. #define DOVE_SCRATCHPAD_PHYS_BASE	0xf0000000
    43. 

  43. #define DOVE_SCRATCHPAD_VIRT_BASE	IOMEM(0xfdd00000)
    44. 

  44. #define DOVE_SCRATCHPAD_SIZE		SZ_1M
    45. 

  45. 

  46. #define DOVE_SB_REGS_PHYS_BASE		0xf1000000
    47. 

  47. #define DOVE_SB_REGS_VIRT_BASE		IOMEM(0xfde00000)
    48. 

  48. #define DOVE_SB_REGS_SIZE		SZ_8M
    49. 

  49. 

  50. #define DOVE_NB_REGS_PHYS_BASE		0xf1800000
    51. 

  51. #define DOVE_NB_REGS_VIRT_BASE		IOMEM(0xfe600000)
    52. 

  52. #define DOVE_NB_REGS_SIZE		SZ_8M
    53. 

  53. 

  54. #define DOVE_PCIE0_IO_PHYS_BASE		0xf2000000
    55. 

  55. #define DOVE_PCIE0_IO_BUS_BASE		0x00000000
    56. 

  56. #define DOVE_PCIE0_IO_SIZE		SZ_64K
    57. 

  57. 

  58. #define DOVE_PCIE1_IO_PHYS_BASE		0xf2100000
    59. 

  59. #define DOVE_PCIE1_IO_BUS_BASE		0x00010000
    60. 

  60. #define DOVE_PCIE1_IO_SIZE		SZ_64K
    61. 

  61. 

  62. /*
    63. 

  63.  * Dove Core Registers Map
    64. 

  64.  */
    65. 

  65. 

  66. /* SPI, I2C, UART */
    67. 

  67. #define DOVE_I2C_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x11000)
    68. 

  68. #define DOVE_UART0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12000)
    69. 

  69. #define DOVE_UART0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12000)
    70. 

  70. #define DOVE_UART1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12100)
    71. 

  71. #define DOVE_UART1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12100)
    72. 

  72. #define DOVE_UART2_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12200)
    73. 

  73. #define DOVE_UART2_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12200)
    74. 

  74. #define DOVE_UART3_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12300)
    75. 

  75. #define DOVE_UART3_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12300)
    76. 

  76. #define DOVE_SPI0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x10600)
    77. 

  77. #define DOVE_SPI1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x14600)
    78. 

  78. 

  79. /* North-South Bridge */
    80. 

  80. #define BRIDGE_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x20000)
    81. 

  81. #define BRIDGE_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x20000)
    82. 

  82. #define  BRIDGE_WINS_BASE       (BRIDGE_PHYS_BASE)
    83. 

  83. #define  BRIDGE_WINS_SZ         (0x80)
    84. 

  84. 

  85. /* Cryptographic Engine */
    86. 

  86. #define DOVE_CRYPT_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x30000)
    87. 

  87. 

  88. /* PCIe 0 */
    89. 

  89. #define DOVE_PCIE0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x40000)
    90. 

  90. 

  91. /* USB */
    92. 

  92. #define DOVE_USB0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x50000)
    93. 

  93. #define DOVE_USB1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x51000)
    94. 

  94. 

  95. /* XOR 0 Engine */
    96. 

  96. #define DOVE_XOR0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60800)
    97. 

  97. #define DOVE_XOR0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60800)
    98. 

  98. #define DOVE_XOR0_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60A00)
    99. 

  99. #define DOVE_XOR0_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60A00)
    100. 

  100. 

  101. /* XOR 1 Engine */
    102. 

  102. #define DOVE_XOR1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60900)
    103. 

  103. #define DOVE_XOR1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60900)
    104. 

  104. #define DOVE_XOR1_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60B00)
    105. 

  105. #define DOVE_XOR1_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60B00)
    106. 

  106. 

  107. /* Gigabit Ethernet */
    108. 

  108. #define DOVE_GE00_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x70000)
    109. 

  109. 

  110. /* PCIe 1 */
    111. 

  111. #define DOVE_PCIE1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x80000)
    112. 

  112. 

  113. /* CAFE */
    114. 

  114. #define DOVE_SDIO0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x92000)
    115. 

  115. #define DOVE_SDIO1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x90000)
    116. 

  116. #define DOVE_CAM_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x94000)
    117. 

  117. #define DOVE_CAFE_WIN_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x98000)
    118. 

  118. 

  119. /* SATA */
    120. 

  120. #define DOVE_SATA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xa0000)
    121. 

  121. 

  122. /* I2S/SPDIF */
    123. 

  123. #define DOVE_AUD0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xb0000)
    124. 

  124. #define DOVE_AUD1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xb4000)
    125. 

  125. 

  126. /* NAND Flash Controller */
    127. 

  127. #define DOVE_NFC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xc0000)
    128. 

  128. 

  129. /* MPP, GPIO, Reset Sampling */
    130. 

  130. #define DOVE_MPP_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0200)
    131. 

  131. #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
    132. 

  132. #define DOVE_RESET_SAMPLE_LO	(DOVE_MPP_VIRT_BASE + 0x014)
    133. 

  133. #define DOVE_RESET_SAMPLE_HI	(DOVE_MPP_VIRT_BASE + 0x018)
    134. 

  134. #define DOVE_GPIO_LO_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0400)
    135. 

  135. #define DOVE_GPIO_HI_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0420)
    136. 

  136. #define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
    137. 

  137. #define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe803c)
    138. 

  138. #define  DOVE_AU1_SPDIFO_GPIO_EN	(1 << 1)
    139. 

  139. #define  DOVE_NAND_GPIO_EN		(1 << 0)
    140. 

  140. #define DOVE_MPP_CTRL4_VIRT_BASE	(DOVE_GPIO_LO_VIRT_BASE + 0x40)
    141. 

  141. #define  DOVE_SPI_GPIO_SEL		(1 << 5)
    142. 

  142. #define  DOVE_UART1_GPIO_SEL		(1 << 4)
    143. 

  143. #define  DOVE_AU1_GPIO_SEL		(1 << 3)
    144. 

  144. #define  DOVE_CAM_GPIO_SEL		(1 << 2)
    145. 

  145. #define  DOVE_SD1_GPIO_SEL		(1 << 1)
    146. 

  146. #define  DOVE_SD0_GPIO_SEL		(1 << 0)
    147. 

  147. 

  148. /* Power Management */
    149. 

  149. #define DOVE_PMU_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0000)
    150. 

  150. #define DOVE_PMU_SIG_CTRL	(DOVE_PMU_VIRT_BASE + 0x802c)
    151. 

  151. 

  152. /* Real Time Clock */
    153. 

  153. #define DOVE_RTC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xd8500)
    154. 

  154. 

  155. /* AC97 */
    156. 

  156. #define DOVE_AC97_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xe0000)
    157. 

  157. #define DOVE_AC97_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe0000)
    158. 

  158. 

  159. /* Peripheral DMA */
    160. 

  160. #define DOVE_PDMA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xe4000)
    161. 

  161. #define DOVE_PDMA_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe4000)
    162. 

  162. 

  163. #define DOVE_GLOBAL_CONFIG_1	(DOVE_SB_REGS_VIRT_BASE + 0xe802C)
    164. 

  164. #define  DOVE_TWSI_ENABLE_OPTION1	(1 << 7)
    165. 

  165. #define DOVE_GLOBAL_CONFIG_2	(DOVE_SB_REGS_VIRT_BASE + 0xe8030)
    166. 

  166. #define  DOVE_TWSI_ENABLE_OPTION2	(1 << 20)
    167. 

  167. #define  DOVE_TWSI_ENABLE_OPTION3	(1 << 21)
    168. 

  168. #define  DOVE_TWSI_OPTION3_GPIO		(1 << 22)
    169. 

  169. #define DOVE_SSP_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xec000)
    170. 

  170. #define DOVE_SSP_CTRL_STATUS_1	(DOVE_SB_REGS_VIRT_BASE + 0xe8034)
    171. 

  171. #define  DOVE_SSP_ON_AU1		(1 << 0)
    172. 

  172. #define  DOVE_SSP_CLOCK_ENABLE		(1 << 1)
    173. 

  173. #define  DOVE_SSP_BPB_CLOCK_SRC_SSP	(1 << 11)
    174. 

  174. /* Memory Controller */
    175. 

  175. #define DOVE_MC_PHYS_BASE       (DOVE_NB_REGS_PHYS_BASE + 0x00000)
    176. 

  176. #define  DOVE_MC_WINS_BASE      (DOVE_MC_PHYS_BASE + 0x100)
    177. 

  177. #define  DOVE_MC_WINS_SZ        (0x8)
    178. 

  178. #define DOVE_MC_VIRT_BASE	(DOVE_NB_REGS_VIRT_BASE + 0x00000)
    179. 

  179. 

  180. /* LCD Controller */
    181. 

  181. #define DOVE_LCD_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x10000)
    182. 

  182. #define DOVE_LCD1_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x20000)
    183. 

  183. #define DOVE_LCD2_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x10000)
    184. 

  184. #define DOVE_LCD_DCON_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x30000)
    185. 

  185. 

  186. /* Graphic Engine */
    187. 

  187. #define DOVE_GPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x40000)
    188. 

  188. 

  189. /* Video Engine */
    190. 

  190. #define DOVE_VPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x400000)
    191. 

  191. 

  192. #endif
    193. 

  193.