head-common.S 5.8 KB

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  1. /*
  2. * linux/arch/arm/kernel/head-common.S
  3. *
  4. * Copyright (C) 1994-2002 Russell King
  5. * Copyright (c) 2003 ARM Limited
  6. * All Rights Reserved
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <asm/assembler.h>
  14. #define ATAG_CORE 0x54410001
  15. #define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
  16. #define ATAG_CORE_SIZE_EMPTY ((2*4) >> 2)
  17. #ifdef CONFIG_CPU_BIG_ENDIAN
  18. #define OF_DT_MAGIC 0xd00dfeed
  19. #else
  20. #define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
  21. #endif
  22. /*
  23. * Exception handling. Something went wrong and we can't proceed. We
  24. * ought to tell the user, but since we don't have any guarantee that
  25. * we're even running on the right architecture, we do virtually nothing.
  26. *
  27. * If CONFIG_DEBUG_LL is set we try to print out something about the error
  28. * and hope for the best (useful if bootloader fails to pass a proper
  29. * machine ID for example).
  30. */
  31. __HEAD
  32. /* Determine validity of the r2 atags pointer. The heuristic requires
  33. * that the pointer be aligned, in the first 16k of physical RAM and
  34. * that the ATAG_CORE marker is first and present. If CONFIG_OF_FLATTREE
  35. * is selected, then it will also accept a dtb pointer. Future revisions
  36. * of this function may be more lenient with the physical address and
  37. * may also be able to move the ATAGS block if necessary.
  38. *
  39. * Returns:
  40. * r2 either valid atags pointer, valid dtb pointer, or zero
  41. * r5, r6 corrupted
  42. */
  43. __vet_atags:
  44. tst r2, #0x3 @ aligned?
  45. bne 1f
  46. ldr r5, [r2, #0]
  47. #ifdef CONFIG_OF_FLATTREE
  48. ldr r6, =OF_DT_MAGIC @ is it a DTB?
  49. cmp r5, r6
  50. beq 2f
  51. #endif
  52. cmp r5, #ATAG_CORE_SIZE @ is first tag ATAG_CORE?
  53. cmpne r5, #ATAG_CORE_SIZE_EMPTY
  54. bne 1f
  55. ldr r5, [r2, #4]
  56. ldr r6, =ATAG_CORE
  57. cmp r5, r6
  58. bne 1f
  59. 2: ret lr @ atag/dtb pointer is ok
  60. 1: mov r2, #0
  61. ret lr
  62. ENDPROC(__vet_atags)
  63. /*
  64. * The following fragment of code is executed with the MMU on in MMU mode,
  65. * and uses absolute addresses; this is not position independent.
  66. *
  67. * r0 = cp#15 control register (exc_ret for M-class)
  68. * r1 = machine ID
  69. * r2 = atags/dtb pointer
  70. * r9 = processor ID
  71. */
  72. __INIT
  73. __mmap_switched:
  74. mov r7, r1
  75. mov r8, r2
  76. mov r10, r0
  77. adr r4, __mmap_switched_data
  78. mov fp, #0
  79. #if defined(CONFIG_XIP_DEFLATED_DATA)
  80. ARM( ldr sp, [r4], #4 )
  81. THUMB( ldr sp, [r4] )
  82. THUMB( add r4, #4 )
  83. bl __inflate_kernel_data @ decompress .data to RAM
  84. teq r0, #0
  85. bne __error
  86. #elif defined(CONFIG_XIP_KERNEL)
  87. ARM( ldmia r4!, {r0, r1, r2, sp} )
  88. THUMB( ldmia r4!, {r0, r1, r2, r3} )
  89. THUMB( mov sp, r3 )
  90. sub r2, r2, r1
  91. bl memcpy @ copy .data to RAM
  92. #endif
  93. ARM( ldmia r4!, {r0, r1, sp} )
  94. THUMB( ldmia r4!, {r0, r1, r3} )
  95. THUMB( mov sp, r3 )
  96. sub r2, r1, r0
  97. mov r1, #0
  98. bl memset @ clear .bss
  99. ldmia r4, {r0, r1, r2, r3}
  100. str r9, [r0] @ Save processor ID
  101. str r7, [r1] @ Save machine type
  102. str r8, [r2] @ Save atags pointer
  103. cmp r3, #0
  104. strne r10, [r3] @ Save control register values
  105. mov lr, #0
  106. b start_kernel
  107. ENDPROC(__mmap_switched)
  108. .align 2
  109. .type __mmap_switched_data, %object
  110. __mmap_switched_data:
  111. #ifdef CONFIG_XIP_KERNEL
  112. #ifndef CONFIG_XIP_DEFLATED_DATA
  113. .long _sdata @ r0
  114. .long __data_loc @ r1
  115. .long _edata_loc @ r2
  116. #endif
  117. .long __bss_stop @ sp (temporary stack in .bss)
  118. #endif
  119. .long __bss_start @ r0
  120. .long __bss_stop @ r1
  121. .long init_thread_union + THREAD_START_SP @ sp
  122. .long processor_id @ r0
  123. .long __machine_arch_type @ r1
  124. .long __atags_pointer @ r2
  125. #ifdef CONFIG_CPU_CP15
  126. .long cr_alignment @ r3
  127. #else
  128. M_CLASS(.long exc_ret) @ r3
  129. AR_CLASS(.long 0) @ r3
  130. #endif
  131. .size __mmap_switched_data, . - __mmap_switched_data
  132. __FINIT
  133. .text
  134. /*
  135. * This provides a C-API version of __lookup_processor_type
  136. */
  137. ENTRY(lookup_processor_type)
  138. stmfd sp!, {r4 - r6, r9, lr}
  139. mov r9, r0
  140. bl __lookup_processor_type
  141. mov r0, r5
  142. ldmfd sp!, {r4 - r6, r9, pc}
  143. ENDPROC(lookup_processor_type)
  144. /*
  145. * Read processor ID register (CP#15, CR0), and look up in the linker-built
  146. * supported processor list. Note that we can't use the absolute addresses
  147. * for the __proc_info lists since we aren't running with the MMU on
  148. * (and therefore, we are not in the correct address space). We have to
  149. * calculate the offset.
  150. *
  151. * r9 = cpuid
  152. * Returns:
  153. * r3, r4, r6 corrupted
  154. * r5 = proc_info pointer in physical address space
  155. * r9 = cpuid (preserved)
  156. */
  157. __lookup_processor_type:
  158. adr r3, __lookup_processor_type_data
  159. ldmia r3, {r4 - r6}
  160. sub r3, r3, r4 @ get offset between virt&phys
  161. add r5, r5, r3 @ convert virt addresses to
  162. add r6, r6, r3 @ physical address space
  163. 1: ldmia r5, {r3, r4} @ value, mask
  164. and r4, r4, r9 @ mask wanted bits
  165. teq r3, r4
  166. beq 2f
  167. add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
  168. cmp r5, r6
  169. blo 1b
  170. mov r5, #0 @ unknown processor
  171. 2: ret lr
  172. ENDPROC(__lookup_processor_type)
  173. /*
  174. * Look in <asm/procinfo.h> for information about the __proc_info structure.
  175. */
  176. .align 2
  177. .type __lookup_processor_type_data, %object
  178. __lookup_processor_type_data:
  179. .long .
  180. .long __proc_info_begin
  181. .long __proc_info_end
  182. .size __lookup_processor_type_data, . - __lookup_processor_type_data
  183. __error_lpae:
  184. #ifdef CONFIG_DEBUG_LL
  185. adr r0, str_lpae
  186. bl printascii
  187. b __error
  188. str_lpae: .asciz "\nError: Kernel with LPAE support, but CPU does not support LPAE.\n"
  189. #else
  190. b __error
  191. #endif
  192. .align
  193. ENDPROC(__error_lpae)
  194. __error_p:
  195. #ifdef CONFIG_DEBUG_LL
  196. adr r0, str_p1
  197. bl printascii
  198. mov r0, r9
  199. bl printhex8
  200. adr r0, str_p2
  201. bl printascii
  202. b __error
  203. str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
  204. str_p2: .asciz ").\n"
  205. .align
  206. #endif
  207. ENDPROC(__error_p)
  208. __error:
  209. #ifdef CONFIG_ARCH_RPC
  210. /*
  211. * Turn the screen red on a error - RiscPC only.
  212. */
  213. mov r0, #0x02000000
  214. mov r3, #0x11
  215. orr r3, r3, r3, lsl #8
  216. orr r3, r3, r3, lsl #16
  217. str r3, [r0], #4
  218. str r3, [r0], #4
  219. str r3, [r0], #4
  220. str r3, [r0], #4
  221. #endif
  222. 1: mov r0, r0
  223. b 1b
  224. ENDPROC(__error)