#31 Display CSI (D-PHY) routing

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opened 5 years ago by Houkime · 0 comments
Houkime commented 5 years ago

(It is a problem relevant to v2 prototype and not neccessarily relevant for a final product.)

CSI interface on the display connector consists of 3 differential pairs:

  • Forward data stream
  • Reverse data stream
  • Clock

CSI is used for a front camera of N900.
And technical requirements for such a bus are:

  • Max Frequency: 500MHz
  • Trace Impedance: 90Ω ±15% differential; 50Ω ±15% single ended
  • Max Intra-pair Skew: <1ps ≈150μm
  • Max Trace Length Skew between clock and data lanes: <10ps ≈1.5mm
  • Max Trace Length from Module Connector: 200mm

However, on the board, since on v2 BB-XM lies north from display connector, we have a situation depicted on the first attachment.

Grey line (on user drawing layer) is a rough draft of more or less the only viable way to route one of the differential pairs to BB-XM (they are neighbors on the connector).

However this means that one of the tracks of clock DP will have to go between holes of BB-XM connector, for which the gap is 0.1 mm and the extra skew introduced is around 1.3 mm.

Making the track exactly 0.1mm may be a bit dangerous. Though at the same time it is only a prototype and BB-XM won't be on the final design anyway. This part doesn't really need to be very reliable.

The other 2 pairs are a bit all over the map as subsequent screenshots show and i am not really sure how to correctly route this mess without breaking requirements above and if such a pinout was indeed neccessary or even intentional.

(It is a problem relevant to v2 prototype and not neccessarily relevant for a final product.) CSI interface on the display connector consists of 3 differential pairs: * Forward data stream * Reverse data stream * Clock CSI is used for a front camera of N900. And technical requirements for such a bus are: * **Max Frequency:** 500MHz * **Trace Impedance:** 90Ω ±15% differential; 50Ω ±15% single ended * **Max Intra-pair Skew:** <1ps ≈150μm * **Max Trace Length Skew between clock and data lanes:** <10ps ≈1.5mm * **Max Trace Length from Module Connector:** 200mm However, on the board, since on v2 BB-XM lies north from display connector, we have a situation depicted on the first attachment. Grey line (on user drawing layer) is a rough draft of more or less the only viable way to route one of the differential pairs to BB-XM (they are neighbors on the connector). However this means that one of the tracks of clock DP will have to go between holes of BB-XM connector, for which the gap is 0.1 mm and the extra skew introduced is around 1.3 mm. Making the track exactly 0.1mm may be a bit dangerous. Though at the same time it is only a prototype and BB-XM won't be on the final design anyway. This part doesn't really need to be very reliable. The other 2 pairs are a bit all over the map as subsequent screenshots show and i am not really sure how to correctly route this mess without breaking requirements above and if such a pinout was indeed neccessary or even intentional.
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