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Dave Woodfall
b66b94d5ec
academic/verilog: Updated for version 11.0.
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2 年之前 | |
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| .. | ||
| README | 9a5f389f29 academic/verilog: Fix README. | 3 年之前 |
| slack-desc | 610e8461bb various: Fix slack-desc formatting and comment nit picks. | 10 年之前 |
| verilog.SlackBuild | b66b94d5ec academic/verilog: Updated for version 11.0. | 2 年之前 |
| verilog.info | b66b94d5ec academic/verilog: Updated for version 11.0. | 2 年之前 |
README
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can
generate an intermediate form called vvp assembly. This intermediate
form is executed by the 'vvp' command. For synthesis, the compiler
generates netlists in the desired format.
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can
generate an intermediate form called vvp assembly. This intermediate
form is executed by the 'vvp' command. For synthesis, the compiler
generates netlists in the desired format.