slackbuilds/academic/DRAMsim3/slack-desc

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DRAMsim3: DRAMsim3 (DRAM simulator)
DRAMsim3:
DRAMsim3:  DRAMsim3 models the timing paramaters and memory controller behavior
DRAMsim3: for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5,
DRAMsim3: GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected
DRAMsim3: oriented model that includes a parameterized DRAM bank model, DRAM
DRAMsim3: controllers, command queues and system-level interfaces to interact
DRAMsim3: with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed
DRAMsim3: to be accurate, portable and parallel. 
DRAMsim3:
DRAMsim3: