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e161958bab
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12.0
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bedlam-name-fixes
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gitignore
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user/anddt/network/strongswan
user/anddt/network/umurmur
user/anddt/network/yt-dlp
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user/anddt/office/gnumeric
user/anddt/office/sigil
user/anddt/system/FontAwesome
user/anddt/system/conky
user/anddt/system/fakeroot
user/anddt/system/hplip-plugin
user/anddt/system/postgresql
user/anddt/system/testdisk
user/anddt/system/worker
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user/chris.willing/updates
user/dslackw/updates
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willysr
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Heinz Wiesinger
63daf9f79a
All: Support $PRINT_PACKAGE_NAME env var
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3 rokov pred | |
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| .. | ||
| files | fd672e3c99 development/gplcver: Added (open-source Verilog simulator). | 11 rokov pred |
| README | fd672e3c99 development/gplcver: Added (open-source Verilog simulator). | 11 rokov pred |
| gplcver.SlackBuild | 63daf9f79a All: Support $PRINT_PACKAGE_NAME env var | 3 rokov pred |
| gplcver.info | aeb81b74d9 development/gplcver: Updated homepage and download links | 7 rokov pred |
| slack-desc | bdc4af97af development/gplcver: Fix slack-desc. | 8 rokov pred |
README
Open-source interpreted Verilog simulator with a feature set and
performance similar to Verilog-XL.
Implements all IEEE 1364-1995 features along with some Verilog-2001
features.
Full support for Verilog PLIs.
performance similar to Verilog-XL.
Implements all IEEE 1364-1995 features along with some Verilog-2001
features.
Full support for Verilog PLIs.