Albero (Tree):
331a473f1a
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12.0
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Andrew Clemons
95f73609d5
academic/DRAMsim3: Fix github tarball handling.
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2 anni fa | |
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| .. | ||
| DRAMsim3.SlackBuild | 95f73609d5 academic/DRAMsim3: Fix github tarball handling. | 2 anni fa |
| DRAMsim3.info | 95f73609d5 academic/DRAMsim3: Fix github tarball handling. | 2 anni fa |
| README | 086f66bbdb academic/DRAMsim3: Added (DRAM simulator). | 2 anni fa |
| slack-desc | 086f66bbdb academic/DRAMsim3: Added (DRAM simulator). | 2 anni fa |
README
DRAMsim3 models the timing paramaters and memory controller behavior
for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5,
GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected
oriented model that includes a parameterized DRAM bank model, DRAM
controllers, command queues and system-level interfaces to interact
with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed
to be accurate, portable and parallel.
for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5,
GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected
oriented model that includes a parameterized DRAM bank model, DRAM
controllers, command queues and system-level interfaces to interact
with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed
to be accurate, portable and parallel.