Дрво:
1a80a96741
11.0
12.0
12.1
12.2
13.0
13.1
13.37
14.0
14.1
14.2
15.0
bedlam
bedlam-name-fixes
dive
erik
gitignore
libressl-gopher-test
master
misc-fixes
python-renames
rworkman
urchlay
user/aclemons/updates
user/anddt/development/acpica
user/anddt/development/glm
user/anddt/development/gnustep-base
user/anddt/development/gnustep-make
user/anddt/games/assaultcube-reloaded
user/anddt/games/doomseeker
user/anddt/games/prboom-plus
user/anddt/games/rocksndiamonds
user/anddt/games/rottexpr
user/anddt/games/srb2
user/anddt/graphics/blender
user/anddt/graphics/maim
user/anddt/ham/chirp
user/anddt/ham/hamlib
user/anddt/libraries/girara
user/anddt/libraries/goffice
user/anddt/libraries/gtksourceview4
user/anddt/libraries/imlib2
user/anddt/libraries/jsoncpp
user/anddt/libraries/libnova
user/anddt/libraries/libopenmpt
user/anddt/libraries/libtorrent
user/anddt/libraries/wxGTK3
user/anddt/libraries/xmlrpc-c
user/anddt/misc/discount
user/anddt/misc/slop
user/anddt/network/nethogs
user/anddt/network/putty
user/anddt/network/rclone
user/anddt/network/rtorrent
user/anddt/network/sshguard
user/anddt/network/strongswan
user/anddt/network/umurmur
user/anddt/network/yt-dlp
user/anddt/network/znc
user/anddt/office/gnumeric
user/anddt/office/sigil
user/anddt/system/FontAwesome
user/anddt/system/conky
user/anddt/system/fakeroot
user/anddt/system/hplip-plugin
user/anddt/system/postgresql
user/anddt/system/testdisk
user/anddt/system/worker
user/anddt/system/xen
user/anddt/system/zzzfm
user/belka/updates
user/chris.willing/updates
user/dslackw/updates
user/elyk/updates
user/kingbeowulf/updates
user/mario/updates
user/ponce/updates
user/pprkut/updates
willysr
wxWidgets-wip
GPG-KEY
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Dave Woodfall
b66b94d5ec
academic/verilog: Updated for version 11.0.
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| README | 9a5f389f29 academic/verilog: Fix README. | пре 4 година |
| slack-desc | 610e8461bb various: Fix slack-desc formatting and comment nit picks. | пре 11 година |
| verilog.SlackBuild | b66b94d5ec academic/verilog: Updated for version 11.0. | пре 2 година |
| verilog.info | b66b94d5ec academic/verilog: Updated for version 11.0. | пре 2 година |
README
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can
generate an intermediate form called vvp assembly. This intermediate
form is executed by the 'vvp' command. For synthesis, the compiler
generates netlists in the desired format.
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can
generate an intermediate form called vvp assembly. This intermediate
form is executed by the 'vvp' command. For synthesis, the compiler
generates netlists in the desired format.