system.c 1.9 KB

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  1. /*
  2. * Copyright (C) 1999 ARM Limited
  3. * Copyright (C) 2000 Deep Blue Solutions Ltd
  4. * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  5. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  6. * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <linux/err.h>
  22. #include <linux/delay.h>
  23. #include <mach/hardware.h>
  24. #include <mach/common.h>
  25. #include <asm/proc-fns.h>
  26. #include <asm/system.h>
  27. #include <asm/mach-types.h>
  28. static void __iomem *wdog_base;
  29. /*
  30. * Reset the system. It is called by machine_restart().
  31. */
  32. void arch_reset(char mode, const char *cmd)
  33. {
  34. unsigned int wcr_enable;
  35. #ifdef CONFIG_MACH_MX51_EFIKAMX
  36. if (machine_is_mx51_efikamx()) {
  37. mx51_efikamx_reset();
  38. return;
  39. }
  40. #endif
  41. if (cpu_is_mx1()) {
  42. wcr_enable = (1 << 0);
  43. } else {
  44. struct clk *clk;
  45. clk = clk_get_sys("imx2-wdt.0", NULL);
  46. if (!IS_ERR(clk))
  47. clk_enable(clk);
  48. wcr_enable = (1 << 2);
  49. }
  50. /* Assert SRS signal */
  51. __raw_writew(wcr_enable, wdog_base);
  52. /* wait for reset to assert... */
  53. mdelay(500);
  54. printk(KERN_ERR "Watchdog reset failed to assert reset\n");
  55. /* delay to allow the serial port to show the message */
  56. mdelay(50);
  57. /* we'll take a jump through zero as a poor second */
  58. cpu_reset(0);
  59. }
  60. void mxc_arch_reset_init(void __iomem *base)
  61. {
  62. wdog_base = base;
  63. }