irq.c 12 KB

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  1. /*
  2. * arch/arm/mach-lpc32xx/irq.c
  3. *
  4. * Author: Kevin Wells <kevin.wells@nxp.com>
  5. *
  6. * Copyright (C) 2010 NXP Semiconductors
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/types.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/irq.h>
  22. #include <linux/err.h>
  23. #include <linux/io.h>
  24. #include <mach/irqs.h>
  25. #include <mach/hardware.h>
  26. #include <mach/platform.h>
  27. #include "common.h"
  28. /*
  29. * Default value representing the Activation polarity of all internal
  30. * interrupt sources
  31. */
  32. #define MIC_APR_DEFAULT 0x3FF0EFE0
  33. #define SIC1_APR_DEFAULT 0xFBD27186
  34. #define SIC2_APR_DEFAULT 0x801810C0
  35. /*
  36. * Default value representing the Activation Type of all internal
  37. * interrupt sources. All are level sensitive.
  38. */
  39. #define MIC_ATR_DEFAULT 0x00000000
  40. #define SIC1_ATR_DEFAULT 0x00026000
  41. #define SIC2_ATR_DEFAULT 0x00000000
  42. struct lpc32xx_event_group_regs {
  43. void __iomem *enab_reg;
  44. void __iomem *edge_reg;
  45. void __iomem *maskstat_reg;
  46. void __iomem *rawstat_reg;
  47. };
  48. static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
  49. .enab_reg = LPC32XX_CLKPWR_INT_ER,
  50. .edge_reg = LPC32XX_CLKPWR_INT_AP,
  51. .maskstat_reg = LPC32XX_CLKPWR_INT_SR,
  52. .rawstat_reg = LPC32XX_CLKPWR_INT_RS,
  53. };
  54. static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
  55. .enab_reg = LPC32XX_CLKPWR_PIN_ER,
  56. .edge_reg = LPC32XX_CLKPWR_PIN_AP,
  57. .maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
  58. .rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
  59. };
  60. struct lpc32xx_event_info {
  61. const struct lpc32xx_event_group_regs *event_group;
  62. u32 mask;
  63. };
  64. /*
  65. * Maps an IRQ number to and event mask and register
  66. */
  67. static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
  68. [IRQ_LPC32XX_GPI_08] = {
  69. .event_group = &lpc32xx_event_pin_regs,
  70. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
  71. },
  72. [IRQ_LPC32XX_GPI_09] = {
  73. .event_group = &lpc32xx_event_pin_regs,
  74. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
  75. },
  76. [IRQ_LPC32XX_GPI_19] = {
  77. .event_group = &lpc32xx_event_pin_regs,
  78. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
  79. },
  80. [IRQ_LPC32XX_GPI_07] = {
  81. .event_group = &lpc32xx_event_pin_regs,
  82. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
  83. },
  84. [IRQ_LPC32XX_GPI_00] = {
  85. .event_group = &lpc32xx_event_pin_regs,
  86. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
  87. },
  88. [IRQ_LPC32XX_GPI_01] = {
  89. .event_group = &lpc32xx_event_pin_regs,
  90. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
  91. },
  92. [IRQ_LPC32XX_GPI_02] = {
  93. .event_group = &lpc32xx_event_pin_regs,
  94. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
  95. },
  96. [IRQ_LPC32XX_GPI_03] = {
  97. .event_group = &lpc32xx_event_pin_regs,
  98. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
  99. },
  100. [IRQ_LPC32XX_GPI_04] = {
  101. .event_group = &lpc32xx_event_pin_regs,
  102. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
  103. },
  104. [IRQ_LPC32XX_GPI_05] = {
  105. .event_group = &lpc32xx_event_pin_regs,
  106. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
  107. },
  108. [IRQ_LPC32XX_GPI_06] = {
  109. .event_group = &lpc32xx_event_pin_regs,
  110. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
  111. },
  112. [IRQ_LPC32XX_GPI_28] = {
  113. .event_group = &lpc32xx_event_pin_regs,
  114. .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
  115. },
  116. [IRQ_LPC32XX_GPIO_00] = {
  117. .event_group = &lpc32xx_event_int_regs,
  118. .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
  119. },
  120. [IRQ_LPC32XX_GPIO_01] = {
  121. .event_group = &lpc32xx_event_int_regs,
  122. .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
  123. },
  124. [IRQ_LPC32XX_GPIO_02] = {
  125. .event_group = &lpc32xx_event_int_regs,
  126. .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
  127. },
  128. [IRQ_LPC32XX_GPIO_03] = {
  129. .event_group = &lpc32xx_event_int_regs,
  130. .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
  131. },
  132. [IRQ_LPC32XX_GPIO_04] = {
  133. .event_group = &lpc32xx_event_int_regs,
  134. .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
  135. },
  136. [IRQ_LPC32XX_GPIO_05] = {
  137. .event_group = &lpc32xx_event_int_regs,
  138. .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
  139. },
  140. [IRQ_LPC32XX_KEY] = {
  141. .event_group = &lpc32xx_event_int_regs,
  142. .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
  143. },
  144. [IRQ_LPC32XX_USB_OTG_ATX] = {
  145. .event_group = &lpc32xx_event_int_regs,
  146. .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
  147. },
  148. [IRQ_LPC32XX_USB_HOST] = {
  149. .event_group = &lpc32xx_event_int_regs,
  150. .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
  151. },
  152. [IRQ_LPC32XX_RTC] = {
  153. .event_group = &lpc32xx_event_int_regs,
  154. .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
  155. },
  156. [IRQ_LPC32XX_MSTIMER] = {
  157. .event_group = &lpc32xx_event_int_regs,
  158. .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
  159. },
  160. [IRQ_LPC32XX_TS_AUX] = {
  161. .event_group = &lpc32xx_event_int_regs,
  162. .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
  163. },
  164. [IRQ_LPC32XX_TS_P] = {
  165. .event_group = &lpc32xx_event_int_regs,
  166. .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
  167. },
  168. [IRQ_LPC32XX_TS_IRQ] = {
  169. .event_group = &lpc32xx_event_int_regs,
  170. .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
  171. },
  172. };
  173. static void get_controller(unsigned int irq, unsigned int *base,
  174. unsigned int *irqbit)
  175. {
  176. if (irq < 32) {
  177. *base = LPC32XX_MIC_BASE;
  178. *irqbit = 1 << irq;
  179. } else if (irq < 64) {
  180. *base = LPC32XX_SIC1_BASE;
  181. *irqbit = 1 << (irq - 32);
  182. } else {
  183. *base = LPC32XX_SIC2_BASE;
  184. *irqbit = 1 << (irq - 64);
  185. }
  186. }
  187. static void lpc32xx_mask_irq(struct irq_data *d)
  188. {
  189. unsigned int reg, ctrl, mask;
  190. get_controller(d->irq, &ctrl, &mask);
  191. reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
  192. __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
  193. }
  194. static void lpc32xx_unmask_irq(struct irq_data *d)
  195. {
  196. unsigned int reg, ctrl, mask;
  197. get_controller(d->irq, &ctrl, &mask);
  198. reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
  199. __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
  200. }
  201. static void lpc32xx_ack_irq(struct irq_data *d)
  202. {
  203. unsigned int ctrl, mask;
  204. get_controller(d->irq, &ctrl, &mask);
  205. __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
  206. /* Also need to clear pending wake event */
  207. if (lpc32xx_events[d->irq].mask != 0)
  208. __raw_writel(lpc32xx_events[d->irq].mask,
  209. lpc32xx_events[d->irq].event_group->rawstat_reg);
  210. }
  211. static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
  212. int use_edge)
  213. {
  214. unsigned int reg, ctrl, mask;
  215. get_controller(irq, &ctrl, &mask);
  216. /* Activation level, high or low */
  217. reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
  218. if (use_high_level)
  219. reg |= mask;
  220. else
  221. reg &= ~mask;
  222. __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
  223. /* Activation type, edge or level */
  224. reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
  225. if (use_edge)
  226. reg |= mask;
  227. else
  228. reg &= ~mask;
  229. __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
  230. /* Use same polarity for the wake events */
  231. if (lpc32xx_events[irq].mask != 0) {
  232. reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
  233. if (use_high_level)
  234. reg |= lpc32xx_events[irq].mask;
  235. else
  236. reg &= ~lpc32xx_events[irq].mask;
  237. __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
  238. }
  239. }
  240. static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
  241. {
  242. switch (type) {
  243. case IRQ_TYPE_EDGE_RISING:
  244. /* Rising edge sensitive */
  245. __lpc32xx_set_irq_type(d->irq, 1, 1);
  246. break;
  247. case IRQ_TYPE_EDGE_FALLING:
  248. /* Falling edge sensitive */
  249. __lpc32xx_set_irq_type(d->irq, 0, 1);
  250. break;
  251. case IRQ_TYPE_LEVEL_LOW:
  252. /* Low level sensitive */
  253. __lpc32xx_set_irq_type(d->irq, 0, 0);
  254. break;
  255. case IRQ_TYPE_LEVEL_HIGH:
  256. /* High level sensitive */
  257. __lpc32xx_set_irq_type(d->irq, 1, 0);
  258. break;
  259. /* Other modes are not supported */
  260. default:
  261. return -EINVAL;
  262. }
  263. /* Ok to use the level handler for all types */
  264. irq_set_handler(d->irq, handle_level_irq);
  265. return 0;
  266. }
  267. static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
  268. {
  269. unsigned long eventreg;
  270. if (lpc32xx_events[d->irq].mask != 0) {
  271. eventreg = __raw_readl(lpc32xx_events[d->irq].
  272. event_group->enab_reg);
  273. if (state)
  274. eventreg |= lpc32xx_events[d->irq].mask;
  275. else {
  276. eventreg &= ~lpc32xx_events[d->irq].mask;
  277. /*
  278. * When disabling the wakeup, clear the latched
  279. * event
  280. */
  281. __raw_writel(lpc32xx_events[d->irq].mask,
  282. lpc32xx_events[d->irq].
  283. event_group->rawstat_reg);
  284. }
  285. __raw_writel(eventreg,
  286. lpc32xx_events[d->irq].event_group->enab_reg);
  287. return 0;
  288. }
  289. /* Clear event */
  290. __raw_writel(lpc32xx_events[d->irq].mask,
  291. lpc32xx_events[d->irq].event_group->rawstat_reg);
  292. return -ENODEV;
  293. }
  294. static void __init lpc32xx_set_default_mappings(unsigned int apr,
  295. unsigned int atr, unsigned int offset)
  296. {
  297. unsigned int i;
  298. /* Set activation levels for each interrupt */
  299. i = 0;
  300. while (i < 32) {
  301. __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
  302. ((atr >> i) & 0x1));
  303. i++;
  304. }
  305. }
  306. static struct irq_chip lpc32xx_irq_chip = {
  307. .irq_ack = lpc32xx_ack_irq,
  308. .irq_mask = lpc32xx_mask_irq,
  309. .irq_unmask = lpc32xx_unmask_irq,
  310. .irq_set_type = lpc32xx_set_irq_type,
  311. .irq_set_wake = lpc32xx_irq_wake
  312. };
  313. static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
  314. {
  315. unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
  316. while (ints != 0) {
  317. int irqno = fls(ints) - 1;
  318. ints &= ~(1 << irqno);
  319. generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
  320. }
  321. }
  322. static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
  323. {
  324. unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
  325. while (ints != 0) {
  326. int irqno = fls(ints) - 1;
  327. ints &= ~(1 << irqno);
  328. generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
  329. }
  330. }
  331. void __init lpc32xx_init_irq(void)
  332. {
  333. unsigned int i;
  334. /* Setup MIC */
  335. __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
  336. __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
  337. __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
  338. /* Setup SIC1 */
  339. __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
  340. __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
  341. __raw_writel(SIC1_ATR_DEFAULT,
  342. LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
  343. /* Setup SIC2 */
  344. __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
  345. __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
  346. __raw_writel(SIC2_ATR_DEFAULT,
  347. LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
  348. /* Configure supported IRQ's */
  349. for (i = 0; i < NR_IRQS; i++) {
  350. irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
  351. handle_level_irq);
  352. set_irq_flags(i, IRQF_VALID);
  353. }
  354. /* Set default mappings */
  355. lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
  356. lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
  357. lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
  358. /* mask all interrupts except SUBIRQ */
  359. __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
  360. __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
  361. __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
  362. /* MIC SUBIRQx interrupts will route handling to the chain handlers */
  363. irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
  364. irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
  365. /* Initially disable all wake events */
  366. __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
  367. __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
  368. __raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
  369. /*
  370. * Default wake activation polarities, all pin sources are low edge
  371. * triggered
  372. */
  373. __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
  374. LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
  375. LPC32XX_CLKPWR_INTSRC_RTC_BIT,
  376. LPC32XX_CLKPWR_INT_AP);
  377. __raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
  378. /* Clear latched wake event states */
  379. __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
  380. LPC32XX_CLKPWR_PIN_RS);
  381. __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
  382. LPC32XX_CLKPWR_INT_RS);
  383. }