irq.c 3.2 KB

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  1. /*
  2. * linux/arch/arm/mach-clps711x/irq.c
  3. *
  4. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/init.h>
  21. #include <linux/list.h>
  22. #include <linux/io.h>
  23. #include <asm/mach/irq.h>
  24. #include <mach/hardware.h>
  25. #include <asm/irq.h>
  26. #include <asm/hardware/clps7111.h>
  27. static void int1_mask(struct irq_data *d)
  28. {
  29. u32 intmr1;
  30. intmr1 = clps_readl(INTMR1);
  31. intmr1 &= ~(1 << d->irq);
  32. clps_writel(intmr1, INTMR1);
  33. }
  34. static void int1_ack(struct irq_data *d)
  35. {
  36. u32 intmr1;
  37. intmr1 = clps_readl(INTMR1);
  38. intmr1 &= ~(1 << d->irq);
  39. clps_writel(intmr1, INTMR1);
  40. switch (d->irq) {
  41. case IRQ_CSINT: clps_writel(0, COEOI); break;
  42. case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
  43. case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
  44. case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
  45. case IRQ_TINT: clps_writel(0, TEOI); break;
  46. case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
  47. }
  48. }
  49. static void int1_unmask(struct irq_data *d)
  50. {
  51. u32 intmr1;
  52. intmr1 = clps_readl(INTMR1);
  53. intmr1 |= 1 << d->irq;
  54. clps_writel(intmr1, INTMR1);
  55. }
  56. static struct irq_chip int1_chip = {
  57. .irq_ack = int1_ack,
  58. .irq_mask = int1_mask,
  59. .irq_unmask = int1_unmask,
  60. };
  61. static void int2_mask(struct irq_data *d)
  62. {
  63. u32 intmr2;
  64. intmr2 = clps_readl(INTMR2);
  65. intmr2 &= ~(1 << (d->irq - 16));
  66. clps_writel(intmr2, INTMR2);
  67. }
  68. static void int2_ack(struct irq_data *d)
  69. {
  70. u32 intmr2;
  71. intmr2 = clps_readl(INTMR2);
  72. intmr2 &= ~(1 << (d->irq - 16));
  73. clps_writel(intmr2, INTMR2);
  74. switch (d->irq) {
  75. case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
  76. }
  77. }
  78. static void int2_unmask(struct irq_data *d)
  79. {
  80. u32 intmr2;
  81. intmr2 = clps_readl(INTMR2);
  82. intmr2 |= 1 << (d->irq - 16);
  83. clps_writel(intmr2, INTMR2);
  84. }
  85. static struct irq_chip int2_chip = {
  86. .irq_ack = int2_ack,
  87. .irq_mask = int2_mask,
  88. .irq_unmask = int2_unmask,
  89. };
  90. void __init clps711x_init_irq(void)
  91. {
  92. unsigned int i;
  93. for (i = 0; i < NR_IRQS; i++) {
  94. if (INT1_IRQS & (1 << i)) {
  95. irq_set_chip_and_handler(i, &int1_chip,
  96. handle_level_irq);
  97. set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
  98. }
  99. if (INT2_IRQS & (1 << i)) {
  100. irq_set_chip_and_handler(i, &int2_chip,
  101. handle_level_irq);
  102. set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
  103. }
  104. }
  105. /*
  106. * Disable interrupts
  107. */
  108. clps_writel(0, INTMR1);
  109. clps_writel(0, INTMR2);
  110. /*
  111. * Clear down any pending interrupts
  112. */
  113. clps_writel(0, COEOI);
  114. clps_writel(0, TC1EOI);
  115. clps_writel(0, TC2EOI);
  116. clps_writel(0, RTCEOI);
  117. clps_writel(0, TEOI);
  118. clps_writel(0, UMSEOI);
  119. clps_writel(0, SYNCIO);
  120. clps_writel(0, KBDEOI);
  121. }