share.h 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683
  1. /*
  2. * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
  3. * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public
  6. * License as published by the Free Software Foundation;
  7. * either version 2, or (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  10. * the implied warranty of MERCHANTABILITY or FITNESS FOR
  11. * A PARTICULAR PURPOSE.See the GNU General Public License
  12. * for more details.
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. */
  18. #ifndef __SHARE_H__
  19. #define __SHARE_H__
  20. /* Define Bit Field */
  21. #define BIT0 0x01
  22. #define BIT1 0x02
  23. #define BIT2 0x04
  24. #define BIT3 0x08
  25. #define BIT4 0x10
  26. #define BIT5 0x20
  27. #define BIT6 0x40
  28. #define BIT7 0x80
  29. /* Video Memory Size */
  30. #define VIDEO_MEMORY_SIZE_16M 0x1000000
  31. /*
  32. * Lengths of the VPIT structure arrays.
  33. */
  34. #define StdCR 0x19
  35. #define StdSR 0x04
  36. #define StdGR 0x09
  37. #define StdAR 0x14
  38. #define PatchCR 11
  39. /* Display path */
  40. #define IGA1 1
  41. #define IGA2 2
  42. /* Define Color Depth */
  43. #define MODE_8BPP 1
  44. #define MODE_16BPP 2
  45. #define MODE_32BPP 4
  46. #define GR20 0x20
  47. #define GR21 0x21
  48. #define GR22 0x22
  49. /* Sequencer Registers */
  50. #define SR01 0x01
  51. #define SR10 0x10
  52. #define SR12 0x12
  53. #define SR15 0x15
  54. #define SR16 0x16
  55. #define SR17 0x17
  56. #define SR18 0x18
  57. #define SR1B 0x1B
  58. #define SR1A 0x1A
  59. #define SR1C 0x1C
  60. #define SR1D 0x1D
  61. #define SR1E 0x1E
  62. #define SR1F 0x1F
  63. #define SR20 0x20
  64. #define SR21 0x21
  65. #define SR22 0x22
  66. #define SR2A 0x2A
  67. #define SR2D 0x2D
  68. #define SR2E 0x2E
  69. #define SR30 0x30
  70. #define SR39 0x39
  71. #define SR3D 0x3D
  72. #define SR3E 0x3E
  73. #define SR3F 0x3F
  74. #define SR40 0x40
  75. #define SR43 0x43
  76. #define SR44 0x44
  77. #define SR45 0x45
  78. #define SR46 0x46
  79. #define SR47 0x47
  80. #define SR48 0x48
  81. #define SR49 0x49
  82. #define SR4A 0x4A
  83. #define SR4B 0x4B
  84. #define SR4C 0x4C
  85. #define SR52 0x52
  86. #define SR57 0x57
  87. #define SR58 0x58
  88. #define SR59 0x59
  89. #define SR5D 0x5D
  90. #define SR5E 0x5E
  91. #define SR65 0x65
  92. /* CRT Controller Registers */
  93. #define CR00 0x00
  94. #define CR01 0x01
  95. #define CR02 0x02
  96. #define CR03 0x03
  97. #define CR04 0x04
  98. #define CR05 0x05
  99. #define CR06 0x06
  100. #define CR07 0x07
  101. #define CR08 0x08
  102. #define CR09 0x09
  103. #define CR0A 0x0A
  104. #define CR0B 0x0B
  105. #define CR0C 0x0C
  106. #define CR0D 0x0D
  107. #define CR0E 0x0E
  108. #define CR0F 0x0F
  109. #define CR10 0x10
  110. #define CR11 0x11
  111. #define CR12 0x12
  112. #define CR13 0x13
  113. #define CR14 0x14
  114. #define CR15 0x15
  115. #define CR16 0x16
  116. #define CR17 0x17
  117. #define CR18 0x18
  118. /* Extend CRT Controller Registers */
  119. #define CR30 0x30
  120. #define CR31 0x31
  121. #define CR32 0x32
  122. #define CR33 0x33
  123. #define CR34 0x34
  124. #define CR35 0x35
  125. #define CR36 0x36
  126. #define CR37 0x37
  127. #define CR38 0x38
  128. #define CR39 0x39
  129. #define CR3A 0x3A
  130. #define CR3B 0x3B
  131. #define CR3C 0x3C
  132. #define CR3D 0x3D
  133. #define CR3E 0x3E
  134. #define CR3F 0x3F
  135. #define CR40 0x40
  136. #define CR41 0x41
  137. #define CR42 0x42
  138. #define CR43 0x43
  139. #define CR44 0x44
  140. #define CR45 0x45
  141. #define CR46 0x46
  142. #define CR47 0x47
  143. #define CR48 0x48
  144. #define CR49 0x49
  145. #define CR4A 0x4A
  146. #define CR4B 0x4B
  147. #define CR4C 0x4C
  148. #define CR4D 0x4D
  149. #define CR4E 0x4E
  150. #define CR4F 0x4F
  151. #define CR50 0x50
  152. #define CR51 0x51
  153. #define CR52 0x52
  154. #define CR53 0x53
  155. #define CR54 0x54
  156. #define CR55 0x55
  157. #define CR56 0x56
  158. #define CR57 0x57
  159. #define CR58 0x58
  160. #define CR59 0x59
  161. #define CR5A 0x5A
  162. #define CR5B 0x5B
  163. #define CR5C 0x5C
  164. #define CR5D 0x5D
  165. #define CR5E 0x5E
  166. #define CR5F 0x5F
  167. #define CR60 0x60
  168. #define CR61 0x61
  169. #define CR62 0x62
  170. #define CR63 0x63
  171. #define CR64 0x64
  172. #define CR65 0x65
  173. #define CR66 0x66
  174. #define CR67 0x67
  175. #define CR68 0x68
  176. #define CR69 0x69
  177. #define CR6A 0x6A
  178. #define CR6B 0x6B
  179. #define CR6C 0x6C
  180. #define CR6D 0x6D
  181. #define CR6E 0x6E
  182. #define CR6F 0x6F
  183. #define CR70 0x70
  184. #define CR71 0x71
  185. #define CR72 0x72
  186. #define CR73 0x73
  187. #define CR74 0x74
  188. #define CR75 0x75
  189. #define CR76 0x76
  190. #define CR77 0x77
  191. #define CR78 0x78
  192. #define CR79 0x79
  193. #define CR7A 0x7A
  194. #define CR7B 0x7B
  195. #define CR7C 0x7C
  196. #define CR7D 0x7D
  197. #define CR7E 0x7E
  198. #define CR7F 0x7F
  199. #define CR80 0x80
  200. #define CR81 0x81
  201. #define CR82 0x82
  202. #define CR83 0x83
  203. #define CR84 0x84
  204. #define CR85 0x85
  205. #define CR86 0x86
  206. #define CR87 0x87
  207. #define CR88 0x88
  208. #define CR89 0x89
  209. #define CR8A 0x8A
  210. #define CR8B 0x8B
  211. #define CR8C 0x8C
  212. #define CR8D 0x8D
  213. #define CR8E 0x8E
  214. #define CR8F 0x8F
  215. #define CR90 0x90
  216. #define CR91 0x91
  217. #define CR92 0x92
  218. #define CR93 0x93
  219. #define CR94 0x94
  220. #define CR95 0x95
  221. #define CR96 0x96
  222. #define CR97 0x97
  223. #define CR98 0x98
  224. #define CR99 0x99
  225. #define CR9A 0x9A
  226. #define CR9B 0x9B
  227. #define CR9C 0x9C
  228. #define CR9D 0x9D
  229. #define CR9E 0x9E
  230. #define CR9F 0x9F
  231. #define CRA0 0xA0
  232. #define CRA1 0xA1
  233. #define CRA2 0xA2
  234. #define CRA3 0xA3
  235. #define CRD2 0xD2
  236. #define CRD3 0xD3
  237. #define CRD4 0xD4
  238. /* LUT Table*/
  239. #define LUT_DATA 0x3C9 /* DACDATA */
  240. #define LUT_INDEX_READ 0x3C7 /* DACRX */
  241. #define LUT_INDEX_WRITE 0x3C8 /* DACWX */
  242. #define DACMASK 0x3C6
  243. /* Definition Device */
  244. #define DEVICE_CRT 0x01
  245. #define DEVICE_DVI 0x03
  246. #define DEVICE_LCD 0x04
  247. /* Device output interface */
  248. #define INTERFACE_NONE 0x00
  249. #define INTERFACE_ANALOG_RGB 0x01
  250. #define INTERFACE_DVP0 0x02
  251. #define INTERFACE_DVP1 0x03
  252. #define INTERFACE_DFP_HIGH 0x04
  253. #define INTERFACE_DFP_LOW 0x05
  254. #define INTERFACE_DFP 0x06
  255. #define INTERFACE_LVDS0 0x07
  256. #define INTERFACE_LVDS1 0x08
  257. #define INTERFACE_LVDS0LVDS1 0x09
  258. #define INTERFACE_TMDS 0x0A
  259. #define HW_LAYOUT_LCD_ONLY 0x01
  260. #define HW_LAYOUT_DVI_ONLY 0x02
  261. #define HW_LAYOUT_LCD_DVI 0x03
  262. #define HW_LAYOUT_LCD1_LCD2 0x04
  263. #define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
  264. /* Definition Refresh Rate */
  265. #define REFRESH_49 49
  266. #define REFRESH_50 50
  267. #define REFRESH_60 60
  268. #define REFRESH_75 75
  269. #define REFRESH_85 85
  270. #define REFRESH_100 100
  271. #define REFRESH_120 120
  272. /* Definition Sync Polarity*/
  273. #define NEGATIVE 1
  274. #define POSITIVE 0
  275. /*480x640@60 Sync Polarity (GTF)
  276. */
  277. #define M480X640_R60_HSP NEGATIVE
  278. #define M480X640_R60_VSP POSITIVE
  279. /*640x480@60 Sync Polarity (VESA Mode)
  280. */
  281. #define M640X480_R60_HSP NEGATIVE
  282. #define M640X480_R60_VSP NEGATIVE
  283. /*640x480@75 Sync Polarity (VESA Mode)
  284. */
  285. #define M640X480_R75_HSP NEGATIVE
  286. #define M640X480_R75_VSP NEGATIVE
  287. /*640x480@85 Sync Polarity (VESA Mode)
  288. */
  289. #define M640X480_R85_HSP NEGATIVE
  290. #define M640X480_R85_VSP NEGATIVE
  291. /*640x480@100 Sync Polarity (GTF Mode)
  292. */
  293. #define M640X480_R100_HSP NEGATIVE
  294. #define M640X480_R100_VSP POSITIVE
  295. /*640x480@120 Sync Polarity (GTF Mode)
  296. */
  297. #define M640X480_R120_HSP NEGATIVE
  298. #define M640X480_R120_VSP POSITIVE
  299. /*720x480@60 Sync Polarity (GTF Mode)
  300. */
  301. #define M720X480_R60_HSP NEGATIVE
  302. #define M720X480_R60_VSP POSITIVE
  303. /*720x576@60 Sync Polarity (GTF Mode)
  304. */
  305. #define M720X576_R60_HSP NEGATIVE
  306. #define M720X576_R60_VSP POSITIVE
  307. /*800x600@60 Sync Polarity (VESA Mode)
  308. */
  309. #define M800X600_R60_HSP POSITIVE
  310. #define M800X600_R60_VSP POSITIVE
  311. /*800x600@75 Sync Polarity (VESA Mode)
  312. */
  313. #define M800X600_R75_HSP POSITIVE
  314. #define M800X600_R75_VSP POSITIVE
  315. /*800x600@85 Sync Polarity (VESA Mode)
  316. */
  317. #define M800X600_R85_HSP POSITIVE
  318. #define M800X600_R85_VSP POSITIVE
  319. /*800x600@100 Sync Polarity (GTF Mode)
  320. */
  321. #define M800X600_R100_HSP NEGATIVE
  322. #define M800X600_R100_VSP POSITIVE
  323. /*800x600@120 Sync Polarity (GTF Mode)
  324. */
  325. #define M800X600_R120_HSP NEGATIVE
  326. #define M800X600_R120_VSP POSITIVE
  327. /*800x480@60 Sync Polarity (CVT Mode)
  328. */
  329. #define M800X480_R60_HSP NEGATIVE
  330. #define M800X480_R60_VSP POSITIVE
  331. /*848x480@60 Sync Polarity (CVT Mode)
  332. */
  333. #define M848X480_R60_HSP NEGATIVE
  334. #define M848X480_R60_VSP POSITIVE
  335. /*852x480@60 Sync Polarity (GTF Mode)
  336. */
  337. #define M852X480_R60_HSP NEGATIVE
  338. #define M852X480_R60_VSP POSITIVE
  339. /*1024x512@60 Sync Polarity (GTF Mode)
  340. */
  341. #define M1024X512_R60_HSP NEGATIVE
  342. #define M1024X512_R60_VSP POSITIVE
  343. /*1024x600@60 Sync Polarity (GTF Mode)
  344. */
  345. #define M1024X600_R60_HSP NEGATIVE
  346. #define M1024X600_R60_VSP POSITIVE
  347. /*1024x768@60 Sync Polarity (VESA Mode)
  348. */
  349. #define M1024X768_R60_HSP NEGATIVE
  350. #define M1024X768_R60_VSP NEGATIVE
  351. /*1024x768@75 Sync Polarity (VESA Mode)
  352. */
  353. #define M1024X768_R75_HSP POSITIVE
  354. #define M1024X768_R75_VSP POSITIVE
  355. /*1024x768@85 Sync Polarity (VESA Mode)
  356. */
  357. #define M1024X768_R85_HSP POSITIVE
  358. #define M1024X768_R85_VSP POSITIVE
  359. /*1024x768@100 Sync Polarity (GTF Mode)
  360. */
  361. #define M1024X768_R100_HSP NEGATIVE
  362. #define M1024X768_R100_VSP POSITIVE
  363. /*1152x864@75 Sync Polarity (VESA Mode)
  364. */
  365. #define M1152X864_R75_HSP POSITIVE
  366. #define M1152X864_R75_VSP POSITIVE
  367. /*1280x720@60 Sync Polarity (GTF Mode)
  368. */
  369. #define M1280X720_R60_HSP NEGATIVE
  370. #define M1280X720_R60_VSP POSITIVE
  371. /* 1280x768@50 Sync Polarity (GTF Mode) */
  372. #define M1280X768_R50_HSP NEGATIVE
  373. #define M1280X768_R50_VSP POSITIVE
  374. /*1280x768@60 Sync Polarity (GTF Mode)
  375. */
  376. #define M1280X768_R60_HSP NEGATIVE
  377. #define M1280X768_R60_VSP POSITIVE
  378. /*1280x800@60 Sync Polarity (CVT Mode)
  379. */
  380. #define M1280X800_R60_HSP NEGATIVE
  381. #define M1280X800_R60_VSP POSITIVE
  382. /*1280x960@60 Sync Polarity (VESA Mode)
  383. */
  384. #define M1280X960_R60_HSP POSITIVE
  385. #define M1280X960_R60_VSP POSITIVE
  386. /*1280x1024@60 Sync Polarity (VESA Mode)
  387. */
  388. #define M1280X1024_R60_HSP POSITIVE
  389. #define M1280X1024_R60_VSP POSITIVE
  390. /* 1360x768@60 Sync Polarity (CVT Mode) */
  391. #define M1360X768_R60_HSP POSITIVE
  392. #define M1360X768_R60_VSP POSITIVE
  393. /* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */
  394. #define M1360X768_RB_R60_HSP POSITIVE
  395. #define M1360X768_RB_R60_VSP NEGATIVE
  396. /* 1368x768@50 Sync Polarity (GTF Mode) */
  397. #define M1368X768_R50_HSP NEGATIVE
  398. #define M1368X768_R50_VSP POSITIVE
  399. /* 1368x768@60 Sync Polarity (VESA Mode) */
  400. #define M1368X768_R60_HSP NEGATIVE
  401. #define M1368X768_R60_VSP POSITIVE
  402. /*1280x1024@75 Sync Polarity (VESA Mode)
  403. */
  404. #define M1280X1024_R75_HSP POSITIVE
  405. #define M1280X1024_R75_VSP POSITIVE
  406. /*1280x1024@85 Sync Polarity (VESA Mode)
  407. */
  408. #define M1280X1024_R85_HSP POSITIVE
  409. #define M1280X1024_R85_VSP POSITIVE
  410. /*1440x1050@60 Sync Polarity (GTF Mode)
  411. */
  412. #define M1440X1050_R60_HSP NEGATIVE
  413. #define M1440X1050_R60_VSP POSITIVE
  414. /*1600x1200@60 Sync Polarity (VESA Mode)
  415. */
  416. #define M1600X1200_R60_HSP POSITIVE
  417. #define M1600X1200_R60_VSP POSITIVE
  418. /*1600x1200@75 Sync Polarity (VESA Mode)
  419. */
  420. #define M1600X1200_R75_HSP POSITIVE
  421. #define M1600X1200_R75_VSP POSITIVE
  422. /* 1680x1050@60 Sync Polarity (CVT Mode) */
  423. #define M1680x1050_R60_HSP NEGATIVE
  424. #define M1680x1050_R60_VSP NEGATIVE
  425. /* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
  426. #define M1680x1050_RB_R60_HSP POSITIVE
  427. #define M1680x1050_RB_R60_VSP NEGATIVE
  428. /* 1680x1050@75 Sync Polarity (CVT Mode) */
  429. #define M1680x1050_R75_HSP NEGATIVE
  430. #define M1680x1050_R75_VSP POSITIVE
  431. /*1920x1080@60 Sync Polarity (CVT Mode)
  432. */
  433. #define M1920X1080_R60_HSP NEGATIVE
  434. #define M1920X1080_R60_VSP POSITIVE
  435. /* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */
  436. #define M1920X1080_RB_R60_HSP POSITIVE
  437. #define M1920X1080_RB_R60_VSP NEGATIVE
  438. /*1920x1440@60 Sync Polarity (VESA Mode)
  439. */
  440. #define M1920X1440_R60_HSP NEGATIVE
  441. #define M1920X1440_R60_VSP POSITIVE
  442. /*1920x1440@75 Sync Polarity (VESA Mode)
  443. */
  444. #define M1920X1440_R75_HSP NEGATIVE
  445. #define M1920X1440_R75_VSP POSITIVE
  446. #if 0
  447. /* 1400x1050@60 Sync Polarity (VESA Mode) */
  448. #define M1400X1050_R60_HSP NEGATIVE
  449. #define M1400X1050_R60_VSP NEGATIVE
  450. #endif
  451. /* 1400x1050@60 Sync Polarity (CVT Mode) */
  452. #define M1400X1050_R60_HSP NEGATIVE
  453. #define M1400X1050_R60_VSP POSITIVE
  454. /* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
  455. #define M1400X1050_RB_R60_HSP POSITIVE
  456. #define M1400X1050_RB_R60_VSP NEGATIVE
  457. /* 1400x1050@75 Sync Polarity (CVT Mode) */
  458. #define M1400X1050_R75_HSP NEGATIVE
  459. #define M1400X1050_R75_VSP POSITIVE
  460. /* 960x600@60 Sync Polarity (CVT Mode) */
  461. #define M960X600_R60_HSP NEGATIVE
  462. #define M960X600_R60_VSP POSITIVE
  463. /* 1000x600@60 Sync Polarity (GTF Mode) */
  464. #define M1000X600_R60_HSP NEGATIVE
  465. #define M1000X600_R60_VSP POSITIVE
  466. /* 1024x576@60 Sync Polarity (GTF Mode) */
  467. #define M1024X576_R60_HSP NEGATIVE
  468. #define M1024X576_R60_VSP POSITIVE
  469. /*1024x600@60 Sync Polarity (GTF Mode)*/
  470. #define M1024X600_R60_HSP NEGATIVE
  471. #define M1024X600_R60_VSP POSITIVE
  472. /* 1088x612@60 Sync Polarity (CVT Mode) */
  473. #define M1088X612_R60_HSP NEGATIVE
  474. #define M1088X612_R60_VSP POSITIVE
  475. /* 1152x720@60 Sync Polarity (CVT Mode) */
  476. #define M1152X720_R60_HSP NEGATIVE
  477. #define M1152X720_R60_VSP POSITIVE
  478. /* 1200x720@60 Sync Polarity (GTF Mode) */
  479. #define M1200X720_R60_HSP NEGATIVE
  480. #define M1200X720_R60_VSP POSITIVE
  481. /* 1200x900@60 Sync Polarity (DCON) */
  482. #define M1200X900_R60_HSP POSITIVE
  483. #define M1200X900_R60_VSP POSITIVE
  484. /* 1280x600@60 Sync Polarity (GTF Mode) */
  485. #define M1280x600_R60_HSP NEGATIVE
  486. #define M1280x600_R60_VSP POSITIVE
  487. /* 1280x720@50 Sync Polarity (GTF Mode) */
  488. #define M1280X720_R50_HSP NEGATIVE
  489. #define M1280X720_R50_VSP POSITIVE
  490. /* 1440x900@60 Sync Polarity (CVT Mode) */
  491. #define M1440X900_R60_HSP NEGATIVE
  492. #define M1440X900_R60_VSP POSITIVE
  493. /* 1440x900@75 Sync Polarity (CVT Mode) */
  494. #define M1440X900_R75_HSP NEGATIVE
  495. #define M1440X900_R75_VSP POSITIVE
  496. /* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
  497. #define M1440X900_RB_R60_HSP POSITIVE
  498. #define M1440X900_RB_R60_VSP NEGATIVE
  499. /* 1600x900@60 Sync Polarity (CVT Mode) */
  500. #define M1600X900_R60_HSP NEGATIVE
  501. #define M1600X900_R60_VSP POSITIVE
  502. /* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
  503. #define M1600X900_RB_R60_HSP POSITIVE
  504. #define M1600X900_RB_R60_VSP NEGATIVE
  505. /* 1600x1024@60 Sync Polarity (GTF Mode) */
  506. #define M1600X1024_R60_HSP NEGATIVE
  507. #define M1600X1024_R60_VSP POSITIVE
  508. /* 1792x1344@60 Sync Polarity (DMT Mode) */
  509. #define M1792x1344_R60_HSP NEGATIVE
  510. #define M1792x1344_R60_VSP POSITIVE
  511. /* 1856x1392@60 Sync Polarity (DMT Mode) */
  512. #define M1856x1392_R60_HSP NEGATIVE
  513. #define M1856x1392_R60_VSP POSITIVE
  514. /* 1920x1200@60 Sync Polarity (CVT Mode) */
  515. #define M1920X1200_R60_HSP NEGATIVE
  516. #define M1920X1200_R60_VSP POSITIVE
  517. /* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */
  518. #define M1920X1200_RB_R60_HSP POSITIVE
  519. #define M1920X1200_RB_R60_VSP NEGATIVE
  520. /* 2048x1536@60 Sync Polarity (CVT Mode) */
  521. #define M2048x1536_R60_HSP NEGATIVE
  522. #define M2048x1536_R60_VSP POSITIVE
  523. /* Definition CRTC Timing Index */
  524. #define H_TOTAL_INDEX 0
  525. #define H_ADDR_INDEX 1
  526. #define H_BLANK_START_INDEX 2
  527. #define H_BLANK_END_INDEX 3
  528. #define H_SYNC_START_INDEX 4
  529. #define H_SYNC_END_INDEX 5
  530. #define V_TOTAL_INDEX 6
  531. #define V_ADDR_INDEX 7
  532. #define V_BLANK_START_INDEX 8
  533. #define V_BLANK_END_INDEX 9
  534. #define V_SYNC_START_INDEX 10
  535. #define V_SYNC_END_INDEX 11
  536. #define H_TOTAL_SHADOW_INDEX 12
  537. #define H_BLANK_END_SHADOW_INDEX 13
  538. #define V_TOTAL_SHADOW_INDEX 14
  539. #define V_ADDR_SHADOW_INDEX 15
  540. #define V_BLANK_SATRT_SHADOW_INDEX 16
  541. #define V_BLANK_END_SHADOW_INDEX 17
  542. #define V_SYNC_SATRT_SHADOW_INDEX 18
  543. #define V_SYNC_END_SHADOW_INDEX 19
  544. /* Definition Video Mode Pixel Clock (picoseconds)
  545. */
  546. #define RES_640X480_60HZ_PIXCLOCK 39722
  547. /* LCD display method
  548. */
  549. #define LCD_EXPANDSION 0x00
  550. #define LCD_CENTERING 0x01
  551. /* LCD mode
  552. */
  553. #define LCD_OPENLDI 0x00
  554. #define LCD_SPWG 0x01
  555. /* Define display timing
  556. */
  557. struct display_timing {
  558. u16 hor_total;
  559. u16 hor_addr;
  560. u16 hor_blank_start;
  561. u16 hor_blank_end;
  562. u16 hor_sync_start;
  563. u16 hor_sync_end;
  564. u16 ver_total;
  565. u16 ver_addr;
  566. u16 ver_blank_start;
  567. u16 ver_blank_end;
  568. u16 ver_sync_start;
  569. u16 ver_sync_end;
  570. };
  571. struct crt_mode_table {
  572. int refresh_rate;
  573. int h_sync_polarity;
  574. int v_sync_polarity;
  575. struct display_timing crtc;
  576. };
  577. struct io_reg {
  578. int port;
  579. u8 index;
  580. u8 mask;
  581. u8 value;
  582. };
  583. #endif /* __SHARE_H__ */