ep93xx-fb.c 17 KB

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  1. /*
  2. * linux/drivers/video/ep93xx-fb.c
  3. *
  4. * Framebuffer support for the EP93xx series.
  5. *
  6. * Copyright (C) 2007 Bluewater Systems Ltd
  7. * Author: Ryan Mallon <ryan@bluewatersys.com>
  8. *
  9. * Copyright (c) 2009 H Hartley Sweeten <hsweeten@visionengravers.com>
  10. *
  11. * Based on the Cirrus Logic ep93xxfb driver, and various other ep93xxfb
  12. * drivers.
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. *
  18. */
  19. #include <linux/platform_device.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/slab.h>
  22. #include <linux/clk.h>
  23. #include <linux/fb.h>
  24. #include <mach/fb.h>
  25. /* Vertical Frame Timing Registers */
  26. #define EP93XXFB_VLINES_TOTAL 0x0000 /* SW locked */
  27. #define EP93XXFB_VSYNC 0x0004 /* SW locked */
  28. #define EP93XXFB_VACTIVE 0x0008 /* SW locked */
  29. #define EP93XXFB_VBLANK 0x0228 /* SW locked */
  30. #define EP93XXFB_VCLK 0x000c /* SW locked */
  31. /* Horizontal Frame Timing Registers */
  32. #define EP93XXFB_HCLKS_TOTAL 0x0010 /* SW locked */
  33. #define EP93XXFB_HSYNC 0x0014 /* SW locked */
  34. #define EP93XXFB_HACTIVE 0x0018 /* SW locked */
  35. #define EP93XXFB_HBLANK 0x022c /* SW locked */
  36. #define EP93XXFB_HCLK 0x001c /* SW locked */
  37. /* Frame Buffer Memory Configuration Registers */
  38. #define EP93XXFB_SCREEN_PAGE 0x0028
  39. #define EP93XXFB_SCREEN_HPAGE 0x002c
  40. #define EP93XXFB_SCREEN_LINES 0x0030
  41. #define EP93XXFB_LINE_LENGTH 0x0034
  42. #define EP93XXFB_VLINE_STEP 0x0038
  43. #define EP93XXFB_LINE_CARRY 0x003c /* SW locked */
  44. #define EP93XXFB_EOL_OFFSET 0x0230
  45. /* Other Video Registers */
  46. #define EP93XXFB_BRIGHTNESS 0x0020
  47. #define EP93XXFB_ATTRIBS 0x0024 /* SW locked */
  48. #define EP93XXFB_SWLOCK 0x007c /* SW locked */
  49. #define EP93XXFB_AC_RATE 0x0214
  50. #define EP93XXFB_FIFO_LEVEL 0x0234
  51. #define EP93XXFB_PIXELMODE 0x0054
  52. #define EP93XXFB_PIXELMODE_32BPP (0x7 << 0)
  53. #define EP93XXFB_PIXELMODE_24BPP (0x6 << 0)
  54. #define EP93XXFB_PIXELMODE_16BPP (0x4 << 0)
  55. #define EP93XXFB_PIXELMODE_8BPP (0x2 << 0)
  56. #define EP93XXFB_PIXELMODE_SHIFT_1P_24B (0x0 << 3)
  57. #define EP93XXFB_PIXELMODE_SHIFT_1P_18B (0x1 << 3)
  58. #define EP93XXFB_PIXELMODE_COLOR_LUT (0x0 << 10)
  59. #define EP93XXFB_PIXELMODE_COLOR_888 (0x4 << 10)
  60. #define EP93XXFB_PIXELMODE_COLOR_555 (0x5 << 10)
  61. #define EP93XXFB_PARL_IF_OUT 0x0058
  62. #define EP93XXFB_PARL_IF_IN 0x005c
  63. /* Blink Control Registers */
  64. #define EP93XXFB_BLINK_RATE 0x0040
  65. #define EP93XXFB_BLINK_MASK 0x0044
  66. #define EP93XXFB_BLINK_PATTRN 0x0048
  67. #define EP93XXFB_PATTRN_MASK 0x004c
  68. #define EP93XXFB_BKGRND_OFFSET 0x0050
  69. /* Hardware Cursor Registers */
  70. #define EP93XXFB_CURSOR_ADR_START 0x0060
  71. #define EP93XXFB_CURSOR_ADR_RESET 0x0064
  72. #define EP93XXFB_CURSOR_SIZE 0x0068
  73. #define EP93XXFB_CURSOR_COLOR1 0x006c
  74. #define EP93XXFB_CURSOR_COLOR2 0x0070
  75. #define EP93XXFB_CURSOR_BLINK_COLOR1 0x021c
  76. #define EP93XXFB_CURSOR_BLINK_COLOR2 0x0220
  77. #define EP93XXFB_CURSOR_XY_LOC 0x0074
  78. #define EP93XXFB_CURSOR_DSCAN_HY_LOC 0x0078
  79. #define EP93XXFB_CURSOR_BLINK_RATE_CTRL 0x0224
  80. /* LUT Registers */
  81. #define EP93XXFB_GRY_SCL_LUTR 0x0080
  82. #define EP93XXFB_GRY_SCL_LUTG 0x0280
  83. #define EP93XXFB_GRY_SCL_LUTB 0x0300
  84. #define EP93XXFB_LUT_SW_CONTROL 0x0218
  85. #define EP93XXFB_LUT_SW_CONTROL_SWTCH (1 << 0)
  86. #define EP93XXFB_LUT_SW_CONTROL_SSTAT (1 << 1)
  87. #define EP93XXFB_COLOR_LUT 0x0400
  88. /* Video Signature Registers */
  89. #define EP93XXFB_VID_SIG_RSLT_VAL 0x0200
  90. #define EP93XXFB_VID_SIG_CTRL 0x0204
  91. #define EP93XXFB_VSIG 0x0208
  92. #define EP93XXFB_HSIG 0x020c
  93. #define EP93XXFB_SIG_CLR_STR 0x0210
  94. /* Minimum / Maximum resolutions supported */
  95. #define EP93XXFB_MIN_XRES 64
  96. #define EP93XXFB_MIN_YRES 64
  97. #define EP93XXFB_MAX_XRES 1024
  98. #define EP93XXFB_MAX_YRES 768
  99. struct ep93xx_fbi {
  100. struct ep93xxfb_mach_info *mach_info;
  101. struct clk *clk;
  102. struct resource *res;
  103. void __iomem *mmio_base;
  104. unsigned int pseudo_palette[256];
  105. };
  106. static int check_screenpage_bug = 1;
  107. module_param(check_screenpage_bug, int, 0644);
  108. MODULE_PARM_DESC(check_screenpage_bug,
  109. "Check for bit 27 screen page bug. Default = 1");
  110. static inline unsigned int ep93xxfb_readl(struct ep93xx_fbi *fbi,
  111. unsigned int off)
  112. {
  113. return __raw_readl(fbi->mmio_base + off);
  114. }
  115. static inline void ep93xxfb_writel(struct ep93xx_fbi *fbi,
  116. unsigned int val, unsigned int off)
  117. {
  118. __raw_writel(val, fbi->mmio_base + off);
  119. }
  120. /*
  121. * Write to one of the locked raster registers.
  122. */
  123. static inline void ep93xxfb_out_locked(struct ep93xx_fbi *fbi,
  124. unsigned int val, unsigned int reg)
  125. {
  126. /*
  127. * We don't need a lock or delay here since the raster register
  128. * block will remain unlocked until the next access.
  129. */
  130. ep93xxfb_writel(fbi, 0xaa, EP93XXFB_SWLOCK);
  131. ep93xxfb_writel(fbi, val, reg);
  132. }
  133. static void ep93xxfb_set_video_attribs(struct fb_info *info)
  134. {
  135. struct ep93xx_fbi *fbi = info->par;
  136. unsigned int attribs;
  137. attribs = EP93XXFB_ENABLE;
  138. attribs |= fbi->mach_info->flags;
  139. ep93xxfb_out_locked(fbi, attribs, EP93XXFB_ATTRIBS);
  140. }
  141. static int ep93xxfb_set_pixelmode(struct fb_info *info)
  142. {
  143. struct ep93xx_fbi *fbi = info->par;
  144. unsigned int val;
  145. info->var.transp.offset = 0;
  146. info->var.transp.length = 0;
  147. switch (info->var.bits_per_pixel) {
  148. case 8:
  149. val = EP93XXFB_PIXELMODE_8BPP | EP93XXFB_PIXELMODE_COLOR_LUT |
  150. EP93XXFB_PIXELMODE_SHIFT_1P_18B;
  151. info->var.red.offset = 0;
  152. info->var.red.length = 8;
  153. info->var.green.offset = 0;
  154. info->var.green.length = 8;
  155. info->var.blue.offset = 0;
  156. info->var.blue.length = 8;
  157. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  158. break;
  159. case 16:
  160. val = EP93XXFB_PIXELMODE_16BPP | EP93XXFB_PIXELMODE_COLOR_555 |
  161. EP93XXFB_PIXELMODE_SHIFT_1P_18B;
  162. info->var.red.offset = 11;
  163. info->var.red.length = 5;
  164. info->var.green.offset = 5;
  165. info->var.green.length = 6;
  166. info->var.blue.offset = 0;
  167. info->var.blue.length = 5;
  168. info->fix.visual = FB_VISUAL_TRUECOLOR;
  169. break;
  170. case 24:
  171. val = EP93XXFB_PIXELMODE_24BPP | EP93XXFB_PIXELMODE_COLOR_888 |
  172. EP93XXFB_PIXELMODE_SHIFT_1P_24B;
  173. info->var.red.offset = 16;
  174. info->var.red.length = 8;
  175. info->var.green.offset = 8;
  176. info->var.green.length = 8;
  177. info->var.blue.offset = 0;
  178. info->var.blue.length = 8;
  179. info->fix.visual = FB_VISUAL_TRUECOLOR;
  180. break;
  181. case 32:
  182. val = EP93XXFB_PIXELMODE_32BPP | EP93XXFB_PIXELMODE_COLOR_888 |
  183. EP93XXFB_PIXELMODE_SHIFT_1P_24B;
  184. info->var.red.offset = 16;
  185. info->var.red.length = 8;
  186. info->var.green.offset = 8;
  187. info->var.green.length = 8;
  188. info->var.blue.offset = 0;
  189. info->var.blue.length = 8;
  190. info->fix.visual = FB_VISUAL_TRUECOLOR;
  191. break;
  192. default:
  193. return -EINVAL;
  194. }
  195. ep93xxfb_writel(fbi, val, EP93XXFB_PIXELMODE);
  196. return 0;
  197. }
  198. static void ep93xxfb_set_timing(struct fb_info *info)
  199. {
  200. struct ep93xx_fbi *fbi = info->par;
  201. unsigned int vlines_total, hclks_total, start, stop;
  202. vlines_total = info->var.yres + info->var.upper_margin +
  203. info->var.lower_margin + info->var.vsync_len - 1;
  204. hclks_total = info->var.xres + info->var.left_margin +
  205. info->var.right_margin + info->var.hsync_len - 1;
  206. ep93xxfb_out_locked(fbi, vlines_total, EP93XXFB_VLINES_TOTAL);
  207. ep93xxfb_out_locked(fbi, hclks_total, EP93XXFB_HCLKS_TOTAL);
  208. start = vlines_total;
  209. stop = vlines_total - info->var.vsync_len;
  210. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VSYNC);
  211. start = vlines_total - info->var.vsync_len - info->var.upper_margin;
  212. stop = info->var.lower_margin - 1;
  213. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VBLANK);
  214. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VACTIVE);
  215. start = vlines_total;
  216. stop = vlines_total + 1;
  217. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VCLK);
  218. start = hclks_total;
  219. stop = hclks_total - info->var.hsync_len;
  220. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HSYNC);
  221. start = hclks_total - info->var.hsync_len - info->var.left_margin;
  222. stop = info->var.right_margin - 1;
  223. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HBLANK);
  224. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HACTIVE);
  225. start = hclks_total;
  226. stop = hclks_total;
  227. ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HCLK);
  228. ep93xxfb_out_locked(fbi, 0x0, EP93XXFB_LINE_CARRY);
  229. }
  230. static int ep93xxfb_set_par(struct fb_info *info)
  231. {
  232. struct ep93xx_fbi *fbi = info->par;
  233. clk_set_rate(fbi->clk, 1000 * PICOS2KHZ(info->var.pixclock));
  234. ep93xxfb_set_timing(info);
  235. info->fix.line_length = info->var.xres_virtual *
  236. info->var.bits_per_pixel / 8;
  237. ep93xxfb_writel(fbi, info->fix.smem_start, EP93XXFB_SCREEN_PAGE);
  238. ep93xxfb_writel(fbi, info->var.yres - 1, EP93XXFB_SCREEN_LINES);
  239. ep93xxfb_writel(fbi, ((info->var.xres * info->var.bits_per_pixel)
  240. / 32) - 1, EP93XXFB_LINE_LENGTH);
  241. ep93xxfb_writel(fbi, info->fix.line_length / 4, EP93XXFB_VLINE_STEP);
  242. ep93xxfb_set_video_attribs(info);
  243. return 0;
  244. }
  245. static int ep93xxfb_check_var(struct fb_var_screeninfo *var,
  246. struct fb_info *info)
  247. {
  248. int err;
  249. err = ep93xxfb_set_pixelmode(info);
  250. if (err)
  251. return err;
  252. var->xres = max_t(unsigned int, var->xres, EP93XXFB_MIN_XRES);
  253. var->xres = min_t(unsigned int, var->xres, EP93XXFB_MAX_XRES);
  254. var->xres_virtual = max(var->xres_virtual, var->xres);
  255. var->yres = max_t(unsigned int, var->yres, EP93XXFB_MIN_YRES);
  256. var->yres = min_t(unsigned int, var->yres, EP93XXFB_MAX_YRES);
  257. var->yres_virtual = max(var->yres_virtual, var->yres);
  258. return 0;
  259. }
  260. static int ep93xxfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
  261. {
  262. unsigned int offset = vma->vm_pgoff << PAGE_SHIFT;
  263. if (offset < info->fix.smem_len) {
  264. return dma_mmap_writecombine(info->dev, vma, info->screen_base,
  265. info->fix.smem_start,
  266. info->fix.smem_len);
  267. }
  268. return -EINVAL;
  269. }
  270. static int ep93xxfb_blank(int blank_mode, struct fb_info *info)
  271. {
  272. struct ep93xx_fbi *fbi = info->par;
  273. unsigned int attribs = ep93xxfb_readl(fbi, EP93XXFB_ATTRIBS);
  274. if (blank_mode) {
  275. if (fbi->mach_info->blank)
  276. fbi->mach_info->blank(blank_mode, info);
  277. ep93xxfb_out_locked(fbi, attribs & ~EP93XXFB_ENABLE,
  278. EP93XXFB_ATTRIBS);
  279. clk_disable(fbi->clk);
  280. } else {
  281. clk_enable(fbi->clk);
  282. ep93xxfb_out_locked(fbi, attribs | EP93XXFB_ENABLE,
  283. EP93XXFB_ATTRIBS);
  284. if (fbi->mach_info->blank)
  285. fbi->mach_info->blank(blank_mode, info);
  286. }
  287. return 0;
  288. }
  289. static inline int ep93xxfb_convert_color(int val, int width)
  290. {
  291. return ((val << width) + 0x7fff - val) >> 16;
  292. }
  293. static int ep93xxfb_setcolreg(unsigned int regno, unsigned int red,
  294. unsigned int green, unsigned int blue,
  295. unsigned int transp, struct fb_info *info)
  296. {
  297. struct ep93xx_fbi *fbi = info->par;
  298. unsigned int *pal = info->pseudo_palette;
  299. unsigned int ctrl, i, rgb, lut_current, lut_stat;
  300. switch (info->fix.visual) {
  301. case FB_VISUAL_PSEUDOCOLOR:
  302. if (regno > 255)
  303. return 1;
  304. rgb = ((red & 0xff00) << 8) | (green & 0xff00) |
  305. ((blue & 0xff00) >> 8);
  306. pal[regno] = rgb;
  307. ep93xxfb_writel(fbi, rgb, (EP93XXFB_COLOR_LUT + (regno << 2)));
  308. ctrl = ep93xxfb_readl(fbi, EP93XXFB_LUT_SW_CONTROL);
  309. lut_stat = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SSTAT);
  310. lut_current = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SWTCH);
  311. if (lut_stat == lut_current) {
  312. for (i = 0; i < 256; i++) {
  313. ep93xxfb_writel(fbi, pal[i],
  314. EP93XXFB_COLOR_LUT + (i << 2));
  315. }
  316. ep93xxfb_writel(fbi,
  317. ctrl ^ EP93XXFB_LUT_SW_CONTROL_SWTCH,
  318. EP93XXFB_LUT_SW_CONTROL);
  319. }
  320. break;
  321. case FB_VISUAL_TRUECOLOR:
  322. if (regno > 16)
  323. return 1;
  324. red = ep93xxfb_convert_color(red, info->var.red.length);
  325. green = ep93xxfb_convert_color(green, info->var.green.length);
  326. blue = ep93xxfb_convert_color(blue, info->var.blue.length);
  327. transp = ep93xxfb_convert_color(transp,
  328. info->var.transp.length);
  329. pal[regno] = (red << info->var.red.offset) |
  330. (green << info->var.green.offset) |
  331. (blue << info->var.blue.offset) |
  332. (transp << info->var.transp.offset);
  333. break;
  334. default:
  335. return 1;
  336. }
  337. return 0;
  338. }
  339. static struct fb_ops ep93xxfb_ops = {
  340. .owner = THIS_MODULE,
  341. .fb_check_var = ep93xxfb_check_var,
  342. .fb_set_par = ep93xxfb_set_par,
  343. .fb_blank = ep93xxfb_blank,
  344. .fb_fillrect = cfb_fillrect,
  345. .fb_copyarea = cfb_copyarea,
  346. .fb_imageblit = cfb_imageblit,
  347. .fb_setcolreg = ep93xxfb_setcolreg,
  348. .fb_mmap = ep93xxfb_mmap,
  349. };
  350. static int __init ep93xxfb_calc_fbsize(struct ep93xxfb_mach_info *mach_info)
  351. {
  352. int i, fb_size = 0;
  353. if (mach_info->num_modes == EP93XXFB_USE_MODEDB) {
  354. fb_size = EP93XXFB_MAX_XRES * EP93XXFB_MAX_YRES *
  355. mach_info->bpp / 8;
  356. } else {
  357. for (i = 0; i < mach_info->num_modes; i++) {
  358. const struct fb_videomode *mode;
  359. int size;
  360. mode = &mach_info->modes[i];
  361. size = mode->xres * mode->yres * mach_info->bpp / 8;
  362. if (size > fb_size)
  363. fb_size = size;
  364. }
  365. }
  366. return fb_size;
  367. }
  368. static int __init ep93xxfb_alloc_videomem(struct fb_info *info)
  369. {
  370. struct ep93xx_fbi *fbi = info->par;
  371. char __iomem *virt_addr;
  372. dma_addr_t phys_addr;
  373. unsigned int fb_size;
  374. fb_size = ep93xxfb_calc_fbsize(fbi->mach_info);
  375. virt_addr = dma_alloc_writecombine(info->dev, fb_size,
  376. &phys_addr, GFP_KERNEL);
  377. if (!virt_addr)
  378. return -ENOMEM;
  379. /*
  380. * There is a bug in the ep93xx framebuffer which causes problems
  381. * if bit 27 of the physical address is set.
  382. * See: http://marc.info/?l=linux-arm-kernel&m=110061245502000&w=2
  383. * There does not seem to be any official errata for this, but I
  384. * have confirmed the problem exists on my hardware (ep9315) at
  385. * least.
  386. */
  387. if (check_screenpage_bug && phys_addr & (1 << 27)) {
  388. dev_err(info->dev, "ep93xx framebuffer bug. phys addr (0x%x) "
  389. "has bit 27 set: cannot init framebuffer\n",
  390. phys_addr);
  391. dma_free_coherent(info->dev, fb_size, virt_addr, phys_addr);
  392. return -ENOMEM;
  393. }
  394. info->fix.smem_start = phys_addr;
  395. info->fix.smem_len = fb_size;
  396. info->screen_base = virt_addr;
  397. return 0;
  398. }
  399. static void ep93xxfb_dealloc_videomem(struct fb_info *info)
  400. {
  401. if (info->screen_base)
  402. dma_free_coherent(info->dev, info->fix.smem_len,
  403. info->screen_base, info->fix.smem_start);
  404. }
  405. static int __devinit ep93xxfb_probe(struct platform_device *pdev)
  406. {
  407. struct ep93xxfb_mach_info *mach_info = pdev->dev.platform_data;
  408. struct fb_info *info;
  409. struct ep93xx_fbi *fbi;
  410. struct resource *res;
  411. char *video_mode;
  412. int err;
  413. if (!mach_info)
  414. return -EINVAL;
  415. info = framebuffer_alloc(sizeof(struct ep93xx_fbi), &pdev->dev);
  416. if (!info)
  417. return -ENOMEM;
  418. info->dev = &pdev->dev;
  419. platform_set_drvdata(pdev, info);
  420. fbi = info->par;
  421. fbi->mach_info = mach_info;
  422. err = fb_alloc_cmap(&info->cmap, 256, 0);
  423. if (err)
  424. goto failed;
  425. err = ep93xxfb_alloc_videomem(info);
  426. if (err)
  427. goto failed;
  428. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  429. if (!res) {
  430. err = -ENXIO;
  431. goto failed;
  432. }
  433. res = request_mem_region(res->start, resource_size(res), pdev->name);
  434. if (!res) {
  435. err = -EBUSY;
  436. goto failed;
  437. }
  438. fbi->res = res;
  439. fbi->mmio_base = ioremap(res->start, resource_size(res));
  440. if (!fbi->mmio_base) {
  441. err = -ENXIO;
  442. goto failed;
  443. }
  444. strcpy(info->fix.id, pdev->name);
  445. info->fbops = &ep93xxfb_ops;
  446. info->fix.type = FB_TYPE_PACKED_PIXELS;
  447. info->fix.accel = FB_ACCEL_NONE;
  448. info->var.activate = FB_ACTIVATE_NOW;
  449. info->var.vmode = FB_VMODE_NONINTERLACED;
  450. info->flags = FBINFO_DEFAULT;
  451. info->node = -1;
  452. info->state = FBINFO_STATE_RUNNING;
  453. info->pseudo_palette = &fbi->pseudo_palette;
  454. fb_get_options("ep93xx-fb", &video_mode);
  455. err = fb_find_mode(&info->var, info, video_mode,
  456. fbi->mach_info->modes, fbi->mach_info->num_modes,
  457. fbi->mach_info->default_mode, fbi->mach_info->bpp);
  458. if (err == 0) {
  459. dev_err(info->dev, "No suitable video mode found\n");
  460. err = -EINVAL;
  461. goto failed;
  462. }
  463. if (mach_info->setup) {
  464. err = mach_info->setup(pdev);
  465. if (err)
  466. return err;
  467. }
  468. err = ep93xxfb_check_var(&info->var, info);
  469. if (err)
  470. goto failed;
  471. fbi->clk = clk_get(info->dev, NULL);
  472. if (IS_ERR(fbi->clk)) {
  473. err = PTR_ERR(fbi->clk);
  474. fbi->clk = NULL;
  475. goto failed;
  476. }
  477. ep93xxfb_set_par(info);
  478. clk_enable(fbi->clk);
  479. err = register_framebuffer(info);
  480. if (err)
  481. goto failed;
  482. dev_info(info->dev, "registered. Mode = %dx%d-%d\n",
  483. info->var.xres, info->var.yres, info->var.bits_per_pixel);
  484. return 0;
  485. failed:
  486. if (fbi->clk)
  487. clk_put(fbi->clk);
  488. if (fbi->mmio_base)
  489. iounmap(fbi->mmio_base);
  490. if (fbi->res)
  491. release_mem_region(fbi->res->start, resource_size(fbi->res));
  492. ep93xxfb_dealloc_videomem(info);
  493. if (&info->cmap)
  494. fb_dealloc_cmap(&info->cmap);
  495. if (fbi->mach_info->teardown)
  496. fbi->mach_info->teardown(pdev);
  497. kfree(info);
  498. platform_set_drvdata(pdev, NULL);
  499. return err;
  500. }
  501. static int __devexit ep93xxfb_remove(struct platform_device *pdev)
  502. {
  503. struct fb_info *info = platform_get_drvdata(pdev);
  504. struct ep93xx_fbi *fbi = info->par;
  505. unregister_framebuffer(info);
  506. clk_disable(fbi->clk);
  507. clk_put(fbi->clk);
  508. iounmap(fbi->mmio_base);
  509. release_mem_region(fbi->res->start, resource_size(fbi->res));
  510. ep93xxfb_dealloc_videomem(info);
  511. fb_dealloc_cmap(&info->cmap);
  512. if (fbi->mach_info->teardown)
  513. fbi->mach_info->teardown(pdev);
  514. kfree(info);
  515. platform_set_drvdata(pdev, NULL);
  516. return 0;
  517. }
  518. static struct platform_driver ep93xxfb_driver = {
  519. .probe = ep93xxfb_probe,
  520. .remove = __devexit_p(ep93xxfb_remove),
  521. .driver = {
  522. .name = "ep93xx-fb",
  523. .owner = THIS_MODULE,
  524. },
  525. };
  526. static int __devinit ep93xxfb_init(void)
  527. {
  528. return platform_driver_register(&ep93xxfb_driver);
  529. }
  530. static void __exit ep93xxfb_exit(void)
  531. {
  532. platform_driver_unregister(&ep93xxfb_driver);
  533. }
  534. module_init(ep93xxfb_init);
  535. module_exit(ep93xxfb_exit);
  536. MODULE_DESCRIPTION("EP93XX Framebuffer Driver");
  537. MODULE_ALIAS("platform:ep93xx-fb");
  538. MODULE_AUTHOR("Ryan Mallon <ryan&bluewatersys.com>, "
  539. "H Hartley Sweeten <hsweeten@visionengravers.com");
  540. MODULE_LICENSE("GPL");