yam.c 32 KB

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  1. /*****************************************************************************/
  2. /*
  3. * yam.c -- YAM radio modem driver.
  4. *
  5. * Copyright (C) 1998 Frederic Rible F1OAT (frible@teaser.fr)
  6. * Adapted from baycom.c driver written by Thomas Sailer (sailer@ife.ee.ethz.ch)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * Please note that the GPL allows you to use the driver, NOT the radio.
  23. * In order to use the radio, you need a license from the communications
  24. * authority of your country.
  25. *
  26. *
  27. * History:
  28. * 0.0 F1OAT 06.06.98 Begin of work with baycom.c source code V 0.3
  29. * 0.1 F1OAT 07.06.98 Add timer polling routine for channel arbitration
  30. * 0.2 F6FBB 08.06.98 Added delay after FPGA programming
  31. * 0.3 F6FBB 29.07.98 Delayed PTT implementation for dupmode=2
  32. * 0.4 F6FBB 30.07.98 Added TxTail, Slottime and Persistence
  33. * 0.5 F6FBB 01.08.98 Shared IRQs, /proc/net and network statistics
  34. * 0.6 F6FBB 25.08.98 Added 1200Bds format
  35. * 0.7 F6FBB 12.09.98 Added to the kernel configuration
  36. * 0.8 F6FBB 14.10.98 Fixed slottime/persistence timing bug
  37. * OK1ZIA 2.09.01 Fixed "kfree_skb on hard IRQ"
  38. * using dev_kfree_skb_any(). (important in 2.4 kernel)
  39. *
  40. */
  41. /*****************************************************************************/
  42. #include <linux/module.h>
  43. #include <linux/types.h>
  44. #include <linux/net.h>
  45. #include <linux/in.h>
  46. #include <linux/if.h>
  47. #include <linux/slab.h>
  48. #include <linux/errno.h>
  49. #include <linux/bitops.h>
  50. #include <linux/random.h>
  51. #include <asm/io.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/ioport.h>
  54. #include <linux/firmware.h>
  55. #include <linux/platform_device.h>
  56. #include <linux/netdevice.h>
  57. #include <linux/if_arp.h>
  58. #include <linux/etherdevice.h>
  59. #include <linux/skbuff.h>
  60. #include <net/ax25.h>
  61. #include <linux/kernel.h>
  62. #include <linux/proc_fs.h>
  63. #include <linux/seq_file.h>
  64. #include <net/net_namespace.h>
  65. #include <asm/uaccess.h>
  66. #include <linux/init.h>
  67. #include <linux/yam.h>
  68. /* --------------------------------------------------------------------- */
  69. static const char yam_drvname[] = "yam";
  70. static const char yam_drvinfo[] __initconst = KERN_INFO \
  71. "YAM driver version 0.8 by F1OAT/F6FBB\n";
  72. /* --------------------------------------------------------------------- */
  73. #define FIRMWARE_9600 "/*(DEBLOBBED)*/"
  74. #define FIRMWARE_1200 "/*(DEBLOBBED)*/"
  75. #define YAM_9600 1
  76. #define YAM_1200 2
  77. #define NR_PORTS 4
  78. #define YAM_MAGIC 0xF10A7654
  79. /* Transmitter states */
  80. #define TX_OFF 0
  81. #define TX_HEAD 1
  82. #define TX_DATA 2
  83. #define TX_CRC1 3
  84. #define TX_CRC2 4
  85. #define TX_TAIL 5
  86. #define YAM_MAX_FRAME 1024
  87. #define DEFAULT_BITRATE 9600 /* bps */
  88. #define DEFAULT_HOLDD 10 /* sec */
  89. #define DEFAULT_TXD 300 /* ms */
  90. #define DEFAULT_TXTAIL 10 /* ms */
  91. #define DEFAULT_SLOT 100 /* ms */
  92. #define DEFAULT_PERS 64 /* 0->255 */
  93. struct yam_port {
  94. int magic;
  95. int bitrate;
  96. int baudrate;
  97. int iobase;
  98. int irq;
  99. int dupmode;
  100. struct net_device *dev;
  101. int nb_rxint;
  102. int nb_mdint;
  103. /* Parameters section */
  104. int txd; /* tx delay */
  105. int holdd; /* duplex ptt delay */
  106. int txtail; /* txtail delay */
  107. int slot; /* slottime */
  108. int pers; /* persistence */
  109. /* Tx section */
  110. int tx_state;
  111. int tx_count;
  112. int slotcnt;
  113. unsigned char tx_buf[YAM_MAX_FRAME];
  114. int tx_len;
  115. int tx_crcl, tx_crch;
  116. struct sk_buff_head send_queue; /* Packets awaiting transmission */
  117. /* Rx section */
  118. int dcd;
  119. unsigned char rx_buf[YAM_MAX_FRAME];
  120. int rx_len;
  121. int rx_crcl, rx_crch;
  122. };
  123. struct yam_mcs {
  124. unsigned char bits[YAM_FPGA_SIZE];
  125. int bitrate;
  126. struct yam_mcs *next;
  127. };
  128. static struct net_device *yam_devs[NR_PORTS];
  129. static struct yam_mcs *yam_data;
  130. static DEFINE_TIMER(yam_timer, NULL, 0, 0);
  131. /* --------------------------------------------------------------------- */
  132. #define RBR(iobase) (iobase+0)
  133. #define THR(iobase) (iobase+0)
  134. #define IER(iobase) (iobase+1)
  135. #define IIR(iobase) (iobase+2)
  136. #define FCR(iobase) (iobase+2)
  137. #define LCR(iobase) (iobase+3)
  138. #define MCR(iobase) (iobase+4)
  139. #define LSR(iobase) (iobase+5)
  140. #define MSR(iobase) (iobase+6)
  141. #define SCR(iobase) (iobase+7)
  142. #define DLL(iobase) (iobase+0)
  143. #define DLM(iobase) (iobase+1)
  144. #define YAM_EXTENT 8
  145. /* Interrupt Identification Register Bit Masks */
  146. #define IIR_NOPEND 1
  147. #define IIR_MSR 0
  148. #define IIR_TX 2
  149. #define IIR_RX 4
  150. #define IIR_LSR 6
  151. #define IIR_TIMEOUT 12 /* Fifo mode only */
  152. #define IIR_MASK 0x0F
  153. /* Interrupt Enable Register Bit Masks */
  154. #define IER_RX 1 /* enable rx interrupt */
  155. #define IER_TX 2 /* enable tx interrupt */
  156. #define IER_LSR 4 /* enable line status interrupts */
  157. #define IER_MSR 8 /* enable modem status interrupts */
  158. /* Modem Control Register Bit Masks */
  159. #define MCR_DTR 0x01 /* DTR output */
  160. #define MCR_RTS 0x02 /* RTS output */
  161. #define MCR_OUT1 0x04 /* OUT1 output (not accessible in RS232) */
  162. #define MCR_OUT2 0x08 /* Master Interrupt enable (must be set on PCs) */
  163. #define MCR_LOOP 0x10 /* Loopback enable */
  164. /* Modem Status Register Bit Masks */
  165. #define MSR_DCTS 0x01 /* Delta CTS input */
  166. #define MSR_DDSR 0x02 /* Delta DSR */
  167. #define MSR_DRIN 0x04 /* Delta RI */
  168. #define MSR_DDCD 0x08 /* Delta DCD */
  169. #define MSR_CTS 0x10 /* CTS input */
  170. #define MSR_DSR 0x20 /* DSR input */
  171. #define MSR_RING 0x40 /* RI input */
  172. #define MSR_DCD 0x80 /* DCD input */
  173. /* line status register bit mask */
  174. #define LSR_RXC 0x01
  175. #define LSR_OE 0x02
  176. #define LSR_PE 0x04
  177. #define LSR_FE 0x08
  178. #define LSR_BREAK 0x10
  179. #define LSR_THRE 0x20
  180. #define LSR_TSRE 0x40
  181. /* Line Control Register Bit Masks */
  182. #define LCR_DLAB 0x80
  183. #define LCR_BREAK 0x40
  184. #define LCR_PZERO 0x28
  185. #define LCR_PEVEN 0x18
  186. #define LCR_PODD 0x08
  187. #define LCR_STOP1 0x00
  188. #define LCR_STOP2 0x04
  189. #define LCR_BIT5 0x00
  190. #define LCR_BIT6 0x02
  191. #define LCR_BIT7 0x01
  192. #define LCR_BIT8 0x03
  193. /* YAM Modem <-> UART Port mapping */
  194. #define TX_RDY MSR_DCTS /* transmitter ready to send */
  195. #define RX_DCD MSR_DCD /* carrier detect */
  196. #define RX_FLAG MSR_RING /* hdlc flag received */
  197. #define FPGA_DONE MSR_DSR /* FPGA is configured */
  198. #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */
  199. #define PTT_OFF (MCR_DTR|MCR_OUT2) /* release PTT */
  200. #define ENABLE_RXINT IER_RX /* enable uart rx interrupt during rx */
  201. #define ENABLE_TXINT IER_MSR /* enable uart ms interrupt during tx */
  202. #define ENABLE_RTXINT (IER_RX|IER_MSR) /* full duplex operations */
  203. /*************************************************************************
  204. * CRC Tables
  205. ************************************************************************/
  206. static const unsigned char chktabl[256] =
  207. {0x00, 0x89, 0x12, 0x9b, 0x24, 0xad, 0x36, 0xbf, 0x48, 0xc1, 0x5a, 0xd3, 0x6c, 0xe5, 0x7e,
  208. 0xf7, 0x81, 0x08, 0x93, 0x1a, 0xa5, 0x2c, 0xb7, 0x3e, 0xc9, 0x40, 0xdb, 0x52, 0xed, 0x64,
  209. 0xff, 0x76, 0x02, 0x8b, 0x10, 0x99, 0x26, 0xaf, 0x34, 0xbd, 0x4a, 0xc3, 0x58, 0xd1, 0x6e,
  210. 0xe7, 0x7c, 0xf5, 0x83, 0x0a, 0x91, 0x18, 0xa7, 0x2e, 0xb5, 0x3c, 0xcb, 0x42, 0xd9, 0x50,
  211. 0xef, 0x66, 0xfd, 0x74, 0x04, 0x8d, 0x16, 0x9f, 0x20, 0xa9, 0x32, 0xbb, 0x4c, 0xc5, 0x5e,
  212. 0xd7, 0x68, 0xe1, 0x7a, 0xf3, 0x85, 0x0c, 0x97, 0x1e, 0xa1, 0x28, 0xb3, 0x3a, 0xcd, 0x44,
  213. 0xdf, 0x56, 0xe9, 0x60, 0xfb, 0x72, 0x06, 0x8f, 0x14, 0x9d, 0x22, 0xab, 0x30, 0xb9, 0x4e,
  214. 0xc7, 0x5c, 0xd5, 0x6a, 0xe3, 0x78, 0xf1, 0x87, 0x0e, 0x95, 0x1c, 0xa3, 0x2a, 0xb1, 0x38,
  215. 0xcf, 0x46, 0xdd, 0x54, 0xeb, 0x62, 0xf9, 0x70, 0x08, 0x81, 0x1a, 0x93, 0x2c, 0xa5, 0x3e,
  216. 0xb7, 0x40, 0xc9, 0x52, 0xdb, 0x64, 0xed, 0x76, 0xff, 0x89, 0x00, 0x9b, 0x12, 0xad, 0x24,
  217. 0xbf, 0x36, 0xc1, 0x48, 0xd3, 0x5a, 0xe5, 0x6c, 0xf7, 0x7e, 0x0a, 0x83, 0x18, 0x91, 0x2e,
  218. 0xa7, 0x3c, 0xb5, 0x42, 0xcb, 0x50, 0xd9, 0x66, 0xef, 0x74, 0xfd, 0x8b, 0x02, 0x99, 0x10,
  219. 0xaf, 0x26, 0xbd, 0x34, 0xc3, 0x4a, 0xd1, 0x58, 0xe7, 0x6e, 0xf5, 0x7c, 0x0c, 0x85, 0x1e,
  220. 0x97, 0x28, 0xa1, 0x3a, 0xb3, 0x44, 0xcd, 0x56, 0xdf, 0x60, 0xe9, 0x72, 0xfb, 0x8d, 0x04,
  221. 0x9f, 0x16, 0xa9, 0x20, 0xbb, 0x32, 0xc5, 0x4c, 0xd7, 0x5e, 0xe1, 0x68, 0xf3, 0x7a, 0x0e,
  222. 0x87, 0x1c, 0x95, 0x2a, 0xa3, 0x38, 0xb1, 0x46, 0xcf, 0x54, 0xdd, 0x62, 0xeb, 0x70, 0xf9,
  223. 0x8f, 0x06, 0x9d, 0x14, 0xab, 0x22, 0xb9, 0x30, 0xc7, 0x4e, 0xd5, 0x5c, 0xe3, 0x6a, 0xf1,
  224. 0x78};
  225. static const unsigned char chktabh[256] =
  226. {0x00, 0x11, 0x23, 0x32, 0x46, 0x57, 0x65, 0x74, 0x8c, 0x9d, 0xaf, 0xbe, 0xca, 0xdb, 0xe9,
  227. 0xf8, 0x10, 0x01, 0x33, 0x22, 0x56, 0x47, 0x75, 0x64, 0x9c, 0x8d, 0xbf, 0xae, 0xda, 0xcb,
  228. 0xf9, 0xe8, 0x21, 0x30, 0x02, 0x13, 0x67, 0x76, 0x44, 0x55, 0xad, 0xbc, 0x8e, 0x9f, 0xeb,
  229. 0xfa, 0xc8, 0xd9, 0x31, 0x20, 0x12, 0x03, 0x77, 0x66, 0x54, 0x45, 0xbd, 0xac, 0x9e, 0x8f,
  230. 0xfb, 0xea, 0xd8, 0xc9, 0x42, 0x53, 0x61, 0x70, 0x04, 0x15, 0x27, 0x36, 0xce, 0xdf, 0xed,
  231. 0xfc, 0x88, 0x99, 0xab, 0xba, 0x52, 0x43, 0x71, 0x60, 0x14, 0x05, 0x37, 0x26, 0xde, 0xcf,
  232. 0xfd, 0xec, 0x98, 0x89, 0xbb, 0xaa, 0x63, 0x72, 0x40, 0x51, 0x25, 0x34, 0x06, 0x17, 0xef,
  233. 0xfe, 0xcc, 0xdd, 0xa9, 0xb8, 0x8a, 0x9b, 0x73, 0x62, 0x50, 0x41, 0x35, 0x24, 0x16, 0x07,
  234. 0xff, 0xee, 0xdc, 0xcd, 0xb9, 0xa8, 0x9a, 0x8b, 0x84, 0x95, 0xa7, 0xb6, 0xc2, 0xd3, 0xe1,
  235. 0xf0, 0x08, 0x19, 0x2b, 0x3a, 0x4e, 0x5f, 0x6d, 0x7c, 0x94, 0x85, 0xb7, 0xa6, 0xd2, 0xc3,
  236. 0xf1, 0xe0, 0x18, 0x09, 0x3b, 0x2a, 0x5e, 0x4f, 0x7d, 0x6c, 0xa5, 0xb4, 0x86, 0x97, 0xe3,
  237. 0xf2, 0xc0, 0xd1, 0x29, 0x38, 0x0a, 0x1b, 0x6f, 0x7e, 0x4c, 0x5d, 0xb5, 0xa4, 0x96, 0x87,
  238. 0xf3, 0xe2, 0xd0, 0xc1, 0x39, 0x28, 0x1a, 0x0b, 0x7f, 0x6e, 0x5c, 0x4d, 0xc6, 0xd7, 0xe5,
  239. 0xf4, 0x80, 0x91, 0xa3, 0xb2, 0x4a, 0x5b, 0x69, 0x78, 0x0c, 0x1d, 0x2f, 0x3e, 0xd6, 0xc7,
  240. 0xf5, 0xe4, 0x90, 0x81, 0xb3, 0xa2, 0x5a, 0x4b, 0x79, 0x68, 0x1c, 0x0d, 0x3f, 0x2e, 0xe7,
  241. 0xf6, 0xc4, 0xd5, 0xa1, 0xb0, 0x82, 0x93, 0x6b, 0x7a, 0x48, 0x59, 0x2d, 0x3c, 0x0e, 0x1f,
  242. 0xf7, 0xe6, 0xd4, 0xc5, 0xb1, 0xa0, 0x92, 0x83, 0x7b, 0x6a, 0x58, 0x49, 0x3d, 0x2c, 0x1e,
  243. 0x0f};
  244. /*************************************************************************
  245. * FPGA functions
  246. ************************************************************************/
  247. static void delay(int ms)
  248. {
  249. unsigned long timeout = jiffies + ((ms * HZ) / 1000);
  250. while (time_before(jiffies, timeout))
  251. cpu_relax();
  252. }
  253. /*
  254. * reset FPGA
  255. */
  256. static void fpga_reset(int iobase)
  257. {
  258. outb(0, IER(iobase));
  259. outb(LCR_DLAB | LCR_BIT5, LCR(iobase));
  260. outb(1, DLL(iobase));
  261. outb(0, DLM(iobase));
  262. outb(LCR_BIT5, LCR(iobase));
  263. inb(LSR(iobase));
  264. inb(MSR(iobase));
  265. /* turn off FPGA supply voltage */
  266. outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));
  267. delay(100);
  268. /* turn on FPGA supply voltage again */
  269. outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));
  270. delay(100);
  271. }
  272. /*
  273. * send one byte to FPGA
  274. */
  275. static int fpga_write(int iobase, unsigned char wrd)
  276. {
  277. unsigned char bit;
  278. int k;
  279. unsigned long timeout = jiffies + HZ / 10;
  280. for (k = 0; k < 8; k++) {
  281. bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR;
  282. outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));
  283. wrd <<= 1;
  284. outb(0xfc, THR(iobase));
  285. while ((inb(LSR(iobase)) & LSR_TSRE) == 0)
  286. if (time_after(jiffies, timeout))
  287. return -1;
  288. }
  289. return 0;
  290. }
  291. /*
  292. * predef should be 0 for loading user defined mcs
  293. * predef should be YAM_1200 for loading predef 1200 mcs
  294. * predef should be YAM_9600 for loading predef 9600 mcs
  295. */
  296. static unsigned char *add_mcs(unsigned char *bits, int bitrate,
  297. unsigned int predef)
  298. {
  299. const char *fw_name[2] = {FIRMWARE_9600, FIRMWARE_1200};
  300. const struct firmware *fw;
  301. struct platform_device *pdev;
  302. struct yam_mcs *p;
  303. int err;
  304. switch (predef) {
  305. case 0:
  306. fw = NULL;
  307. break;
  308. case YAM_1200:
  309. case YAM_9600:
  310. predef--;
  311. pdev = platform_device_register_simple("yam", 0, NULL, 0);
  312. if (IS_ERR(pdev)) {
  313. printk(KERN_ERR "yam: Failed to register firmware\n");
  314. return NULL;
  315. }
  316. err = reject_firmware(&fw, fw_name[predef], &pdev->dev);
  317. platform_device_unregister(pdev);
  318. if (err) {
  319. printk(KERN_ERR "Failed to load firmware \"%s\"\n",
  320. fw_name[predef]);
  321. return NULL;
  322. }
  323. if (fw->size != YAM_FPGA_SIZE) {
  324. printk(KERN_ERR "Bogus length %zu in firmware \"%s\"\n",
  325. fw->size, fw_name[predef]);
  326. release_firmware(fw);
  327. return NULL;
  328. }
  329. bits = (unsigned char *)fw->data;
  330. break;
  331. default:
  332. printk(KERN_ERR "yam: Invalid predef number %u\n", predef);
  333. return NULL;
  334. }
  335. /* If it already exists, replace the bit data */
  336. p = yam_data;
  337. while (p) {
  338. if (p->bitrate == bitrate) {
  339. memcpy(p->bits, bits, YAM_FPGA_SIZE);
  340. goto out;
  341. }
  342. p = p->next;
  343. }
  344. /* Allocate a new mcs */
  345. if ((p = kmalloc(sizeof(struct yam_mcs), GFP_KERNEL)) == NULL) {
  346. release_firmware(fw);
  347. return NULL;
  348. }
  349. memcpy(p->bits, bits, YAM_FPGA_SIZE);
  350. p->bitrate = bitrate;
  351. p->next = yam_data;
  352. yam_data = p;
  353. out:
  354. release_firmware(fw);
  355. return p->bits;
  356. }
  357. static unsigned char *get_mcs(int bitrate)
  358. {
  359. struct yam_mcs *p;
  360. p = yam_data;
  361. while (p) {
  362. if (p->bitrate == bitrate)
  363. return p->bits;
  364. p = p->next;
  365. }
  366. /* Load predefined mcs data */
  367. switch (bitrate) {
  368. case 1200:
  369. /* setting predef as YAM_1200 for loading predef 1200 mcs */
  370. return add_mcs(NULL, bitrate, YAM_1200);
  371. default:
  372. /* setting predef as YAM_9600 for loading predef 9600 mcs */
  373. return add_mcs(NULL, bitrate, YAM_9600);
  374. }
  375. }
  376. /*
  377. * download bitstream to FPGA
  378. * data is contained in bits[] array in yam1200.h resp. yam9600.h
  379. */
  380. static int fpga_download(int iobase, int bitrate)
  381. {
  382. int i, rc;
  383. unsigned char *pbits;
  384. pbits = get_mcs(bitrate);
  385. if (pbits == NULL)
  386. return -1;
  387. fpga_reset(iobase);
  388. for (i = 0; i < YAM_FPGA_SIZE; i++) {
  389. if (fpga_write(iobase, pbits[i])) {
  390. printk(KERN_ERR "yam: error in write cycle\n");
  391. return -1; /* write... */
  392. }
  393. }
  394. fpga_write(iobase, 0xFF);
  395. rc = inb(MSR(iobase)); /* check DONE signal */
  396. /* Needed for some hardwares */
  397. delay(50);
  398. return (rc & MSR_DSR) ? 0 : -1;
  399. }
  400. /************************************************************************
  401. * Serial port init
  402. ************************************************************************/
  403. static void yam_set_uart(struct net_device *dev)
  404. {
  405. struct yam_port *yp = netdev_priv(dev);
  406. int divisor = 115200 / yp->baudrate;
  407. outb(0, IER(dev->base_addr));
  408. outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));
  409. outb(divisor, DLL(dev->base_addr));
  410. outb(0, DLM(dev->base_addr));
  411. outb(LCR_BIT8, LCR(dev->base_addr));
  412. outb(PTT_OFF, MCR(dev->base_addr));
  413. outb(0x00, FCR(dev->base_addr));
  414. /* Flush pending irq */
  415. inb(RBR(dev->base_addr));
  416. inb(MSR(dev->base_addr));
  417. /* Enable rx irq */
  418. outb(ENABLE_RTXINT, IER(dev->base_addr));
  419. }
  420. /* --------------------------------------------------------------------- */
  421. enum uart {
  422. c_uart_unknown, c_uart_8250,
  423. c_uart_16450, c_uart_16550, c_uart_16550A
  424. };
  425. static const char *uart_str[] =
  426. {"unknown", "8250", "16450", "16550", "16550A"};
  427. static enum uart yam_check_uart(unsigned int iobase)
  428. {
  429. unsigned char b1, b2, b3;
  430. enum uart u;
  431. enum uart uart_tab[] =
  432. {c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A};
  433. b1 = inb(MCR(iobase));
  434. outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
  435. b2 = inb(MSR(iobase));
  436. outb(0x1a, MCR(iobase));
  437. b3 = inb(MSR(iobase)) & 0xf0;
  438. outb(b1, MCR(iobase)); /* restore old values */
  439. outb(b2, MSR(iobase));
  440. if (b3 != 0x90)
  441. return c_uart_unknown;
  442. inb(RBR(iobase));
  443. inb(RBR(iobase));
  444. outb(0x01, FCR(iobase)); /* enable FIFOs */
  445. u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
  446. if (u == c_uart_16450) {
  447. outb(0x5a, SCR(iobase));
  448. b1 = inb(SCR(iobase));
  449. outb(0xa5, SCR(iobase));
  450. b2 = inb(SCR(iobase));
  451. if ((b1 != 0x5a) || (b2 != 0xa5))
  452. u = c_uart_8250;
  453. }
  454. return u;
  455. }
  456. /******************************************************************************
  457. * Rx Section
  458. ******************************************************************************/
  459. static inline void yam_rx_flag(struct net_device *dev, struct yam_port *yp)
  460. {
  461. if (yp->dcd && yp->rx_len >= 3 && yp->rx_len < YAM_MAX_FRAME) {
  462. int pkt_len = yp->rx_len - 2 + 1; /* -CRC + kiss */
  463. struct sk_buff *skb;
  464. if ((yp->rx_crch & yp->rx_crcl) != 0xFF) {
  465. /* Bad crc */
  466. } else {
  467. if (!(skb = dev_alloc_skb(pkt_len))) {
  468. printk(KERN_WARNING "%s: memory squeeze, dropping packet\n", dev->name);
  469. ++dev->stats.rx_dropped;
  470. } else {
  471. unsigned char *cp;
  472. cp = skb_put(skb, pkt_len);
  473. *cp++ = 0; /* KISS kludge */
  474. memcpy(cp, yp->rx_buf, pkt_len - 1);
  475. skb->protocol = ax25_type_trans(skb, dev);
  476. netif_rx(skb);
  477. ++dev->stats.rx_packets;
  478. }
  479. }
  480. }
  481. yp->rx_len = 0;
  482. yp->rx_crcl = 0x21;
  483. yp->rx_crch = 0xf3;
  484. }
  485. static inline void yam_rx_byte(struct net_device *dev, struct yam_port *yp, unsigned char rxb)
  486. {
  487. if (yp->rx_len < YAM_MAX_FRAME) {
  488. unsigned char c = yp->rx_crcl;
  489. yp->rx_crcl = (chktabl[c] ^ yp->rx_crch);
  490. yp->rx_crch = (chktabh[c] ^ rxb);
  491. yp->rx_buf[yp->rx_len++] = rxb;
  492. }
  493. }
  494. /********************************************************************************
  495. * TX Section
  496. ********************************************************************************/
  497. static void ptt_on(struct net_device *dev)
  498. {
  499. outb(PTT_ON, MCR(dev->base_addr));
  500. }
  501. static void ptt_off(struct net_device *dev)
  502. {
  503. outb(PTT_OFF, MCR(dev->base_addr));
  504. }
  505. static netdev_tx_t yam_send_packet(struct sk_buff *skb,
  506. struct net_device *dev)
  507. {
  508. struct yam_port *yp = netdev_priv(dev);
  509. if (skb->protocol == htons(ETH_P_IP))
  510. return ax25_ip_xmit(skb);
  511. skb_queue_tail(&yp->send_queue, skb);
  512. netif_trans_update(dev);
  513. return NETDEV_TX_OK;
  514. }
  515. static void yam_start_tx(struct net_device *dev, struct yam_port *yp)
  516. {
  517. if ((yp->tx_state == TX_TAIL) || (yp->txd == 0))
  518. yp->tx_count = 1;
  519. else
  520. yp->tx_count = (yp->bitrate * yp->txd) / 8000;
  521. yp->tx_state = TX_HEAD;
  522. ptt_on(dev);
  523. }
  524. static void yam_arbitrate(struct net_device *dev)
  525. {
  526. struct yam_port *yp = netdev_priv(dev);
  527. if (yp->magic != YAM_MAGIC || yp->tx_state != TX_OFF ||
  528. skb_queue_empty(&yp->send_queue))
  529. return;
  530. /* tx_state is TX_OFF and there is data to send */
  531. if (yp->dupmode) {
  532. /* Full duplex mode, don't wait */
  533. yam_start_tx(dev, yp);
  534. return;
  535. }
  536. if (yp->dcd) {
  537. /* DCD on, wait slotime ... */
  538. yp->slotcnt = yp->slot / 10;
  539. return;
  540. }
  541. /* Is slottime passed ? */
  542. if ((--yp->slotcnt) > 0)
  543. return;
  544. yp->slotcnt = yp->slot / 10;
  545. /* is random > persist ? */
  546. if ((prandom_u32() % 256) > yp->pers)
  547. return;
  548. yam_start_tx(dev, yp);
  549. }
  550. static void yam_dotimer(unsigned long dummy)
  551. {
  552. int i;
  553. for (i = 0; i < NR_PORTS; i++) {
  554. struct net_device *dev = yam_devs[i];
  555. if (dev && netif_running(dev))
  556. yam_arbitrate(dev);
  557. }
  558. yam_timer.expires = jiffies + HZ / 100;
  559. add_timer(&yam_timer);
  560. }
  561. static void yam_tx_byte(struct net_device *dev, struct yam_port *yp)
  562. {
  563. struct sk_buff *skb;
  564. unsigned char b, temp;
  565. switch (yp->tx_state) {
  566. case TX_OFF:
  567. break;
  568. case TX_HEAD:
  569. if (--yp->tx_count <= 0) {
  570. if (!(skb = skb_dequeue(&yp->send_queue))) {
  571. ptt_off(dev);
  572. yp->tx_state = TX_OFF;
  573. break;
  574. }
  575. yp->tx_state = TX_DATA;
  576. if (skb->data[0] != 0) {
  577. /* do_kiss_params(s, skb->data, skb->len); */
  578. dev_kfree_skb_any(skb);
  579. break;
  580. }
  581. yp->tx_len = skb->len - 1; /* strip KISS byte */
  582. if (yp->tx_len >= YAM_MAX_FRAME || yp->tx_len < 2) {
  583. dev_kfree_skb_any(skb);
  584. break;
  585. }
  586. skb_copy_from_linear_data_offset(skb, 1,
  587. yp->tx_buf,
  588. yp->tx_len);
  589. dev_kfree_skb_any(skb);
  590. yp->tx_count = 0;
  591. yp->tx_crcl = 0x21;
  592. yp->tx_crch = 0xf3;
  593. yp->tx_state = TX_DATA;
  594. }
  595. break;
  596. case TX_DATA:
  597. b = yp->tx_buf[yp->tx_count++];
  598. outb(b, THR(dev->base_addr));
  599. temp = yp->tx_crcl;
  600. yp->tx_crcl = chktabl[temp] ^ yp->tx_crch;
  601. yp->tx_crch = chktabh[temp] ^ b;
  602. if (yp->tx_count >= yp->tx_len) {
  603. yp->tx_state = TX_CRC1;
  604. }
  605. break;
  606. case TX_CRC1:
  607. yp->tx_crch = chktabl[yp->tx_crcl] ^ yp->tx_crch;
  608. yp->tx_crcl = chktabh[yp->tx_crcl] ^ chktabl[yp->tx_crch] ^ 0xff;
  609. outb(yp->tx_crcl, THR(dev->base_addr));
  610. yp->tx_state = TX_CRC2;
  611. break;
  612. case TX_CRC2:
  613. outb(chktabh[yp->tx_crch] ^ 0xFF, THR(dev->base_addr));
  614. if (skb_queue_empty(&yp->send_queue)) {
  615. yp->tx_count = (yp->bitrate * yp->txtail) / 8000;
  616. if (yp->dupmode == 2)
  617. yp->tx_count += (yp->bitrate * yp->holdd) / 8;
  618. if (yp->tx_count == 0)
  619. yp->tx_count = 1;
  620. yp->tx_state = TX_TAIL;
  621. } else {
  622. yp->tx_count = 1;
  623. yp->tx_state = TX_HEAD;
  624. }
  625. ++dev->stats.tx_packets;
  626. break;
  627. case TX_TAIL:
  628. if (--yp->tx_count <= 0) {
  629. yp->tx_state = TX_OFF;
  630. ptt_off(dev);
  631. }
  632. break;
  633. }
  634. }
  635. /***********************************************************************************
  636. * ISR routine
  637. ************************************************************************************/
  638. static irqreturn_t yam_interrupt(int irq, void *dev_id)
  639. {
  640. struct net_device *dev;
  641. struct yam_port *yp;
  642. unsigned char iir;
  643. int counter = 100;
  644. int i;
  645. int handled = 0;
  646. for (i = 0; i < NR_PORTS; i++) {
  647. dev = yam_devs[i];
  648. yp = netdev_priv(dev);
  649. if (!netif_running(dev))
  650. continue;
  651. while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) {
  652. unsigned char msr = inb(MSR(dev->base_addr));
  653. unsigned char lsr = inb(LSR(dev->base_addr));
  654. unsigned char rxb;
  655. handled = 1;
  656. if (lsr & LSR_OE)
  657. ++dev->stats.rx_fifo_errors;
  658. yp->dcd = (msr & RX_DCD) ? 1 : 0;
  659. if (--counter <= 0) {
  660. printk(KERN_ERR "%s: too many irq iir=%d\n",
  661. dev->name, iir);
  662. goto out;
  663. }
  664. if (msr & TX_RDY) {
  665. ++yp->nb_mdint;
  666. yam_tx_byte(dev, yp);
  667. }
  668. if (lsr & LSR_RXC) {
  669. ++yp->nb_rxint;
  670. rxb = inb(RBR(dev->base_addr));
  671. if (msr & RX_FLAG)
  672. yam_rx_flag(dev, yp);
  673. else
  674. yam_rx_byte(dev, yp, rxb);
  675. }
  676. }
  677. }
  678. out:
  679. return IRQ_RETVAL(handled);
  680. }
  681. #ifdef CONFIG_PROC_FS
  682. static void *yam_seq_start(struct seq_file *seq, loff_t *pos)
  683. {
  684. return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
  685. }
  686. static void *yam_seq_next(struct seq_file *seq, void *v, loff_t *pos)
  687. {
  688. ++*pos;
  689. return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
  690. }
  691. static void yam_seq_stop(struct seq_file *seq, void *v)
  692. {
  693. }
  694. static int yam_seq_show(struct seq_file *seq, void *v)
  695. {
  696. struct net_device *dev = v;
  697. const struct yam_port *yp = netdev_priv(dev);
  698. seq_printf(seq, "Device %s\n", dev->name);
  699. seq_printf(seq, " Up %d\n", netif_running(dev));
  700. seq_printf(seq, " Speed %u\n", yp->bitrate);
  701. seq_printf(seq, " IoBase 0x%x\n", yp->iobase);
  702. seq_printf(seq, " BaudRate %u\n", yp->baudrate);
  703. seq_printf(seq, " IRQ %u\n", yp->irq);
  704. seq_printf(seq, " TxState %u\n", yp->tx_state);
  705. seq_printf(seq, " Duplex %u\n", yp->dupmode);
  706. seq_printf(seq, " HoldDly %u\n", yp->holdd);
  707. seq_printf(seq, " TxDelay %u\n", yp->txd);
  708. seq_printf(seq, " TxTail %u\n", yp->txtail);
  709. seq_printf(seq, " SlotTime %u\n", yp->slot);
  710. seq_printf(seq, " Persist %u\n", yp->pers);
  711. seq_printf(seq, " TxFrames %lu\n", dev->stats.tx_packets);
  712. seq_printf(seq, " RxFrames %lu\n", dev->stats.rx_packets);
  713. seq_printf(seq, " TxInt %u\n", yp->nb_mdint);
  714. seq_printf(seq, " RxInt %u\n", yp->nb_rxint);
  715. seq_printf(seq, " RxOver %lu\n", dev->stats.rx_fifo_errors);
  716. seq_printf(seq, "\n");
  717. return 0;
  718. }
  719. static const struct seq_operations yam_seqops = {
  720. .start = yam_seq_start,
  721. .next = yam_seq_next,
  722. .stop = yam_seq_stop,
  723. .show = yam_seq_show,
  724. };
  725. static int yam_info_open(struct inode *inode, struct file *file)
  726. {
  727. return seq_open(file, &yam_seqops);
  728. }
  729. static const struct file_operations yam_info_fops = {
  730. .owner = THIS_MODULE,
  731. .open = yam_info_open,
  732. .read = seq_read,
  733. .llseek = seq_lseek,
  734. .release = seq_release,
  735. };
  736. #endif
  737. /* --------------------------------------------------------------------- */
  738. static int yam_open(struct net_device *dev)
  739. {
  740. struct yam_port *yp = netdev_priv(dev);
  741. enum uart u;
  742. int i;
  743. int ret=0;
  744. printk(KERN_INFO "Trying %s at iobase 0x%lx irq %u\n", dev->name, dev->base_addr, dev->irq);
  745. if (!yp->bitrate)
  746. return -ENXIO;
  747. if (!dev->base_addr || dev->base_addr > 0x1000 - YAM_EXTENT ||
  748. dev->irq < 2 || dev->irq > 15) {
  749. return -ENXIO;
  750. }
  751. if (!request_region(dev->base_addr, YAM_EXTENT, dev->name))
  752. {
  753. printk(KERN_ERR "%s: cannot 0x%lx busy\n", dev->name, dev->base_addr);
  754. return -EACCES;
  755. }
  756. if ((u = yam_check_uart(dev->base_addr)) == c_uart_unknown) {
  757. printk(KERN_ERR "%s: cannot find uart type\n", dev->name);
  758. ret = -EIO;
  759. goto out_release_base;
  760. }
  761. if (fpga_download(dev->base_addr, yp->bitrate)) {
  762. printk(KERN_ERR "%s: cannot init FPGA\n", dev->name);
  763. ret = -EIO;
  764. goto out_release_base;
  765. }
  766. outb(0, IER(dev->base_addr));
  767. if (request_irq(dev->irq, yam_interrupt, IRQF_SHARED, dev->name, dev)) {
  768. printk(KERN_ERR "%s: irq %d busy\n", dev->name, dev->irq);
  769. ret = -EBUSY;
  770. goto out_release_base;
  771. }
  772. yam_set_uart(dev);
  773. netif_start_queue(dev);
  774. yp->slotcnt = yp->slot / 10;
  775. /* Reset overruns for all ports - FPGA programming makes overruns */
  776. for (i = 0; i < NR_PORTS; i++) {
  777. struct net_device *yam_dev = yam_devs[i];
  778. inb(LSR(yam_dev->base_addr));
  779. yam_dev->stats.rx_fifo_errors = 0;
  780. }
  781. printk(KERN_INFO "%s at iobase 0x%lx irq %u uart %s\n", dev->name, dev->base_addr, dev->irq,
  782. uart_str[u]);
  783. return 0;
  784. out_release_base:
  785. release_region(dev->base_addr, YAM_EXTENT);
  786. return ret;
  787. }
  788. /* --------------------------------------------------------------------- */
  789. static int yam_close(struct net_device *dev)
  790. {
  791. struct sk_buff *skb;
  792. struct yam_port *yp = netdev_priv(dev);
  793. if (!dev)
  794. return -EINVAL;
  795. /*
  796. * disable interrupts
  797. */
  798. outb(0, IER(dev->base_addr));
  799. outb(1, MCR(dev->base_addr));
  800. /* Remove IRQ handler if last */
  801. free_irq(dev->irq,dev);
  802. release_region(dev->base_addr, YAM_EXTENT);
  803. netif_stop_queue(dev);
  804. while ((skb = skb_dequeue(&yp->send_queue)))
  805. dev_kfree_skb(skb);
  806. printk(KERN_INFO "%s: close yam at iobase 0x%lx irq %u\n",
  807. yam_drvname, dev->base_addr, dev->irq);
  808. return 0;
  809. }
  810. /* --------------------------------------------------------------------- */
  811. static int yam_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  812. {
  813. struct yam_port *yp = netdev_priv(dev);
  814. struct yamdrv_ioctl_cfg yi;
  815. struct yamdrv_ioctl_mcs *ym;
  816. int ioctl_cmd;
  817. if (copy_from_user(&ioctl_cmd, ifr->ifr_data, sizeof(int)))
  818. return -EFAULT;
  819. if (yp->magic != YAM_MAGIC)
  820. return -EINVAL;
  821. if (!capable(CAP_NET_ADMIN))
  822. return -EPERM;
  823. if (cmd != SIOCDEVPRIVATE)
  824. return -EINVAL;
  825. switch (ioctl_cmd) {
  826. case SIOCYAMRESERVED:
  827. return -EINVAL; /* unused */
  828. case SIOCYAMSMCS:
  829. if (netif_running(dev))
  830. return -EINVAL; /* Cannot change this parameter when up */
  831. if ((ym = kmalloc(sizeof(struct yamdrv_ioctl_mcs), GFP_KERNEL)) == NULL)
  832. return -ENOBUFS;
  833. if (copy_from_user(ym, ifr->ifr_data, sizeof(struct yamdrv_ioctl_mcs))) {
  834. kfree(ym);
  835. return -EFAULT;
  836. }
  837. if (ym->bitrate > YAM_MAXBITRATE) {
  838. kfree(ym);
  839. return -EINVAL;
  840. }
  841. /* setting predef as 0 for loading userdefined mcs data */
  842. add_mcs(ym->bits, ym->bitrate, 0);
  843. kfree(ym);
  844. break;
  845. case SIOCYAMSCFG:
  846. if (!capable(CAP_SYS_RAWIO))
  847. return -EPERM;
  848. if (copy_from_user(&yi, ifr->ifr_data, sizeof(struct yamdrv_ioctl_cfg)))
  849. return -EFAULT;
  850. if ((yi.cfg.mask & YAM_IOBASE) && netif_running(dev))
  851. return -EINVAL; /* Cannot change this parameter when up */
  852. if ((yi.cfg.mask & YAM_IRQ) && netif_running(dev))
  853. return -EINVAL; /* Cannot change this parameter when up */
  854. if ((yi.cfg.mask & YAM_BITRATE) && netif_running(dev))
  855. return -EINVAL; /* Cannot change this parameter when up */
  856. if ((yi.cfg.mask & YAM_BAUDRATE) && netif_running(dev))
  857. return -EINVAL; /* Cannot change this parameter when up */
  858. if (yi.cfg.mask & YAM_IOBASE) {
  859. yp->iobase = yi.cfg.iobase;
  860. dev->base_addr = yi.cfg.iobase;
  861. }
  862. if (yi.cfg.mask & YAM_IRQ) {
  863. if (yi.cfg.irq > 15)
  864. return -EINVAL;
  865. yp->irq = yi.cfg.irq;
  866. dev->irq = yi.cfg.irq;
  867. }
  868. if (yi.cfg.mask & YAM_BITRATE) {
  869. if (yi.cfg.bitrate > YAM_MAXBITRATE)
  870. return -EINVAL;
  871. yp->bitrate = yi.cfg.bitrate;
  872. }
  873. if (yi.cfg.mask & YAM_BAUDRATE) {
  874. if (yi.cfg.baudrate > YAM_MAXBAUDRATE)
  875. return -EINVAL;
  876. yp->baudrate = yi.cfg.baudrate;
  877. }
  878. if (yi.cfg.mask & YAM_MODE) {
  879. if (yi.cfg.mode > YAM_MAXMODE)
  880. return -EINVAL;
  881. yp->dupmode = yi.cfg.mode;
  882. }
  883. if (yi.cfg.mask & YAM_HOLDDLY) {
  884. if (yi.cfg.holddly > YAM_MAXHOLDDLY)
  885. return -EINVAL;
  886. yp->holdd = yi.cfg.holddly;
  887. }
  888. if (yi.cfg.mask & YAM_TXDELAY) {
  889. if (yi.cfg.txdelay > YAM_MAXTXDELAY)
  890. return -EINVAL;
  891. yp->txd = yi.cfg.txdelay;
  892. }
  893. if (yi.cfg.mask & YAM_TXTAIL) {
  894. if (yi.cfg.txtail > YAM_MAXTXTAIL)
  895. return -EINVAL;
  896. yp->txtail = yi.cfg.txtail;
  897. }
  898. if (yi.cfg.mask & YAM_PERSIST) {
  899. if (yi.cfg.persist > YAM_MAXPERSIST)
  900. return -EINVAL;
  901. yp->pers = yi.cfg.persist;
  902. }
  903. if (yi.cfg.mask & YAM_SLOTTIME) {
  904. if (yi.cfg.slottime > YAM_MAXSLOTTIME)
  905. return -EINVAL;
  906. yp->slot = yi.cfg.slottime;
  907. yp->slotcnt = yp->slot / 10;
  908. }
  909. break;
  910. case SIOCYAMGCFG:
  911. memset(&yi, 0, sizeof(yi));
  912. yi.cfg.mask = 0xffffffff;
  913. yi.cfg.iobase = yp->iobase;
  914. yi.cfg.irq = yp->irq;
  915. yi.cfg.bitrate = yp->bitrate;
  916. yi.cfg.baudrate = yp->baudrate;
  917. yi.cfg.mode = yp->dupmode;
  918. yi.cfg.txdelay = yp->txd;
  919. yi.cfg.holddly = yp->holdd;
  920. yi.cfg.txtail = yp->txtail;
  921. yi.cfg.persist = yp->pers;
  922. yi.cfg.slottime = yp->slot;
  923. if (copy_to_user(ifr->ifr_data, &yi, sizeof(struct yamdrv_ioctl_cfg)))
  924. return -EFAULT;
  925. break;
  926. default:
  927. return -EINVAL;
  928. }
  929. return 0;
  930. }
  931. /* --------------------------------------------------------------------- */
  932. static int yam_set_mac_address(struct net_device *dev, void *addr)
  933. {
  934. struct sockaddr *sa = (struct sockaddr *) addr;
  935. /* addr is an AX.25 shifted ASCII mac address */
  936. memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
  937. return 0;
  938. }
  939. /* --------------------------------------------------------------------- */
  940. static const struct net_device_ops yam_netdev_ops = {
  941. .ndo_open = yam_open,
  942. .ndo_stop = yam_close,
  943. .ndo_start_xmit = yam_send_packet,
  944. .ndo_do_ioctl = yam_ioctl,
  945. .ndo_set_mac_address = yam_set_mac_address,
  946. };
  947. static void yam_setup(struct net_device *dev)
  948. {
  949. struct yam_port *yp = netdev_priv(dev);
  950. yp->magic = YAM_MAGIC;
  951. yp->bitrate = DEFAULT_BITRATE;
  952. yp->baudrate = DEFAULT_BITRATE * 2;
  953. yp->iobase = 0;
  954. yp->irq = 0;
  955. yp->dupmode = 0;
  956. yp->holdd = DEFAULT_HOLDD;
  957. yp->txd = DEFAULT_TXD;
  958. yp->txtail = DEFAULT_TXTAIL;
  959. yp->slot = DEFAULT_SLOT;
  960. yp->pers = DEFAULT_PERS;
  961. yp->dev = dev;
  962. dev->base_addr = yp->iobase;
  963. dev->irq = yp->irq;
  964. skb_queue_head_init(&yp->send_queue);
  965. dev->netdev_ops = &yam_netdev_ops;
  966. dev->header_ops = &ax25_header_ops;
  967. dev->type = ARPHRD_AX25;
  968. dev->hard_header_len = AX25_MAX_HEADER_LEN;
  969. dev->mtu = AX25_MTU;
  970. dev->addr_len = AX25_ADDR_LEN;
  971. memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
  972. memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
  973. }
  974. static int __init yam_init_driver(void)
  975. {
  976. struct net_device *dev;
  977. int i, err;
  978. char name[IFNAMSIZ];
  979. printk(yam_drvinfo);
  980. for (i = 0; i < NR_PORTS; i++) {
  981. sprintf(name, "yam%d", i);
  982. dev = alloc_netdev(sizeof(struct yam_port), name,
  983. NET_NAME_UNKNOWN, yam_setup);
  984. if (!dev) {
  985. pr_err("yam: cannot allocate net device\n");
  986. err = -ENOMEM;
  987. goto error;
  988. }
  989. err = register_netdev(dev);
  990. if (err) {
  991. printk(KERN_WARNING "yam: cannot register net device %s\n", dev->name);
  992. goto error;
  993. }
  994. yam_devs[i] = dev;
  995. }
  996. yam_timer.function = yam_dotimer;
  997. yam_timer.expires = jiffies + HZ / 100;
  998. add_timer(&yam_timer);
  999. proc_create("yam", S_IRUGO, init_net.proc_net, &yam_info_fops);
  1000. return 0;
  1001. error:
  1002. while (--i >= 0) {
  1003. unregister_netdev(yam_devs[i]);
  1004. free_netdev(yam_devs[i]);
  1005. }
  1006. return err;
  1007. }
  1008. /* --------------------------------------------------------------------- */
  1009. static void __exit yam_cleanup_driver(void)
  1010. {
  1011. struct yam_mcs *p;
  1012. int i;
  1013. del_timer_sync(&yam_timer);
  1014. for (i = 0; i < NR_PORTS; i++) {
  1015. struct net_device *dev = yam_devs[i];
  1016. if (dev) {
  1017. unregister_netdev(dev);
  1018. free_netdev(dev);
  1019. }
  1020. }
  1021. while (yam_data) {
  1022. p = yam_data;
  1023. yam_data = yam_data->next;
  1024. kfree(p);
  1025. }
  1026. remove_proc_entry("yam", init_net.proc_net);
  1027. }
  1028. /* --------------------------------------------------------------------- */
  1029. MODULE_AUTHOR("Frederic Rible F1OAT frible@teaser.fr");
  1030. MODULE_DESCRIPTION("Yam amateur radio modem driver");
  1031. MODULE_LICENSE("GPL");
  1032. /*(DEBLOBBED)*/
  1033. module_init(yam_init_driver);
  1034. module_exit(yam_cleanup_driver);
  1035. /* --------------------------------------------------------------------- */